JPH0137890B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code transmission device, and particularly to a code transmission device suitable for a transmission line with large transmission loss in low frequency components.

Conventionally, there has been a device of this type as shown in FIG. In the figure, 1 is a biphase encoding circuit, 2 is a modulator, 3 is a transmission path, 4 is a demodulator, 5 is a 1/2 frequency divider, 6 is a phase switch, and 7 is a code detector.

Figure 2 is a waveform diagram showing the waveforms of each part in Figure 1.
Figure 2 a, b, c, d, e are in Figure 1 a, b,
The waveforms of each signal are shown as c, d, and e.

Next, the operation of the circuit shown in FIG. 1 will be explained using FIG. 2. In Figure 2, the time interval between the vertical dotted lines is T
During this time, 1-bit NRZ (non-
(return to zero) sign shall be included. FIG. 2e shows the transmission data to be sent, and is composed of an NRZ code with a 1-bit cycle of T. Let A be the logic of this 1-bit NRZ code. (A is “H”
The biphase encoding circuit 1 inputs a 1-bit NRZ code with period T logic A, and inputs a 1-bit NRZ code with period T/2 and logic A or A (second
Since it outputs a 2-bit NRZ code (A in the case of the figure), the output of the biphasic encoding circuit 1 has the waveform shown in Figure 2a, and passes through the modulator 2, transmission line 3, and demodulator 4 to the demodulator. If we ignore the distortion and time delay caused by transmission, the output a of 4 is also as shown in Figure 2 a.
The result will be as shown in . This waveform is input to the sign detector 7, and on the other hand, from this waveform, the period T/2
A pulse train is generated and input to the frequency divider 5. The frequency divider 5 generates pulse trains b and c of a period T having a phase difference of T/2 from the pulse train of T/2. The phase switch 6 switches and outputs the pulse trains b and c, and the code detector 7 detects the code.

By the way, since the pulse trains b and c are generated by the frequency divider 5, it is not determined which pulse train comes in the first half of the period T. In the example shown in Figure 2, pulse train b comes in the first half of period T and pulse train c comes in the second half, so the signal logic at the point of pulse train b is "L" and the signal logic at the point of the next pulse train c. is “H”
If so, the signal logic is "H", and if the signal logic at the point of pulse train b is "H" and the signal logic at the point of the next pulse train c is "L", the signal logic is "L". , and an output as shown in FIG. 2d can be obtained as the output of the sign detector 7. In this case, if the signal logic at the point of pulse train b is the same as the signal logic at the point of the next pulse train c, it can be determined that there is an error. it is,
This is because 1 bit of period T logic A is sent as 2 bits of period T/2 logic A, so the first half and second half of period T will never have the same logic.
This allows code errors to be removed. However, as mentioned above, the pulse train b does not necessarily come in the first half of the period T. If pulse train b comes in the latter half of period T, and the next pulse train c comes in the first half of the next period, as is clear from FIG. 2a, the signal logic at the time of pulse train b and the next pulse train c The signal logic at the time of may match. When such a coincidence is detected, the outputs of the pulse trains b and c are switched in the phase switch 6 by a switching signal from the code detector 7.

Transmission distortion occurs due to the characteristics of the transmission line 3, and the signal that is a rectangular wave as shown in Figure 2a at the output of the biphasic encoding circuit 1 becomes a distorted waveform at the output point of the demodulator 4. .

FIG. 3 is an eye pattern diagram showing an example of the shape of a code bit that has been distorted by the transmission line 3. The distortion caused by the transmission line 3 can be caused by blocking high frequency components or by blocking low frequency components. It is well known that the value of period T/2 must be determined according to the characteristics of the transmission line 3 in order to prevent code errors caused by distortion caused by cutting off high frequency components. It's a place. On the other hand, cutting off low frequency components may cause signal sag, which may result in code errors. Sag increases the longer the time that signals have the same logic, and in the circuit shown in Figure 1, this time does not exceed the period T, but even so, in a transmission line where the cutoff of low frequency components extends to a considerably high frequency range. There is a possibility that a code error may occur due to the sag. Furthermore, the influence of sag on the signal generated by the biphasic encoding circuit 1 is as follows:
There are fewer bits in the second half of the period T than in the first half. This is because the bits in the first half of period T may have the same logic as the bits in the second half of the previous period T, but the logic of the bits in the second half of period T is always inverted with respect to the bits in the first half. .

However, in the conventional code transmission device, the operation of the phase switch 6 is controlled and the code detector 7 performs detection, assuming that the bits in the first half and the second half of the period T are detected equally correctly. A drawback of this method is that code errors occur in transmission lines where the cut-off extends to a fairly high frequency range.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by providing a decoding circuit that utilizes only the code bits in the latter half of the period T of the signal generated through the biphase coding circuit. It is an object of the present invention to provide a code transmission device that does not generate code errors even when the low frequency characteristics of a transmission path are poor.

Embodiments of the invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing an embodiment of the present invention, where 1, 2, 3, 4, and 5 indicate the same parts as the same reference numerals as in FIG. 1, 8 is an inverter, 9 is a first flip-flop, and 10 is a second flip-flop, 11 is a first synchronization word detection circuit, 12 is a second synchronization word detection circuit, 13 is a first monostable flip-flop, 14 is a second monostable flip-flop,
15 and 16 are AND gates, and 7 is an OR gate, and the gates 15, 16, and 17 constitute a switching gate circuit 18.

5 is a waveform diagram showing the waveforms of each part of the circuit of FIG. 4, and FIG. 5 a to k represent the waveforms of each signal shown by a to k in FIG. 4. Next, the operation of the circuit shown in FIG. 4 will be explained using FIG. 5. In the embodiment described here, the periodic word is "1101", and the biphase encoding circuit 1 converts 1 bit of period T logic A into 2 bits of period T/2 logic A. In Fig. 4, the operations of parts 1, 2, 3, 4, and 5 are as explained in Fig. 1, the output of demodulator 4 is as shown in Fig. 5a, and the output of frequency divider 5 is The result is as shown in Fig. 5c and d. Since it is uncertain whether the signal c enters the second half of the period T or the signal d enters the second half of the period T, both cases are shown by solid lines and dotted lines. The case of the solid line will be explained below. Further, the signal c will be referred to as a first pulse train, and the signal d will be referred to as a second pulse train.

Inverter 8 inverts the logic of signal a and outputs signal b shown in FIG. 5b. The signal input terminal D of the first and second flip-flops 9 and 10 has a signal b.
is connected, and the signal logic at the input terminal D at the time when the first and second pulse trains c and d are respectively input to the clock input terminal C is set. Therefore, the first and second flip-flops 9,
The signal waveforms at the output terminal Q of No. 10 are as shown in FIG. 5e and f. As shown in FIG. 5, in the case of the solid line, the signal e has a bit pattern of "1101", and the signal f does not have this bit pattern. signal e,
f are the first and second synchronization word detection circuits 1, respectively;
However, since the signal e matches the bit pattern of the synchronization word, the first synchronization word detection circuit 11 outputs a matching signal g (FIG. 5g), and the first monostable flip-flop 13 is set, the signal i at the terminal Q (FIG. 5 i) becomes logic "H", and the switching gate circuit 18 changes the signal e to the signal k.
(Fig. 5k) is output.

That is, when the first pulse train c comes in the latter half of the period T as in the case of the solid line in FIG. ) is output as the decoded output signal k.

On the other hand, if the signals c and d are in the relative phase shown by the dotted line in FIG. 5, the output of the second flip-flop 10 matches the synchronization word as shown by the dotted line in FIG. The matching signal h (Fig. 5h) is output from the word detection circuit 12, the second monostable flip-flop 14 is set (Fig. 5j), and the signal f is output as the signal k. The latter half of the period T will be sampled.

Inverter 8 is omitted and signal a is replaced with signal b.
When inputting to flip-flops 9 and 10,
The synchronization word detection circuits 11 and 12 may detect a bit pattern of the inverted logic of the bit pattern of the synchronization word.

In the above embodiment, the biphase encoding circuit 1
Although the case of converting the logic A of the original signal to A has been described in the above, the same applies to the case of converting to A, and in this case, for example, the design in FIG. 4 may be such that the inverter 8 is omitted.

As described above, according to the present invention, only the code bits that are less affected by low-frequency cutoff are detected from among the code series transmitted through the biphasic encoding circuit, so that the low-frequency characteristics deteriorate more than before. It is possible to perform transmission without code errors using a transmission path that is

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional device, Fig. 2 is a waveform diagram showing the waveforms of each part in Fig. 1, and Fig. 3 is a pattern showing an example of the shape of code bits distorted by the transmission path. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a waveform diagram showing waveforms at various parts in FIG. 4. 1...Biphase encoding circuit, 2...Modulator, 3...Transmission line, 4...1/2 frequency divider, c...
First pulse train, d...Second pulse train, 9...
First flip-flop, 10...Second flip-flop, 11...First synchronization word detection circuit, 1
2...Second synchronization word detection circuit, 18...Switching gate circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1 A means for composing transmission data in which a synchronization word of a predetermined bit pattern is added to the front part of the data to be transmitted, using an NRZ code with a 1-bit period T, and a means for configuring the transmission data with a NRZ code with a 1-bit period T and the logic A(A). is either logic "H" or "L"), and outputs a 2-bit NRZ code whose logic is A or A at a period of T/2. A means for sending data to a transmission line, a demodulator for demodulating the signal transmitted by this transmission line, a first pulse train of period T from the signal demodulated by this demodulator, and this first pulse train is T/ a first flip-flop having a signal input of the output of the demodulator or its inverted output and a clock input of the first pulse train; A second flip-flop whose signal input is the same as that of the flip-flop and whose clock input is the second pulse train, and whose output is the bit pattern of the synchronization word or its inverted bit pattern. a first synchronization word detection circuit that outputs a match signal when a match occurs; and a second synchronization word detection circuit that outputs a match signal when the output of the second flip-flop matches the bit pattern of the synchronization word or its inverted bit pattern.
and a switching gate circuit for selecting the output of a flip-flop corresponding to the second synchronization word detection circuit or the first synchronization word detection circuit which outputs a matching signal. Device.