US3628033A

US3628033A - Photoelectric time delay lock

Info

Publication number: US3628033A
Application number: US851361A
Authority: US
Inventors: Jean-Francois Taillens
Original assignee: Individual
Current assignee: Individual
Priority date: 1969-08-19
Filing date: 1969-08-19
Publication date: 1971-12-14
Anticipated expiration: 1988-12-14

Abstract

The lock comprises an electric circuit including four interconnected circuit sections including a power supply, a photoelectric lock, a key identification logic circuit, and an electrically actuated door latch. These circuit sections are adapted to verify the predetermined position of a plurality of apertures contained in the forward body portion of an opaque key as well as the absence of apertures therein by means of light rays emanating from a light source located adjacent the key and traversing these apertures to one of two sets of selectively positioned photoconductive elements on the other side of the key when the key is inserted into the lock. Output signals are provided from both sets of photoconductive elements in response to the aperture configuration of the key which are coupled to the logic circuit where proper identification of the key is made to then operate the door latch if the proper code is presented by the key.

Description

United States Patent 72] Inventor Jean-Francois Taillens 65 Chemin Isabelle de Montolieu, 100 Lausanne, Switzerland [21] App]. No. 851,361

Aug. 19, 1969 Dec. 14, 1971 [22] Filed [45] Patented [54] PHOTOELECTRIC TIME DELAY LOCK 2 Claims, 6 Drawing Figs.

3,441,715 4/1969 Amacher ABSTRACT: The lock comprises an electric circuit including four interconnected circuit sections including a power supply, a photoelectric lock, a key identification logic circuit, and an electrically actuated door latch. These circuit sections are adapted to verify the predetermined position of a plurality of apertures contained in the forward body portion of an opaque key as well as the absence of apertures therein by means of light rays emanating from a light source located adjacent the key and traversing these apertures to one of two sets of selectively positioned photoconductive elements on the other side of the key when the key is inserted into the lock. Output signals are provided from both sets of photoconductive elements in response to the aperture configuration of the key which are coupled to the logic circuit where proper identification of the key is made to then operate the door latch if the proper code is presented by the key.

as 5'5 D PHOTOELECTRIC TIME DELAY LOCK FIELD OF THE INVENTION The present invention relates to a time delay photoelectric lock with photoelectric actuation means and being further characterized by an electric circuit for the operation of the lock.

SUMMARY Briefly, interconnection is successively made between a first section which constitutes a power supply, a second section which contains the lock portion of the subject invention, a third section which constitutes a circuit for the identification of the key introduced into the lock portion, and a fourth section which contains an electrically actuated door latch. The four interconnected sections are adapted to verify and identify the key by the relative position of one or more apertures disposed in the body of the key by means of light rays emitted from light source which are made to pass through these apertures. The aforesaid light rays are absorbed by first set of selectively positioned photoelectric cells facing the apertures. The proper operation of the lock depends not only upon the registration of the apertures of the key with respect to the first set of photoelectric cells but also to a second set of photoelectric cells which are adapted not to be illuminated when the proper key is inserted. The output signals from both sets of photoelectric cells are then fed to a coincidence logic circuit which is adapted to release the door latch when a key having proper aperture structure is inserted into the lock.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings illustrate by way of example the preferred embodiment and one modification of the lock comprising the subject invention, wherein FIG. I is a schematic view in side elevation of an apertured key;

FIG. 2 is a plan view schematically illustrative of the lock portion of the subject invention with the apertured key shown in FIG. I inserted therein;

FIG. 3 is an electronic circuit diagram of the subject invention;

FIG. 4 is a partial side elevational view of a wall equipped with the subject invention;

FIG. 5 is a schematic view in side elevation of a modification ofthe apertured key illustrated in FIG. I; and

FIG. 6 is another embodiment of a switch utilized in the lock portion ofthe circuit illustrated in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings and more particularly to FIG. I. the preferred embodiment of the subject invention includes an opaque l ey A with three apertures B, B, B" adapted to permit the passage of light energy through the forward body portion thereof emitted from a light source C (FIG. 2) located in the photoelectric lock D. Source C operates when the key A is inserted into the lock which then closes the switch 5 due to the contact with the forward portion of the key. The relative position of these three apertures B, B and B" constitutes a code which if correct, will cause an electrical mechanical or electromagnetic door latch I4 to unlock a door, not shown. The light rays emitted by this source C are restricted so that they must pass through the apertures B, B and B" in the key A whereupon each selectively transmitted ray strikes the light sensitive portion of a selectively located opposing set of photocells E, E and E", respectively, whereupon an electrical signal indicative of this condition is coupled to a logic decoding circuit III for identification as described below.

It should be pointed out that in the case of the installation limited only to the configuration noted, above, a transparent glass plate would be sufficient to operate the lock. However, in order to overcome this simple means of defeating the lock, it is necessary to include into the lock D another set of three photocells F, F' and F", as shown in FIG. 2, which operate in an opposite sense with respect to the sense of the photocells E, E and E", respectively. More particularly, photocells F, F and F", when not illuminated through one or more key apertures, provide the same logic sense output signal as the first set of cells E, E and E" when illuminated. It should be pointed out, however, that the three photocells F, F and F" could be replaced by a single photocell G which is responsive to a selected portion of the surface of the key A after its introduction into the lock D.

Referring now to FIG. 3, the installation of the lock comprises four circuit sections coupled together by means ofsuitable electric circuit interconnections. Section I comprises the power supply for the lock and its associated circuitry and includes, inter alia, an AC rectifier I connected with the electric mains, not shown. Rectifier 1 is used to charge an emergency DC supply 2 which may be, for example, a battery as well as supplying DC power to the subject invention under normal operation. The supply 2 merely permits one to utilize the lock in case of a failure of current in the mains. Section I additionally includes two switches, an ON-OFF power switch 3 and a door latch actuation switch 4, each with pushbuttons, mounted on a common switchboard. The main power switch 3 is utilized as the principal power switch for the installation and it permits the interruption of the DC power necessary for the operation of the lock. The switch 4 is provided in order to manually operate the opening or closing of the electrically operated door latch 14 located in section IV.

Section II constitutes the lock portion of the subject invention and includes, inter alia, a switch 5 which is operated by the key A when it is inserted into the lock D (FIG. 2) whereupon DC power present on circuit buss 50 when ON-OFF switch 3 is closed is applied to circuit buss 512. Section II additionally contains two sets of photocells 6 and 7. The photocells 6, being of selected quantity and location with respect to a predetermined key aperture configuration, are positioned in the lock D so as not to be lighted when the correct key is inserted and provide a binary logic signal P (yes) or N (no) on circuit lead 6a if they are all not lighted and lighted respectively. The set of photocells 7, on the other hand, are all illuminated at the same time when a proper key A is introduced into the lock and registration is made between the aperture B and photocell E, etc., at which time a signal P (yes) appears on circuit lead 7a which is the same as that appearing on circuit lead 611. The set of photocells 6 thus are not illuminated, whereas the set of photocells 7 are illuminated. This condition must exist for operating the lock to unlock the door latch I4.

Section III constitutes the identification logic circuit portion of the subject invention and includes, inter alia, and AND-gate 8 which provides at its output circuit lead 811 a signal P (yes) only when each of its two input signals applied via circuit leads 6a and 7a from cells 6 and 7 are a signal having a P value. In the opposing sense, the combination of a signal N and of a signal P on either of circuit leads 6a and 70 causes an output signal of N (no) to appear on circuit lead 8a and will prevent the operation of the door latch 14.

Section III additionally includes a first time delay device 9, having a delay of, for example, one second. The purpose of this is to prevent sporadic signals from apparatus, such as high-frequency generators, to undesirably trigger the openihg ofthe lock. This preventative measure is provided by the timedelay device 9 which delays for one second the signal P appearing on circuit lead 8a and representative of a key having the proper aperture configuration. This signal is then coupled to output lead 9a and constitutes a signal P when a proper key is inserted into the lock D. A second AND-gate 10 is adapted to couple a relay energizing signal to a relay coil 20 which is adapted to operate relay contacts R,,1 and R I' in the event that a second one second time delay device 11 applied a signal P to one input of the AND-gate 10 on circuit lead Ila. The coincidence of P logic signals on circuit leads 9a and Ila causes AND-gate I0 to couple a signal which energizes relay coil 20. The energization of relay coil 20 causes relay contacts R,,] and R l to switch from the normally deenergized state shown in FIG. 3 to the opposite terminal. The actuation of relay contacts R l' causes the DC voltage present at the junction 3 of the ON-OFF switch 3 and pushbutton switch 4 to be applied to the door latch mechanism 14 which then releases. Relay contacts R l, on the other hand, disconnects circuit buss 512 from the capacitor 12, the resistor R and a third time delay device 13 which has a 2-second time delay period. In the case where the proper key A is inserted in the lock, AND-gate 10 receives coincident input signals from time delay circuits 9 and 11 after a l-second time delay which then operates the door latch 14. In the case of the introduction ofa false key, however, switch closes, whereupon capacitor 12 charges through the normally closed relay contacts R,,l, the time delay device 13 and the diode, after a Z-second delay. The charge placed on capacitor 12 prevents the time delay device 11 from coupling an output signal to the AND-gate until the capacitor l2 discharges through the resistor R which is adapted to provide an RC discharge time constant of approximately 1 hour. Thus, the operating cycle of the lock is interrupted during this time. For a true key, capacitor 12 will not charge because relay contacts R l will open after a l-second time delay and the 2-second time delay circuit 13 prevents any charge from accumulating thereon. Thus, whenever the wrong or faulty key is inserted into the lock D, the capacitor 12 will charge after a 2-second time delay which then effectively prevents AND-gate 10 from energizing the relay coil R.

The above-described time delay photoelectric lock can be utilized for other applications, as well as the operation of a door latch. FIG. 5, for example, illustrates a second embodiment ofa key which may be utilized, for example, with a vehicle. In this embodiment of the key, the aperture comprises a single oblong slit 15 which replaces the three apertures B, B and B" in the key A shown in FIG. 1. Of course, it would be possible to envision a key A with a plurality of slits similar to the slit l5 whenever the aforesaid key would be utilized for individually starting several difference electric apparatus. In the particular case of an automobile, the engine starter would be put into operation by means ofa photoelectric cell being illuminated through the slit 15 in combination with the blockage of any further light for the other set of photoelectric cells, as previously described.

When desirable, switch 5 could be configured as a microswitch or even a magnetically actuated reed" switch such as shown in FIG. 6 and illustrated by reference numeral [6. In this embodiment, the body of the key A is additionally comprised of magnetic material which closes a magnetic circuit around element 17 which is also comprised of magnetic material when the key A" is inserted into the lock. The completion of the magnetic circuit actuates the reed switch 16. The magnetic circuit is continuously magnetized by means of the permanent magnet 18 located on one arm of the element [7.

I claim as my invention:

1. A photoelectric time delay apparatus for actuating an electrical device, comprising, in combination:

an electrical power supply providing a supply voltage;

an opaque key member including a body portion having a plurality of apertures intermediate the ends thereof;

a photoelectric lock including a housing having a channel therein for the insertion ofsaid key member;

an electrical switch mounted in said housing, being coupled to said power supply and adapted to be actuated by said key to provide said supply voltage on a circuit buss;

a light source mounted in said housing adjacent one side of said channel and coupled to said supply buss, being energized by said supply voltage when said key is inserted in said channel and transmitting light rays across said channel through said plurality ofapertures;

a first plurality of photodetector means mounted in said housing adjacent the other side of said channel, being positioned in selective registration with said opaque key member to be responsive to light transmitted through said plurality ofapertures; first circuit means coupled to said first plurality of photodetector means providing a first-type output signal in the event all of said photodetector means are illuminated through said plurality of apertures;

a second plurality of photodetector means mounted in said housing adjacent said other side of said channel, being positioned in selective registration with said opaque key member to be normally blocked from light emitted from said source by said body portion of said key member;

second circuit means coupled to said second plurality of photodetector means providing another first-type output signal in the event all of said second photodetector means are blocked but an opposite-type output signal when said second photodetector means are illuminated from said source through said key member;

logic circuit means coupled to said first and second plurality of photodetector means and providing a control signal output in response to the time coincidence of inputs of said first-type output signals therefrom, said logic circuit means comprising: (a) a first AND logic gate coupled to said first and second plurality of photodetector means; (b) a first time delay circuit, having a first selected time delay, coupled to the output of said first AND gate; (c) a second time delay circuit, having substantially the same selected time delay as said first time delay circuit, coupled to said circuit buss; (d) a second AND logic gate, coupled to said first and second time delay circuits, becoming operative in response to time coincident outputs therefrom to provide said control signal; (e) relay circuit means coupled to said second AND gate, becoming energized by said control signal and applying said actuating signal to said electrical device; (f) circuit interruptor means operated by said relay circuit means; (g) a third time delay circuit, having a time delay greater than said first time delay, coupled to said circuit interruptor means; and (h) a resistance-capacitance charging circuit including at least one capacitor coupled to said second time delay circuit, said capacitor being adapted to be charged through said third time delay circuit and said circuit interruptor means to render said second time delay circuit inoperative after a time delay greater than said first time delay when either said first or second plurality of photodetector means provides a mutually oppositetype logic output signal, said circuit interruptor means, however, disconnecting said third time delay circuit upon operation of said second AND gate thereby preventing said capacitor from charging.

2. The invention as defined by claim 1 wherein said circuit interruptor means comprises a normally closed pair of relay contacts included in said relay circuit means.

Claims

1. A photoelectric time delay apparatus for actuating an electrical device, comprising, in combination: an electrical power supply providing a supply voltage; an opaque key member including a body portion having a plurality of apertures intermediate the ends thereof; a photoelectric lock including a housing having a channel therein for the insertion of said key member; an electrical switch mounted in said housing, being coupled to said power supply and adapted to be actuated by said key to provide said supply voltage on a circuit buss; a light source mounted in said housing adjacent one side of said channel and coupled to said supply buss, being energized by said supply voltage when said key is inserted in said channel and transmitting light rays across said channel through said plurality of apertures; a first plurality of photodetector means mounted in said housing adjacent the other side of said channel, being positioned in selective registration with said opaque key member to be responsive to light transmitted through said plurality of apertures; first circuit means coupled to said first plurality of photodetector means providing a first-type output signal in the event all of said photodetector means are illuminated through said plurality of apertures; a second plurality of photodetector means mounted in said housing adjacent said other side of said channel, being positioned in selective registration with said opaque key member to be normally blocked from light emitted from said source by said body portion of said key member; second circuit means coupled to said second plurality of photodetector means providing another first-type output signal in the event all of said second photodetector means are blocked but an opposite-type output signal when said second photodetector means are illuminated from said source through said key member; logic circuit means coupled to said first and second plurality of photodetector means and providing a control signal output in response to the time coincidence of inputs of said first-type output signals therefrom, said logic circuit means comprising: (a) a first AND logic gate coupled to said first and second plurality of photodetector means; (b) a first time delay circuit, having a first selected time delay, coupled to the output of said first AND gate; (c) a second time delay circuit, having substantially the same selected time delay as said first time delay circuit, coupled to said circuit buss; (d) a second AND logic gate, coupled to said first and second time delay circuits, becoming operative in response to time coincident outputs therefrom To provide said control signal; (e) relay circuit means coupled to said second AND gate, becoming energized by said control signal and applying said actuating signal to said electrical device; (f) circuit interruptor means operated by said relay circuit means; (g) a third time delay circuit, having a time delay greater than said first time delay, coupled to said circuit interruptor means; and (h) a resistance-capacitance charging circuit including at least one capacitor coupled to said second time delay circuit, said capacitor being adapted to be charged through said third time delay circuit and said circuit interruptor means to render said second time delay circuit inoperative after a time delay greater than said first time delay when either said first or second plurality of photodetector means provides a mutually opposite-type logic output signal, said circuit interruptor means, however, disconnecting said third time delay circuit upon operation of said second AND gate thereby preventing said capacitor from charging.