US20130142238A1

US20130142238A1 - High resolution symbol timing tracking

Info

Publication number: US20130142238A1
Application number: US13/646,138
Authority: US
Inventors: Chun-Hsuan Kuo
Original assignee: Broadcom Corp
Current assignee: Avago Technologies International Sales Pte Ltd
Priority date: 2011-12-01
Filing date: 2012-10-05
Publication date: 2013-06-06
Also published as: US20130143554A1; US20130141257A1; US20130143577A1; US20130142221A1; US20130142190A1; US8670509B2; US8842658B2; US8861652B2; US9198149B2; US20130142057A1; US20130142223A1; US20130142273A1

Abstract

Embodiments of the present disclosure prove an apparatus and method for symbol timing tracking. Such embodiments are configured to obtain a sampling time for sampling a signal pulse; generate a symbol value for the sampling time from actual sample values of the signal pulse corresponding to predetermined sampling times by interpolating the symbol value utilizing the predetermined sampling times and the actual sample values, wherein the sampling time is not included as one of the predetermined sampling times; and utilize the symbol value to determine an optimal sampling time for sampling the signal pulse.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Provisional Patent Application entitled “Cellular Baseband Processing” having Ser. No. 61/565,864, filed Dec. 1, 2011; and “Cellular Baseband Processing” having Ser. No. 61/568,868, filed Dec. 9, 2011, the entireties of which are hereby incorporated by reference.

BACKGROUND

In communication systems, a transmitter transmits signals carrying digital data to a receiver with a specific symbol timing T1. After receiving the signals, a receiver recovers the digital data by sampling the signals according to a specific symbol timing T2. If the symbol timing T2 of the receiver is the same as the symbol timing T1 of the transmitter, the receiver will recover the digital data correctly. However, if the symbol timing T2 is different from the symbol timing T1, the receiver will not recover the digital data correctly.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block diagram of an exemplary communication system in accordance with embodiments of the present disclosure.

FIG. 2 is a block diagram of a portion of an exemplary receiver including a timing recovery module in accordance with embodiments of the present disclosure.

FIG. 3 is a block diagram of a portion of the timing recovery module of FIG. 2 in accordance with embodiments of the present disclosure.

FIG. 4 is an illustrative diagram of sample values in accordance with embodiments of the present disclosure.

FIG. 5 is a flow chart diagram describing exemplary operation of a portion of the receiver of FIG. 2 in accordance with embodiments of the present disclosure.

FIG. 6 is a schematic block diagram of an exemplary communication device 600 equipped with the receiver of FIG. 2 according to embodiments of the present disclosure.

DETAILED DESCRIPTION

In summary, embodiments of the present disclosure provide a system and method for symbol timing tracking. Embodiments allow a receiver to track the timing of symbols and determining a sampling offset or difference between the receiver timing and a transmitter timing, where a corrected sampling time may be determined accounting for the sampling offset with a high and improved resolution.
FIG. 1 is a block diagram of an exemplary communication system 100 including a transmitter 101 and a receiver 102. Transmitter 101 transmits a data signal 104 including, for example, a series of data symbols, to receiver 102. Data signal 104 has a frequency f1 (for example, a symbol baud rate f1) and a phase P1 both related to a frequency and a phase of an oscillator local to transmitter 101. Receiver 102 samples data signal 104 (for example, symbols included in the data signal) to recover data from the data signal 104. Receiver 102 samples the data signal at sampling times established by a sampling signal 106 generated locally at receiver 102. Locally generated sampling signal 106 has a frequency f2 and a corresponding phase P2.
In one embodiment, the transmitter 101 may employ spread spectrum modulation, such as chirp modulation. For chirp modulation, an exemplary receiver utilizes a matched filter matched to the angular rate of change of the transmitter frequency-swept signal. An estimate of the transmitted signal can be generated by using a voltage controlled oscillator (VCO) and matched filter used in the receiver 102 as a dispersive delay line (DDL).
To minimize errors in recovering the data from data signal 104, it is desirable that frequencies f2 and f1 match one another, and that phases P1 and P2 are aligned with one another, such that sampling signal 106 causes receiver 102 to sample serial data signal 104 at optimum sampling times coinciding with occurrences of a maximum Signal-to-Noise (S/N) level of the serial data signal. Often, however, frequency f2 and phase P2 are respectively offset from frequency f1 and phase P1 because of differences between the respective oscillators used in transmitter 101 and receiver 102.
The phase offset between phase P1 and phase P2 can cause receiver 102 to sample serial data signal 104 at sub-optimal sampling times, while the frequency offset between frequencies f1 and f2 tends to cause the data signal to drift through sampling signal 106. Therefore, such offsets can cause errors in recovering the data from data signal 104. Consequently, it is desirable to compensate for such frequency and phase offsets in receiver 102 in order to optimally recover data from serial data signal 104.
For spread spectrum systems, an exemplary receiver employs a synchronized replica of the spreading or code signal to demodulate the received signal successfully, in one embodiment. The process of synchronizing the locally generated spreading signal with the received spread spectrum signal may be accomplished in multiple stages of timing recovery circuitry. First, an acquisition stage brings the two spreading signals into coarse alignment with one another. Second, a tracking stage proceeds and continuously maintains the best possible waveform fine alignment by means of a feedback loop with the acquisition stage.
A common feature of acquisition techniques is that the receiver signal and the locally generated signal are first correlated to produce a measure of similarity between the two. This measure is then compared with a threshold to decide if the two signals are in sync. If they are in sync, the tracking loop or stage takes over. If they are not in sync, the acquisition procedure provides for a phase or frequency change in a locally generated uncertainty region, and another correlation process is started again. For the tracking loop, code tracking is accomplished by a delay lock loop (DLL), in some embodiments, and may comprise a second order loop.
A purpose of the timing recovery circuitry is to obtain symbol synchronization in which two quantities are determined by the receiver 102 to achieve symbol synchronization. The first is the sampling frequency. Locking the sampling frequency requires estimating the symbol period so that samples can be taken at the correct rate within a received signal.
The other quantity to determine is sampling phase or time. Locking the sampling phase involves determining the correct time within a symbol period or chip duration to take a sample. Real-world symbol pulse shapes have a peak in the center of the symbol period. Sampling the symbol at this peak results in the best signal-to-noise-ratio and will ideally eliminate interference from other symbols. Sampling the symbol at instances besides the peak will result in sampling phase errors.
Accordingly, one embodiment of an exemplary DLL used in timing recovery circuitry is based on an early-late synchronizer approach. Sampling times that are determined to be early or late to the optimum sampling time (by comparing respective amplitudes) cause for a previous sampling time to be adjusted.
Therefore, this “timing estimator” circuitry processes input samples, typically received from a baseband analog-to-digital converter (ADC) in the corresponding receiver 102. The timing estimator is configured to provide fine estimation and tracking of clock phase error between the transmitter 101 and receiver 102 given an initial coarse estimate of the clock phase error. The initial coarse estimate may be determined using any of a variety of well-known conventional techniques, as will be readily apparent to those skilled in the art.
The timing estimator then further refines the estimate of the clock phase error, where the estimate is performed over a designated number N of samples per chip. The determined phase/time offset or error may provide the correction to be applied to the timing of the punctual sample, where a voltage controlled oscillator (VCO) provides the timing for sampling operations. That is, the sampling phase or time instant of the punctual sample should be corrected by the amount of the error. Multiple sample values of the same are available of a finite predetermined number.
These values are essentially the values of the chip pulse at integers of the sampling instant. A corrected sampling phase may not necessarily coincide with the previous finite number of samples that are being used for the sampling and have been predetermined. However, embodiments of the present disclosure employ interpolation to obtain a sample value corresponding to the corrected phase, such as via cubic polynomial interpolation or other interpolation technique. In the case of cubic polynomial interpretations, 4 samples may be used to define a plot of the chip pulse and extract a sample value at the corrected phase which is used to adaptively determine the phase error. Accordingly, the timing recovery circuitry may include interpolation circuitry or logic for use in calculating the phase error and determining corrected sample phases. It should be noted that the predetermined and received signal samples are typically held in a buffer or other memory element of the receiver. Thus, the process of generating the sample value at the corrected phase or sample instant may amount to using four different entries of the buffer, in one embodiment.
Consider an exemplary illustration where a period T of a symbol or chip interval is divided into a finite number of units. Accordingly, the chip pulse received by the receiver 102 is sampled at (or oversampled at) a sampling time corresponding to each unit. Then, if a determined offset is applied to a sampling time to obtain a corrected sampling time, the corrected sampling time may not coincide with any of the finite number of units. Instead of selecting the unit that is closest to the corrected sampling time and being limited to a finite resolution (e.g., have only a finite number of possible options), a sample value for the actual sampling time may be determined via interpolation. In this case, one is not limited or restricted to a finite number of options and instead, an infinite number of options is available within the symbol interval to consider as the sampling time. Accordingly, a function defining the chip pulse may be estimated using interpolation and a subset of the sampled units. As non-limiting examples, two samples may be used in linear interpolation and four samples may be used in cubic polynomial interpolation. It may also be desired to use more than four signal samples with a high order polynomial interpolation, in some embodiments.
Next, FIG. 2 is a block diagram of a portion of an exemplary receiver 200 including a timing recovery module 202 in accordance with the present disclosure. Receiver 200 also includes a reference signal generator 204. Timing recovery module 202 receives data signal 104, including, for example, a series of data symbols. Reference signal generator 204 generates a set of reference signals 206 and provides the reference signal set to timing recovery module 202.
Based on data signal 104 and reference signal set 206, timing recovery module 202 derives a timing/sampling signal 208 used by receiver 200 to recover data from data signal 104. Timing/sampling signal 208 is preferably used as a sampling signal in receiver 200 to sample symbols included in data signal 104. Timing recovery module 202 derives sampling signal 208 such that the sampling signal is phase-aligned with data signal 104 and such that the frequency of sampling signal 208 matches the frequency (such as a symbol baud rate) of data signal 104. In this manner, timing recovery module 202 recovers timing information (for example, phase and frequency information) from data signal 104 in accordance with the present disclosure.
Referring now to FIG. 3, a block diagram of a portion of the receiver timing recovery module 202 is depicted in accordance with embodiments of the present disclosure. Such a recovery module may be used in receivers and systems described in U.S. patent application Ser. 13/564,282, filed Aug. 1, 2012, which is incorporated herein by reference in its entirety.
As discussed, the receiver timing module 202 includes circuitry 304 and/or logic for implementing an acquisition stage. The acquisition circuitry 304 determines whether a locally generated signal matches or is in sync with a received transmitted signal. If the signals are in sync, tracking circuitry 306 of the receiver timing module 202 obtains symbol synchronization by locking the sampling frequency of the locally generated signal with the transmitted signal. Locking the sampling frequency requires estimating the symbol period so that samples can be taken at the correct rate within a received signal from the transmitter.
The tracking circuitry may further include timing estimator circuitry 308 that processes input samples from buffer or memory 308, typically received from a baseband ADC in the corresponding receiver. The timing estimator 308 then further refines the estimate of the clock phase error (from acquisition circuitry 304), where the estimate is performed over a designated number N of samples per chip. The determined phase/time offset or error (x) may provide the correction to be applied to the timing of the punctual sample. That is, the sampling phase or time instant of the punctual sample should be corrected by the amount of the error provided from feedback loop 307. Multiple sample values of the same are available of a finite predetermined number.
Embodiments of the present disclosure include interpolator circuitry 312 to obtain a sample value corresponding to the corrected phase, such as via cubic polynomial interpolation or other interpolation technique. Interpolator circuitry 312, in various embodiments, may utilize Farrow structures, polyphase filters, FIR filters, and/or other components.
In accordance with the present disclosure, embodiments of the interpolator circuitry 312 may obtain a sample value corresponding to the corrected phase, such as via cubic polynomial interpolation or other interpolation technique. In the case of cubic polynomial interpretations, four samples may be used to define a plot of the chip pulse and extract a sample value at the corrected phase which is used to adaptively determine the phase error. It should be noted that the predetermined and received signal samples are typically held in a buffer 308 or other memory element of the receiver 200. Thus, the process of generating the sample value at the corrected phase or sample instant may amount to using four different entries of the buffer, in one embodiment.
To illustrate, consider FIG. 4, which graphically depicts stored sample values for sampling times T1-T8. In this example, a corrected or adjusted sampling time (“x”) has been determined by the timing estimator 310 of the receiver timing recovery module 202. The corrected sampling time falls between the stored values for T4 and T5. While the corrected sampling time x is in close proximity to T5, the sample value (represented by the unfilled or open circle above the x), is not the same value as the sample value for T5 (represented as a filled or closed circle). Therefore, by estimating a polynomial function that satisfies the constraints of containing a subset of the sampling times (e.g., sampling times (e.g. T3, T4, T5, T6 for a cubic polynomial estimation), the sample value for the desired corrected sample value may be obtained. Similarly, if the timing estimator 310 generates a new offset to the previous sample value, a new corrected sample value for a new corrected sampling time may be obtained anywhere within a sampling interval, thereby allowing for infinite resolution capability.
Referring next to FIG. 5, shown is a flow chart that provides one example of the operation of a portion of the receiver 102 (FIG. 2) according to various embodiments. It is understood that the flow chart of FIG. 5 provides merely an example of the many different types of functional arrangements that may be employed to implement the operation of the portion of the receiver 102 as described herein. As an alternative, the flow chart of FIG. 5 may be viewed as depicting an example of operations or actions of a method implemented in a communication device 600 (FIG. 6) according to one or more embodiments.
Beginning with reference character 510, a sampling time is obtained by timing estimator circuitry 308 (FIG. 3) of the receiver 102 (FIG. 1) for sampling a signal pulse. The sampling time may be obtained from acquisition circuitry 304 (FIG. 3). Then, with reference character 520, the timing estimator 308 generates a symbol value for the sampling time from actual sample values of the signal pulse corresponding to predetermined sampling times by interpolating the symbol value utilizing the predetermined sampling times and the actual sample values, wherein the sampling time is not included as one of the predetermined sampling times. In performing the interpolation, some embodiments may utilize a cubic polynomial interpolation. Also, some embodiments may use other forms of interpolation including linear interpolation, polynomial interpolations having a degree higher than 3, and other techniques. Accordingly, in FIG. 5, the symbol value is utilized (530) to determine an optimal sampling time for sampling the signal pulse.
FIG. 6 is a schematic block diagram of an exemplary communication device 600 that is equipped with embodiments of the receiver 102, 200 according to the present disclosure. The communication device 600 includes a processor 603 and a memory 606, which are coupled to a local interface 609. The communication device 600 may comprise, for example, at least one computing device or like device. The communication device 600 may be embedded on a chip as part of an on-chip network, such as one embedded in a system on a chip (SoC) for a communication system. The local interface 609 may comprise, for example, a data bus with an accompanying address/control bus or other bus structure as can be appreciated.
The communication device 600 may be implemented as a board level product, as a single chip, application specific integrated circuit (ASIC), and so on. Alternatively, certain aspects of the present disclosure are implemented as firmware. Such components as the timing estimator 308 and the interpolator component 312 may be stored in memory 606 with other components and executed by the processor 603. It is understood that there may be other systems that are stored in the memory 606 and are executable by the processor 603 as can be appreciated. A number of software components are stored in the memory 606 and are executable by the processor 603. In this respect, the term “executable” means a program file that is in a form that can ultimately be run by the processor 603.
Examples of executable programs may be, for example, a compiled program that can be translated into machine code in a format that can be loaded into a random access portion of the memory 606 and run by the processor 603, source code that may be expressed in proper format such as object code that is capable of being loaded into a random access portion of the memory 606 and executed by the processor 603, or source code that may be interpreted by another executable program to generate instructions in a random access portion of the memory 606 to be executed by the processor 603, etc.
The memory 606 is defined herein as including both volatile and nonvolatile memory and data storage components. Volatile components are those that do not retain data values upon loss of power. Nonvolatile components are those that retain data upon a loss of power. Thus, the memory 606 may comprise, for example, random access memory (RAM), read-only memory (ROM), and/or other memory components, or a combination of any two or more of these memory components. In addition, the RAM may comprise, for example, static random access memory (SRAM), dynamic random access memory (DRAM), or magnetic random access memory (MRAM) and other such devices.
Also, the processor 603 may represent multiple processors 603 and the memory 606 may represent multiple memories 606 that operate in parallel processing circuits, respectively. In such a case, the local interface 609 may be an appropriate network that facilitates communication between any two of the multiple processors 603, between any processor 603 and any of the memories 606, or between any two of the memories 606, etc. The local interface 609 may comprise additional systems designed to coordinate this communication, including, for example, performing load balancing. The processor 603 may be of electrical or of some other available construction. In one embodiment, the processor 603 and memory 606 may correspond to a system-on-a-chip.
Although portions of the communication device 600 described herein may be embodied in software or code executed by general purpose hardware as discussed above, as an alternative, the same may also be embodied in dedicated hardware or a combination of software/general purpose hardware and dedicated hardware. If embodied in dedicated hardware, each component may be implemented as a circuit or state machine that employs any one of or a combination of a number of technologies. These technologies may include, but are not limited to, discrete logic circuits having logic gates for implementing various logic functions upon an application of one or more data signals, ASICs having appropriate logic gates, or other components, etc. Such technologies are generally well known by those skilled in the art and, consequently, are not described in detail herein.
Similarly, components of the communications device 600 or system 100, in combination with operational instructions stored in memory, may be, but is not limited to being, enabled to execute receiver functions and/or transmitter functions, respectively. The receiver functions may comprise, but are not limited to, demodulation, constellation demapping, decoding, and/or descrambling. The transmitter functions may comprise, but are not limited to, scrambling, encoding, constellation mapping, and modulation. The receiver and the transmitter components, respectively, may be implemented using a shared processing device, individual processing devices, or a plurality of processing devices, for example, a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions.
The flowchart of FIG. 5 shows the functionality and operation of an implementation of portions of the receiver 102. If embodied in software, each block may represent a module, segment, or portion of code that comprises program instructions to implement the specified logical function(s). The program instructions may be embodied in the form of source code that comprises human-readable statements written in a programming language or machine code that comprises numerical instructions recognizable by a suitable execution system such as a processor 603 in a computer system or other system. The machine code may be converted from the source code, etc. If embodied in hardware, each block may represent a circuit or a number of interconnected circuits to implement the specified logical function(s).
Although the flowchart of FIG. 5 shows a specific order of execution, it is understood that the order of execution may differ from that which is depicted. For example, the order of execution of two or more blocks may be scrambled relative to the order shown. Also, two or more blocks shown in succession in FIG. 5 may be executed concurrently or with partial concurrence. Further, in some embodiments, one or more of the blocks shown in FIG. 5 may be skipped or omitted. It is understood that all such variations are within the scope of the present disclosure.
Also, any logic or application described herein that comprises software or code can be embodied in any non-transitory computer-readable medium for use by or in connection with an instruction execution system such as, for example, a processor 603 in a computer system or other system. In this sense, the logic may comprise, for example, statements including instructions and declarations that can be fetched from the computer-readable medium and executed by the instruction execution system. In the context of the present disclosure, a “computer-readable medium” can be any medium that can contain, store, communicate, propagate, or maintain the logic or application described herein for use by or in connection with the instruction execution system.
The computer-readable medium can comprise any one of many physical media such as, for example, magnetic, optical, or semiconductor media and may include electronic, electromagnetic, infrared, or, or propagation media. More specific examples of a suitable computer-readable medium would include, but are not limited to, random access memory (RAM) including, for example, static random access memory (SRAM) and dynamic random access memory (DRAM), or magnetic random access memory (MRAM). In addition, the computer-readable medium may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or other type of memory device.
It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims

At least the following is claimed:

1. A symbol timing tracking method, comprising:

obtaining a sampling time for sampling a signal pulse;

generating a symbol value for the sampling time from actual sample values of the signal pulse corresponding to predetermined sampling times by interpolating the symbol value utilizing the predetermined sampling times and the actual sample values, wherein the sampling time is not included as one of the predetermined sampling times; and

utilizing the symbol value to determine an optimal sampling time for sampling the signal pulse,

wherein the predetermined sampling times, the sampling time, and the optimal sampling time fall within a defined interval period of the signal pulse.

2. The method of claim 1, wherein a cubic polynomial interpolation is used in interpolating the symbol value.

3. The method of claim 1, wherein a polynomial interpolation having a degree higher than 3 is used in interpolating the symbol value.

4. The method of claim 1, wherein a number of the predetermined sampling times is finite and a number of possible sample values to be generated in determining the optimal sampling time by interpolation is infinite.

5. The method of claim 4, wherein a subset of the predetermined sampling times is used in the interpolation of the symbol value.

6. The method of claim 1, wherein the sampling time for sampling a signal pulse is obtained from acquisition circuitry comprising a mismatch filter.

7. A system comprising:

timing estimator circuitry that receives a sampling time signal for sampling a signal pulse and generates a symbol value for a sampling time from actual sample values of the signal pulse corresponding to predetermined sampling times by interpolating the symbol value utilizing the predetermined sampling times and the actual sample values, wherein the sampling time is not included as one of the predetermined sampling times;

a buffer that stores the actual sample values for the predetermined sampling times; and

a loopback input that that feeds the symbol value back to the timing estimator circuitry to determine an optimal sampling time for sampling the signal pulse.

8. The system of claim 7, wherein the timing estimator circuitry comprises a delay-locked loop.

9. The system of claim 7, wherein the timing estimator circuitry comprises interpolator circuitry having Farrow structures.

10. The system of claim 7, further comprising acquisition circuitry having a mismatch filter that generates the sampling time signal that is provided to the timing estimator.

11. The system of claim 7, wherein a polynomial interpolation having a degree higher than 2 is used in interpolating the symbol value.

12. The system of claim 7, wherein a number of the predetermined sampling times is finite and a number of possible sample values to be generated in determining the optimal sampling time by interpolation is infinite.

13. The system of claim 12, wherein a subset of the predetermined sampling times is used in the interpolation of the symbol value.

14. The system of claim 7, wherein the predetermined sampling times, the sampling time, and the optimal sampling time fall within a defined interval period of the signal pulse.

15. A non-transitory computer readable medium having a program, when executed by a hardware processor, causes the processor to:

obtain a sampling time for sampling a signal pulse;

generate a symbol value for the sampling time from actual sample values of the signal pulse corresponding to predetermined sampling times by interpolating the symbol value utilizing the predetermined sampling times and the actual sample values, wherein the sampling time is not included as one of the predetermined sampling times; and

utilize the symbol value to determine an optimal sampling time for sampling the signal pulse.

16. The non-transitory medium of claim 15, wherein a cubic polynomial interpolation is used in interpolating the symbol value.

17. The non-transitory medium of claim 15, wherein a polynomial interpolation having a degree higher than 3 is used in interpolating the symbol value.

18. The non-transitory medium of claim 15, wherein a number of the predetermined sampling times is finite and a number of possible sample values to be generated in determining the optimal sampling time by interpolation is infinite.

19. The non-transitory medium of claim 18, wherein a subset of the predetermined sampling times is used in the interpolation of the symbol value.

20. The non-transitory medium of claim 15, wherein the predetermined sampling times, the sampling time, and the optimal sampling time fall within a defined interval period of the signal pulse.