US20130142221A1

US20130142221A1 - High performance window searcher for cell measurement

Info

Publication number: US20130142221A1
Application number: US13/415,487
Authority: US
Inventors: Pengfei Xia; Mark Hahm; Jaeyoung Kwak; Severine Catreux-Erceg; Nelson Sollenberger
Original assignee: Broadcom Corp
Current assignee: Avago Technologies International Sales Pte Ltd
Priority date: 2011-12-01
Filing date: 2012-03-08
Publication date: 2013-06-06
Also published as: US8842658B2; US20130143554A1; US20130142238A1; US20130143577A1; US8670509B2; US20130142273A1; US20130142190A1; US20130141257A1; US9198149B2; US8861652B2; US20130142223A1; US20130142057A1

Abstract

Disclosed are various embodiments involving a window searcher for cell measurement. A window search is configurable and scalable as to a number of scrambling codes to be searched in parallel over a window span for each scrambling code. A received signal is descrambled. A coherent accumulation is performed on the descrambled received signal at a first subchip resolution to produce a coherent accumulation result. The coherent accumulation result is interpolated to a second subchip resolution. A non-coherent accumulation is performed on the descrambled received signal at the second subchip resolution based at least in part on the interpolated coherent accumulation result.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to, and the benefit of, U.S. Provisional Patent Application entitled “CELLULAR BASEBAND PROCESSING,” having Ser. No. 61/565,864, filed on Dec. 1, 2011, and U.S. Provisional Patent Application entitled “CELLULAR BASEBAND PROCESSING,” having Ser. No. 61/568,868, filed on Dec. 9, 2011, both of which are incorporated by reference in their entirety.

BACKGROUND

Wideband code division multiple access (WCDMA) is a third generation (3G) cellular technology that enables the concurrent transmission of a plurality of distinct digital signals via a common RF channel. WCDMA supports a range of communications services that include voice, high speed data and video communications. One such high speed data communications service, which is based on WCDMA technology, is the high speed downlink packet access (HSDPA) service.
WCDMA is a spread spectrum technology in which each digital signal is coded or “spread” across the RF channel bandwidth using a spreading code. Each of the bits in the coded digital signal is referred to as a “chip.” A given base transceiver station (BTS), which concurrently transmits a plurality of distinct digital signals, may encode each of a plurality of distinct digital signals by utilizing a different spreading code for each distinct digital signal. At a typical BTS, each of these spreading codes is referred to as a Walsh code. The Walsh coded digital signal may in turn be scrambled by utilizing a pseudo-noise (PN) bit sequence to generate chips. An example of a PN bit sequence is a Gold code. Each of a plurality of BTS within an RF coverage area may utilize a distinct PN bit sequence. Consequently, Walsh codes may be utilized to distinguish distinct digital signals concurrently transmitted from a given BTS via a common RF channel while PN bit sequences may be utilized to distinguish digital signals transmitted by distinct BTSs. The utilization of Walsh codes and PN sequences may increase RF frequency spectrum utilization by allowing a larger number of wireless communications to occur concurrently within a given RF frequency spectrum. Accordingly, a greater number of users may utilize mobile communication devices, such as mobile telephones, Smart phones and/or wireless computing devices, to communicate concurrently via wireless communication networks.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a drawing of an exemplary wireless communication system, in accordance with an embodiment of the present disclosure.

FIG. 2 is a drawing of an exemplary transceiver system, in accordance with an embodiment of the present disclosure.

FIG. 3 is a drawing of an exemplary window search module employed in the transceiver system of FIG. 2, in accordance with an embodiment of the present disclosure.

FIG. 4 is a block diagram illustrating one example of Ec estimation logic used in the window search module of FIG. 3, in accordance with an embodiment of the present disclosure.

FIGS. 5 and 6 are flowcharts illustrating examples of functionality implemented as portions of the window search module of FIG. 2 according to various embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure relates to an enhanced window searcher for cell measurement. In WCDMA and/or other wireless technologies subject to mobility, a wireless communications device, such as a cell phone, periodically performs a window search to measure the received energy from the multipath delay profile of the active cells and/or other cells. The sum of the measured energy of all detected paths is reported by the user equipment (UE) to the network so that each cell strength may be monitored and continuously updated. This enables dynamic cell reselection and soft handover.
A signal from a base station may be reflected by various objects, thereby resulting in multiple paths being received at different delays by the receiver. A window search is employed to identify these multiple delayed paths over a time “window” surrounding an identified peak energy path. The window span, or the length of the window, may be 15 chips, 30 chips, 60 chips, 90 chips, or some other length. The resolution for path energy measurement may be chip or sub-chip resolution (e.g., ½ chip, ¾ chip, etc.). The path energy is obtained by first descrambling and despreading the received signal, and then squaring the magnitude of the despreaded symbol. The scrambling code phase is offset by one chip at a time (or some other predetermined number of chips) to cover the length of the time window.
Various embodiments of the present disclosure provide configurable and scalable window search logic that exploits parallelism and reduces power consumption through resource sharing. To this end, sufficient hardware resources may be provided to enable parallel searching for multiple scrambling codes, multiple window spans, and/or multiple antennas. That is, the window search logic is equipped with a total number of coherent accumulators N, and the number N can be dynamically allocated to search across various dimensions as needed, where the dimensions are scrambling code, antennas, and window span.
Additionally, for power consumption savings, not all N resources need to be active all the time. If a search requires fewer than N resources, then the power consumption scales down accordingly. For example, the number of active coherent accumulators, which are a major source of power consumption in window search logic, may be reduced given that the longest window span (e.g., 90 chips or some other span) may be needed only for a small number of the scrambling codes, and given that parallel searching for the maximum number of scrambling codes (e.g., 8 scrambling codes or some other number) may not be needed most of the time. Furthermore, the number of coherent accumulators may be reduced by way of using interpolation logic to achieve a desired higher subchip resolution (e.g., chip by 4 (cx4) resolution or another higher subchip resolution).
FIG. 1 is an illustration of an exemplary wireless communication system, in accordance with an embodiment. Referring to FIG. 1, there is shown a cell 100 and a base station C 106. The cell 100 comprises base station A 102, mobile communication device MU_—1 112 and mobile communication device MU_—2 114. The base station 106 may be located outside of the cell 100.
The mobile communication devices MU_—1 112 and MU_—2 114 may be engaged in a communication via the base station A 102. The mobile communication device MU_—1 112 may transmit signals to the base station A 102 via an uplink RF channel 122. In response, the base station A 102 may transmit signals to the mobile communication device MU_—2 114 via a downlink RF channel 124. Signals transmitted by the base station A 102 may communicate chips that are generated utilizing a scrambling code PN_A. The signals transmitted via RF channel 124 may be spread utilizing a spreading code WC_—12. The spreading code WC_—12 may comprise an orthogonal variable spreading factor (OVSF) code, for example, a Walsh code, which enables the mobile communication device MU_—2 114 to distinguish signals transmitted by the base station A 102 via the downlink RF channel 124 from signals transmitted concurrently by the base station A 102 via other downlink RF channels, for example downlink RF channel 126. The base station A 102 may utilize one or more OVSF codes, WC_other, when spreading data transmitted via downlink RF channel 126. The one or more OVSF codes, WC_other, may be distinct from the OVSF code WC_—12. The base station A 102 may also transmit broadcast signals which may be received by all mobile communication devices. The broadcast signals, spread by OVSF code, WC_broadcast, may be sent simultaneously on downlink RF channels 124 and 126.
The mobile communication device MU_—2 114 may receive multiple access interference (MAI) signals from RF channel 126 and/or RF channel 130. As stated above, the signals received via RF channel 126 may be transmitted by the base station A 102. The signals received via RF channel 130 may be transmitted by the base station C 106. The signals transmitted by the base station C 106 may be scrambled based on a scrambling code PN_C.
The mobile communication device MU_—2 114 may be operable to perform a soft handoff from the current serving base station A 102 to a base station, which is outside of the cell 100, for example, the base station C 106. Accordingly, the mobile communication device MU_—2 114 may be operable to process received signals based on scrambling code PN_C. In this regard, MU_—2 114 may listen for signals from base station C 106.
Although FIG. 1 depicts communication between two mobile devices via a single BTS, the present disclosure is not so limited. For example, aspects of the present disclosure may be equally applicable regardless of the origin of data communicated wirelessly to the mobile communication device 114.
FIG. 2 is a diagram of an exemplary communication device in accordance with various embodiments. Referring to FIG. 2, there is shown a transceiver system 200, a receiving antenna 222 and a transmitting antenna 232. The transceiver system 200 may comprise at least a receiver 202, a transmitter 204, a processor 206, a memory 208, a window search module 210, a receive diversity adaptation module 211, and/or other components. Although a separate receiver 202 and transmitter 204 are illustrated by FIG. 2, the present disclosure is not limited. In this regard, the transmit function and receive function may be integrated into a single transceiver block. The transceiver system 200 may also comprise a plurality of transmitting antennas and/or a plurality of receiving antennas, for example to support diversity transmission and/or diversity reception. Various embodiments may comprise a single antenna, which is coupled to the transmitter 204 and receiver 202 via a transmit and receive (T/R) switch. The T/R switch may selectively couple the single antenna to the receiver 202 or to the transmitter 204 under the control of the processor 206, for example.
The receiver 202 may comprise suitable logic, circuitry, interfaces and/or code that may be operable to perform receive functions that may comprise PHY layer function for the reception or signals. These PHY layer functions may comprise, but are not limited to, the amplification of received RF signals, generation of frequency carrier signals corresponding to selected RF channels, for example uplink or downlink channels, the down-conversion of the amplified RF signals by the generated frequency carrier signals, demodulation of data contained in data symbols based on application of a selected demodulation type, and detection of data contained in the demodulated signals. The RF signals may be received via the receiving antenna 222. The receiver 202 may be operable to process the received RF signals to generate baseband signals. A chip-level baseband signal may comprise a plurality of chips. The chip-level baseband signal may be descrambled based on a PN sequence and despread based on an OVSF code, for example a Walsh code, to generate a symbol-level baseband signal. The symbol-level baseband signal may comprise a plurality of data symbols. The receiver 202 may comprise a rake receiver, which in turn comprises a plurality of rake fingers to process a corresponding plurality of received multipath signals.
The transmitter 204 may comprise suitable logic, circuitry, interfaces and/or code that may be operable to perform transmit functions that may comprise PHY layer function for the transmission or signals. These PHY layer functions may comprise, but are not limited to, modulation of received data to generate data symbols based on application of a selected modulation type, generation of frequency carrier signals corresponding to selected RF channels, for example uplink or downlink channels, the up-conversion of the data symbols by the generated frequency carrier signals, and the generation and amplification of RF signals. The RF signals may be transmitted via the transmitting antenna 232.
The memory 208 may comprise suitable logic, circuitry, interfaces and/or code that may enable storage and/or retrieval of data and/or code. The memory 208 is defined herein as potentially including both volatile and nonvolatile memory and data storage components. Volatile components are those that do not retain data values upon loss of power. Nonvolatile components are those that retain data upon a loss of power. Thus, the memory 208 may comprise, for example, random access memory (RAM), read-only memory (ROM), hard disk drives, solid-state drives, USB flash drives, memory cards accessed via a memory card reader, floppy disks accessed via an associated floppy disk drive, optical discs accessed via an optical disc drive, magnetic tapes accessed via an appropriate tape drive, and/or other memory components, or a combination of any two or more of these memory components. In addition, the RAM may comprise, for example, static random access memory (SRAM), dynamic random access memory (DRAM), or magnetic random access memory (MRAM) and other such devices. The ROM may comprise, for example, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or other like memory device.
The window search module 210 may comprise suitable logic, circuitry and/or code that are operable to perform a window search on a received signal. Some features of the window search module 210 may include parallel searching for multiple scrambling codes (e.g., 8 scrambling codes, or some other number), receive combining diversity support, resource sharing, configurable window span, dual carrier support, scalable power consumption due to a scalable number of active coherent accumulators, and/or other features.
In operation, the receiver 202 may receive signals via the receiving antenna 222. In an exemplary embodiment, the receiver 202 may comprise a rake receiver. The receiver 202 may communicate signals to the processor 206 and/or to the window search module 210.
The window search module 210 may generate timing information that corresponds to each of the fingers in the rake receiver portion of the receiver 202. Each of the fingers in the rake receiver may process a distinct one of a plurality of multipath signals that are received within a delay spread time duration. Based on the received RF signals, the receiver 202 may generate chip-level baseband signals. The rake receiver within receiver 202 may generate one or more symbol-level baseband signals based on a selected one or more OVSF codes and a selected one or more PN sequences. The symbol-level baseband signals may be communicated to the processor 206. The OVSF codes may be selected based on a specified desired user signal. For example, referring to FIG. 1, the rake receiver within receiver 202 associated with mobile communication device MU_—2 may select an OVSF code, WC_—12, or a broadcast OVSF code, WC_broadcast, and a PN sequence, PN_A, which may be utilized to generate the symbol-level baseband signal from the chip-level baseband signal.
The processor 206 may determine which BTSs are associated with a current cell 100 and which BTSs are not associated with the current cell 100. For example, the processor 206 may determine that the base station A 102 is associated with the current cell 100, while the base station C 106 is not associated with the current cell 100. In an exemplary embodiment, the processor 206 may store PN sequences for at least a portion of the BTSs that are associated with the current cell 100. For example, referring to FIG. 1, the processor 206 may generate and/or store corresponding PN sequences, for example PN_A in the memory 208. The PN sequences may be generated on the fly based on the code structure utilized by the BTS and/or based on timing information associated with the BTS. The PN sequence PN_A may be associated with the current cell 100. The processor 206 may correspond to an ARM processor or other processor.
In other exemplary embodiments, the processor 206 may generate and/or store PN sequences for at least a portion of the BTSs that are associated with the current cell 100 and at least a portion of the BTSs that are not associated with the current cell 100. For example, referring to FIG. 1, the processor 206 may generate and/or store corresponding PN sequences, for example PN_A and PN_C in the memory 208. In general, the processor 206 may store the PN sequences for the BTSs from which a mobile communication device, for example the mobile communication device MC_—2 114, may expect to receive signals and the processor 206 may store PN sequences from which the mobile communicating device may not expect to receive signals. The mobile communication device may expect to receive signals, for example common pilot channel (CPICH) signals, from a plurality of BTSs in anticipation of a soft handoff from a current service BTS to a subsequent serving BTS.
In instances in which the transceiver system 200 utilizes a plurality of receiving antennas, for example the receiving antennas 222_1 and 222_2, the transceiver system 200 may utilize receive diversity. In a receive diversity system, the receiver 202 may receive a first set of signals via the receiving antenna 222_1 and a second set of signals via the receiving antenna 222_2. In various embodiments, which may utilize receive diversity, the receiver 202 and/or the window search module 210 may also process signals that are transmitted by BTSs, which utilize signal transmission diversity. Hence, some embodiments support any combination of transmit and receive diversity (i.e., no diversity, receive diversity only, transmit diversity only, or both receive and transmit diversity). In embodiments employing multiple receive antennas 222, the receive diversity adaptation module 211 is configured to selectively enable or disable receive diversity based, for example, on whether a path from one of the receive antennas 222 is comparatively weaker and may be disabled.
Turning now to FIG. 3, shown is an example of a window search module 210 according to various embodiments. The window search module 210 may include Io estimation logic 303, Ec estimation logic 306, control logic 309, sort logic 312, report generation logic 315, and/or other components. The control logic 309 is configured to control the operation of the Ec estimation logic 306, the report generation logic 315, and/or other components. To this end, the control logic 309 is operable to enable various configurations for the window search module 210. Allocation of hardware resources may be performed by the control logic 309. For example, the control logic 309 may distribute the total search resources between active set window search and neighbor window search. Each scrambling code may be controlled independently with its own configuration, including coherent accumulation length, non-coherent accumulation length, transmit diversity, receive diversity, window span, carrier selection, sample start position, slot start position, and/or other parameters.
The Io estimation logic 303 is configured to estimate total energy for each of the received signals 318 a and/or 318 b. Each of the received signals 318 a and 318 b corresponds to a received signal from a respective receive antenna 222 (FIG. 2). The outputs, Io 321 a and Io 321 b, each correspond to a measure of total energy as the “Io” component of an Ec/Io metric. The Io 321 a and 321 b signals are provided to the report generation logic 315. In one embodiment, each received signal 318 is composed of M-bit I/Q (i.e., M-bit I and M-bit Q) complex samples at a CxP sampling rate (e.g., P*3.84 MHz). Inside the Io estimation logic 303, the real values (I components) are squared, the imaginary values (Q components) are squared, and the squared I and Q are accumulated at a chip by P (cxP) rate. For power consumption savings, the Io accumulation may be shared across multiple scrambling codes, with the time-based subcomponents being combined to provide values for the distinct scrambling codes.
The total energy Io for a given receive antenna 222 is computed over the same period as that used for the corresponding Ec estimation which will be explained below. That is, for a given scrambling code, the Io and Ec are computed over the same time period, defined in chips as the product between the coherent and non-coherent accumulation lengths. As a non-limiting example, if the coherent accumulation length is set to 1024 chips and the non-coherent accumulation length is set to 2, the time period is 2048 chips.
The Ec estimation logic 306 is configured to estimate energy per chip (Ec) for each of the received signals 318 a and 318 b. In one embodiment, the Ec estimation logic 306 may support searching multiple scrambling codes on multiple carriers in parallel. Multiple carrier support may be enabled with an extra buffer at the front end, with one buffer per carrier and a multiplex block to select the I/Q stream from the selected carrier to be used as input to the Ec estimation logic 306 and Io estimation logic 303.
Transmit diversity may be enabled in the Ec estimation logic 206 using the property of the CPICH channel that it is orthogonal over a certain period of chips (e.g., 512 chips). Signals from multiple transmit antennas may be independently measured because they become orthogonal. To this end, the signal from a second transmit antenna may be recovered by rotating the descrambled signal by the polarity of the second transmit antenna. This rotation causes the signal from the first transmit antenna to be canceled out.
In one embodiment, the Ec estimation logic 306 supports cx4 resolution for at least a subset of the window span. In one embodiment, the Ec estimation logic 306 provides cx4 resolution over the first 15 chips for channels having closely spaced multiple paths. In other embodiments, the cx4 resolution is supported for the entire window span. Resolution beyond cx2 (cx4 and above) may be obtained via interpolation. The outputs from the Ec estimation logic 306 are provided to the sort logic 312, which sorts the results to provide a set of top Ec measurements to the report generation logic 315 for each of the receive antennas 222. The report generation logic 315 is configured to generate Ec/Io reports, perform finger management functions, and/or cell energy reporting to the network.
The sort logic 312 obtains a number of raw energy samples for each receive antenna 222, e.g., 60, 120, 180, 240, 360, or some other number of samples. As a result of the coherent and non-coherent accumulations over a window span L(i), the overall number of non-coherent accumulator outcomes for a scrambling code i is 4*L(i) for cx4 resolution. The sort logic 312 outputs a number T of top energy samples to the report generation logic 315, e.g., T=32, along with their corresponding position offsets (e.g., 0, 1 . . . 4*L(i)−1 in cx4 resolution). If receive diversity is disabled, the outputs may simply be the top T sorted results out of the raw energy list for the active receive antenna 222.
By contrast, if receive diversity is enabled, the sorting may be done according to at least three different configurations. In a first configuration, per-antenna-based sorting may be used, where the sorting and reporting are done individually for each receive antenna 222. That is to say, the outputs for each receive antenna 222 are the top T energy values for the respective receive antenna 222. In a second configuration, per-antenna-pair-based sorting may be used with reporting on a per-antenna basis (i.e., combined sorting and separate reporting), where the sorting is based on the sum of energy values across receive antennas 222. The outputs are the sorted top T results out of a raw energy sum list across the receive antennas 222. The offsets may correspond to the relative offsets in the raw energy sum list.
In a third configuration, sorting is done on a per-antenna-pair basis, while the report is on a per-antenna-pair basis as well. In such a case, the results are sorted as in the second configuration. Each energy value from a first receive antenna 222 may be scaled by a first antenna combining gain factor, and each energy value from a second receive antenna 222 may be scaled by a second antenna combining gain factor before the results are summed. In contrast to the second configuration, the combined scaled results are reported. The results may be divided by the number of receive antennas 222 to prevent overflow. Which configuration is used may be configurable by the control logic 309.
In one embodiment, the sort logic 312 assigns energy values to bins based on threshold determinations. For example, where 16-bit values are employed, the most-significant-bits of the energy values may be used to assign the values to one of 16 bins. To sort, in one embodiment, the sort logic 312 may find a threshold 2^k, with k as large as possible while more than 32 samples are beyond this threshold. The sort logic 312 may then brute-force sort the samples above the threshold. Each incoming sample is compared with all 32 incumbents. Other sorting techniques may be employed in other embodiments.
The control logic 309 may configure a back-to-back search by the window search module 210. A back-to-back search enables a batch of searches of a single cell back to back, with only one configuration in the beginning. Once a back-to-back search is activated, every search within the same batch employs the same searching parameters.
Moving now to FIG. 4, shown is a block diagram showing portions of the Ec estimation logic 306 according to one embodiment. The Ec estimation logic 306 includes descrambler logic 403, scrambling code generation logic 406, coherent accumulation logic 409, interpolator 412, non-coherent accumulation logic 415, and/or other components.
The received signal 418 is obtained from a chip matched filter and is composed of M-bit I/Q (i.e., M-bit I and M-bit Q) complex samples. The received signal 418 and may be decimated to a chip by 2 (cx2) (e.g., 7.68 MHz) resolution. Chip rate samples may be provided on each of an early bus and a late bus to the descrambler logic 403, where the early and late branches are fed with samples offset by one half-chip sample. The scrambling code generation logic 406 provides one or more scrambling codes to the descrambler logic 403 for use in descrambling the received signal 418. In one embodiment, the descrambler logic 403 may support descrambling of up to K (e.g., K=8) scrambling codes in parallel. By supporting the search of multiple scrambling codes in parallel, the window search is performed faster and with reduced power consumption relative to a one-at-a-time search. With increased window search bandwidth, more cells can be measured over a longer span, and awake time within the discontinuous reception (DRX) mode can be reduced, thus saving power.
For a given scrambling code i, the scrambling code generation logic 406 also provides a shifted version of the same scrambling code, offset by X chips, where X=1, . . . L(i), and L(i) is the configured window span for the search on that scrambling code. For example, if the window span L(i) is configured as 90 chips, the scrambling code generation logic 406 will provide 90 different phases of the same scrambling code, each phase shifted by 1 chip, to cover the entire window span of 90 chips. The same I/Q complex sample is multiplied by L(i) different phases of the scrambling code in parallel. The descrambled I/Q for a given scrambling code phase is referred to as a slice. Thus, there is a bank of L(i) slices per early and late branch, per scrambling code, per receive antenna 222, and per transmit antenna, fed into the coherent accumulation logic 409.
The chip rate descrambled received signals from each of the early and late branch and from each of the L(i) slices are then provided to the coherent accumulation logic 409, which performs coherent accumulation on each of the slices. In one embodiment, the window search module 210 includes M=960 coherent accumulators, hence supporting a total of M=960 slices in parallel. The coherent accumulation results are interpolated to a higher resolution (e.g., cx4 resolution) by the interpolator 412.
The coherent accumulation results (original set of cx2) as well as the interpolated result are provided to the non-coherent accumulation logic 415 to perform a non-coherent accumulation at the higher resolution. In this way, the higher resolution (e.g., cx4 resolution) may be achieved for a window search by doubling only the number of non-coherent accumulators relative to cx2 resolution and keeping the number of coherent accumulators the same as for cx2 resolution. Since the coherent accumulation stage is more computationally intensive than the non-coherent accumulation stage, significant power consumption may be saved. In one embodiment, the window search module includes 1920 (M*N=960*2) non-coherent accumulators. The non-coherent accumulators square the I and Q components at the output of the coherent accumulators and accumulate the squared I and Q over the non-coherent accumulation length.
The interpolator 412 performs an interpolation to a higher subchip resolution. For example, the interpolator 412 may interpolate samples at a chip by 2 (cx2) resolution to a chip by 4 (cx4) resolution. In one embodiment, the even cx4 samples pass unchanged directly from the coherent accumulators to the non-coherent accumulators, while the odd cx4 samples are reconstructed from even cx4 samples nearby by the interpolator 412. The interpolation may be performed, for example, according to the following equation:
$c_{2 m + 1} = \frac{1}{8} (- 1 \cdot c_{2 m - 2} + 5 \cdot c_{2 m} + 5 \cdot c_{2 m + 2} - 1 \cdot c_{2 m + 4})$
The coefficients employed above ([−1 5 5 −1]/8) may be chosen for ease of hardware implementation or for other reasons.
In the case of receive diversity, the components shown in FIG. 4 may be duplicated for the additional receive paths. Receive combining diversity may be supported by weighting and combining the non-coherent accumulation results per receive antenna 222 (FIG. 2). In the case that one of the receive antennas 222 is receiving a signal that is significantly stronger than that received by another one of the receive antennas 222 (e.g., where one received signal meets a signal strength threshold relative to the other received signal), receive selection may be possible by shutting down the weaker receive path components, thereby further saving power consumption in the window search module 210 (FIG. 2). The decision to disable or enable receive diversity based on path strengths may be made by the receive diversity adaptation module 211 (FIG. 2). In the exemplary case of two receive antennas 222, the window search module 210 may be configured to receive with either the first receive antenna 222 only, the second receive antenna 222 only, or with both receive antennas 222.
Next, several non-limiting examples of configurations for the window search module 210 will be discussed. For these examples, assume that a total number of 960 coherent accumulators are available (M=960), and that two base station transmit antennas and/or two receive antennas 222 may be employed. In a first configuration, five scrambling codes are searched in parallel. The first scrambling code is searched with a window span of 15 and with transmit and receive diversity enabled. The search for the first scrambling code uses 15*2*2*2=120 coherent accumulators (15 window span length*2 branches [early/late]*2 receive paths*2 transmit paths).
The second scrambling code is searched with a window span of 30 with receive diversity enabled and transmit diversity disabled. The search for the second scrambling code uses 30*2*2*1=120 coherent accumulators (30 window span length*2 branches [early/late]*2 receive paths*1 transmit path). The third scrambling code is searched with a window span of 60 with receive diversity disabled and transmit diversity enabled. The search for the third scrambling code uses 60*2*1*2=240 coherent accumulators (60 window span length*2 branches [early/late]*1 receive path*2 transmit paths). The fourth scrambling code is searched with a window span of 60 with receive diversity enabled and transmit diversity disabled. The search for the fourth scrambling code uses 60*2*1*2=240 coherent accumulators (60 window span length*2 branches [early/late]*2 receive paths*1 transmit path).
The fifth scrambling code is searched with a window span of 90 with receive and transmit diversity disabled. The search for the fifth scrambling code uses 90*2*1*1=180 coherent accumulators (90 window span length*2 branches [early/late]*1 receive path*1 transmit path). According to the first configuration, 900 coherent accumulators out of 960 total are active, yielding a resource consumption of 93.75%. It is noted that according to the first configuration, each of the five scrambling codes has an independent and different configuration.
In a second configuration, the window search module 210 searches seven scrambling codes in parallel. Three of the scrambling codes employ a window span length of 60 chips, while the remaining four of the scrambling codes employ a window span length of 15 chips. Receive diversity is enabled and transmit diversity is disabled for all seven of the scrambling codes. Each one of the three scrambling codes uses 60*2*2*1=240 coherent accumulators (60 window span length*2 branches [early/late]*2 receive paths*1 transmit path), and each one of the four scrambling codes uses 15*2*2*1=60 coherent accumulators (15 window span length*2 branches [early/late]*2 receive paths*1 transmit path). This results in a total active usage of 960 coherent accumulators, corresponding to 100% utilization. In this configuration, some of the scrambling codes use the same configuration, but it is not a requirement.
In a third configuration, the window search module 210 searches six scrambling codes in parallel. Under the third configuration, receive diversity is disabled as a second receive antenna 222 has been disabled, e.g., because its signal has been determined to be too weak. The first scrambling code is searched with a window span of 60 with transmit diversity enabled. The search for the first scrambling code uses 60*2*1*2=240 coherent accumulators (60 window span length*2 branches [early/late]*1 receive path*2 transmit paths). The second scrambling code is searched with a window span of 90 with transmit diversity disabled. The search for the second scrambling code uses 90*2*1*1=180 coherent accumulators (90 window span length*2 branches [early/late]*1 receive path*1 transmit path).
The third scrambling code is searched with a window span of 60 with transmit diversity disabled. The search for the third scrambling code uses 60*2*1*1==120 coherent accumulators (60 window span length*2 branches [early/late]*1 receive path*1 transmit path). The fourth scrambling code is searched with a window span of 30 with transmit diversity disabled. The search for the fourth scrambling code uses 30*2*1*1=60 coherent accumulators (30 window span length*2 branches [early/late]*1 receive path*1 transmit path). The fifth scrambling code is searched with a window span of 15 with transmit diversity enabled. The search for the fifth scrambling code uses 15*2*1*2=60 coherent accumulators (15 window span length*2 branches [early/late]*1 receive path*2 transmit paths).
The sixth scrambling code is searched with a window span of 15 with transmit diversity disabled. The search for the sixth scrambling code uses 15*2*1*1=30 coherent accumulators (15 window span length*2 branches [early/late]*1 receive path*1 transmit path). Under the third configuration, no receive diversity is configured for any of the six scrambling codes. Consequently, only a subset of the total resource is active, resulting in power consumption savings. In this example, 690 coherent accumulators are in active use out of 960, resulting in 71.88% utilization. It is noted that even if receive diversity is active, the window search module 210 may still be configured to despread signals from both receive antennas 222 or either one of the two.
With reference to FIG. 5, shown is a flowchart that provides one example of the operation of a portion of the window search module 210 (FIG. 2) according to various embodiments. It is understood that the flowchart of FIG. 5 provides merely an example of the many different types of functional arrangements that may be employed to implement the operation of the portion of the window search module 210 as described herein. As an alternative, the flowchart of FIG. 5 may be viewed as depicting an example of steps of a method implemented in the transceiver system 200 (FIG. 2) according to one or more embodiments.
Beginning with box 503, the window search module 210 configures window search logic including M coherent accumulators to perform a window search on a received signal for a set of scrambling codes i. Each one of the set of scrambling codes is to be searched for a respective window span L(i). In box 506, the window search module 210 performs the window search for each of the set of scrambling codes i in parallel in the window search logic.
The window searches utilize a scalable number M1 of the coherent accumulators. M1 may be determined based at least in part on the number of scrambling codes i, the respective window spans L(i) to be searched, whether receive diversity is enabled, whether transmit diversity is enabled, and/or on other factors. Receive diversity and/or transmit diversity may be enabled on a per-scrambling-code basis. In one example, M1 may equal M. Alternatively, if M1 is less than M, one or more of the M coherent accumulators may be inactive and in a reduced power consumption state during the window search due to the scalability of the window search logic.
In box 509, the window search module 210 sorts the respective set of energy results for each scrambling code i based at least in part on a selected sorting approach. If receive diversity is not enabled, the selected sorting approach may default to per-antenna-based sorting for the active receive antenna 222 (FIG. 2). If receive diversity is enabled, the selected sorting approach may be chosen from per-antenna-based sorting or per-antenna-pair-based sorting.
In box 512, the window search module 210 reports the respective sorted set of energy results for each scrambling code i based at least in part on a selected reporting approach. When per-antenna-based sorting is used, the selected reporting approach may be per-antenna-based reporting. When per-antenna-pair-based sorting is used, the selected reporting approach may be per-antenna-based reporting or per-antenna-pair-based reporting. Subsequently, the window search module 210 may be reconfigured for a different number of scrambling codes, different window spans, and different receive and transmit diversity settings. Thereafter, the portion of the window search module 210 ends.
With reference to FIG. 6, shown is a flowchart that provides one example of the operation of another portion of the window search module 210 (FIG. 2) according to various embodiments. In particular, the portion of the window search module 210 depicted in FIG. 6 may correspond to a portion of the Ec estimation logic 306 (FIG. 3). It is understood that the flowchart of FIG. 6 provides merely an example of the many different types of functional arrangements that may be employed to implement the operation of the portion of the window search module 210 as described herein. As an alternative, the flowchart of FIG. 6 may be viewed as depicting an example of steps of a method implemented in the transceiver system 200 (FIG. 2) according to one or more embodiments.
Beginning with box 601, the window search module 210 is configured to perform a series of operations in parallel across multiple scrambling codes and, potentially, multiple transmit antennas and multiple receive antennas 222 (FIG. 2). In box 602, for a given scrambling code i, the scrambling code generation logic 406 provides L(i) shifted versions of the same scrambling code i, each offset by 1 chip (or some other predetermined number of chips), where L(i) is the configured window span in chips for that search. In box 603, the window search module 210 descrambles the received signal for Tx/Rx antenna pair (t, r) for each of the L(i) chip positions, at a first subchip resolution, e.g., cx2 resolution or some other resolution.
In box 606, the window search module 210 performs a coherent accumulation over a length of CI chips on the descrambled received signal for Tx/Rx antenna pair (t, r) for each of the L(i) chip positions, at the first subchip resolution. In box 609, the window search module 210 interpolates the coherent accumulation result for Tx/Rx antenna pair (t, r) for each of the L(i) chip positions to a second subchip resolution, e.g., cx4 resolution or some other resolution. In box 612, the window search module 210 performs a non-coherent accumulation over a length of NCI samples at the second chip resolution using the interpolated coherent accumulation result. In various embodiments, the window search module 210 includes a set of M coherent accumulators and a set of N*M non-coherent accumulators, where N is greater than 1. The value of N may correspond to an interpolation factor employed in the interpolation of box 609.
If embodied in dedicated hardware, the systems described herein can be implemented as a circuit or state machine that employs any one of or a combination of a number of technologies. These technologies may include, but are not limited to, discrete logic circuits having logic gates for implementing various logic functions upon an application of one or more data signals, application specific integrated circuits having appropriate logic gates, or other components, etc. Such technologies are generally well known by those skilled in the art and, consequently, are not described in detail herein. Although the various systems described herein may be embodied in dedicated hardware as discussed above, as an alternative the same may also be embodied in software or code executed by general purpose hardware or a combination of software/general purpose hardware and dedicated hardware.
The flowcharts of FIGS. 5 and 6 show the functionality and operation of an implementation of portions of the window search module 210. If embodied in software, each block may represent a module, segment, or portion of code that comprises program instructions to implement the specified logical function(s). The program instructions may be embodied in the form of source code that comprises human-readable statements written in a programming language or machine code that comprises numerical instructions recognizable by a suitable execution system such as a processor 206 (FIG. 2) in a computer system or other system. The machine code may be converted from the source code, etc. If embodied in hardware, each block may represent a circuit or a number of interconnected circuits to implement the specified logical function(s).
Although the flowcharts of FIGS. 5 and 6 show a specific order of execution, it is understood that the order of execution may differ from that which is depicted. For example, the order of execution of two or more blocks may be scrambled relative to the order shown. Also, two or more blocks shown in succession in FIGS. 5 and 6 may be executed concurrently or with partial concurrence. Further, in some embodiments, one or more of the blocks shown in FIGS. 5 and 6 may be skipped or omitted. In addition, any number of counters, state variables, warning semaphores, or messages might be added to the logical flow described herein, for purposes of enhanced utility, accounting, performance measurement, or providing troubleshooting aids, etc. It is understood that all such variations are within the scope of the present disclosure.
Also, any logic or application described herein that comprises software or code can be embodied in any non-transitory computer-readable medium for use by or in connection with an instruction execution system such as, for example, a processor 206 in a computer system or other system. In this sense, the logic may comprise, for example, statements including instructions and declarations that can be fetched from the computer-readable medium and executed by the instruction execution system. In the context of the present disclosure, a “computer-readable medium” can be any medium that can contain, store, or maintain the logic or application described herein for use by or in connection with the instruction execution system.
The computer-readable medium can comprise any one of many physical media such as, for example, magnetic, optical, or semiconductor media. More specific examples of a suitable computer-readable medium would include, but are not limited to, magnetic tapes, magnetic floppy diskettes, magnetic hard drives, memory cards, solid-state drives, USB flash drives, or optical discs. Also, the computer-readable medium may be a random access memory (RAM) including, for example, static random access memory (SRAM) and dynamic random access memory (DRAM), or magnetic random access memory (MRAM). In addition, the computer-readable medium may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or other type of memory device.
It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims

Therefore, at least the following is claimed:

1. A system for cell measurement, comprising:

a wireless communications device including at least one processor and/or circuit configured to:

descramble a received signal;

perform a coherent accumulation on the descrambled received signal at a first subchip resolution to produce a coherent accumulation result;

interpolate the coherent accumulation result to a second subchip resolution; and

perform a non-coherent accumulation on the descrambled received signal at the second subchip resolution based at least in part on the interpolated coherent accumulation result.

2. The system of claim 1, wherein the received signal corresponds to a wideband code division multiple access (WCDMA) signal.

3. The system of claim 1, wherein the coherent accumulation and the non-coherent accumulation are employed as part of a window search.

4. The system of claim 3, wherein the window search is configurable as to a plurality of scrambling codes i to be searched in parallel over a respective window span L(i) in chips.

5. The system of claim 4, wherein the wireless communications device is further configured to offset each scrambling code i phase by a predetermined number of chips for L(i) chips to cover the respective window span L(i).

6. The system of claim 4, wherein the window search is configurable as to a plurality of transmit antenna and receive antenna pairs (t, r) such that the scrambling codes i are searched in parallel over the respective window span L(i) for each of the transmit antenna and receive antenna pairs (t, r).

7. The system of claim 4, wherein the at least one processor and/or circuit includes a set of M coherent accumulators to perform the coherent accumulation, wherein a scalable subset of the M coherent accumulators are active based at least in part on a number of scrambling codes i to be searched, the respective window spans L(i), a number of receive antennas, and a number of transmit antennas.

8. The system of claim 1, wherein the at least one processor and/or circuit includes a set of M coherent accumulators to perform the coherent accumulation and a set of M*N non-coherent accumulators to perform the non-coherent accumulation, wherein N corresponds to an interpolation factor used in the interpolation.

9. A method for cell measurement in a wireless communications device, comprising:

configuring window search logic including M coherent accumulators to perform a window search on a received signal for a set of scrambling codes i, wherein each one of the set of scrambling codes i is to be searched for a respective window span L1(i); and

performing the window search for each of the set of scrambling codes i in parallel in the window search logic, wherein the window search utilizes a scalable number M1 of the coherent accumulators based at least in part on a number of scrambling codes i and the respective window spans L1(i) to be searched, and M1 is less than or equal to M.

10. The method of claim 9, further comprising:

reconfiguring the window search logic to perform another window search on the received signal for another set of scrambling codes i, wherein each one of the other set of scrambling codes i is to be searched for a respective window span L2(i); and

performing the other window search for each of the other set of scrambling codes i in parallel in the window search logic, wherein the other window search utilizes M2 of the coherent accumulators, M2 is less than or equal to M, and M2 does not equal M1.

11. The method of claim 10, wherein the set of scrambling codes i and the other set of scrambling codes i each have a different number of scrambling codes.

12. The method of claim 9, wherein M1 is less than M, and at least one of the M coherent accumulators is inactive and in a reduced power consumption state during the window search.

13. The method of claim 9, wherein M1 equals M.

14. The method of claim 9, wherein the window search utilizes the scalable number M1 of the coherent accumulators based at least in part on whether transmit diversity is enabled for each respective scrambling code i.

15. The method of claim 9, wherein the window search utilizes the scalable number M1 of the coherent accumulators based at least in part on whether receive diversity is enabled for each respective scrambling code i.

16. The method of claim 9, wherein performing the window search comprises:

descrambling the received signal;

performing a coherent accumulation on the descrambled received signal at a first subchip resolution to produce a coherent accumulation result;

interpolating the coherent accumulation result to a second subchip resolution; and

performing a non-coherent accumulation on the descrambled received signal at the second subchip resolution based at least in part on the interpolated coherent accumulation result.

17. The method of claim 16, wherein the window search logic includes a set of N*M non-coherent accumulators, N is based at least in part on an interpolation factor relating the first subchip resolution to the second subchip resolution, and N is greater than 1.

18. A system for cell measurement, the system comprising:

perform a window search for each of a set of scrambling codes i in parallel, wherein the window search utilizes a configurable number M1 of a set of M coherent accumulators based at least in part on a number of scrambling codes i and a respective window span L1(i) for each scrambling code i to be searched, and M1 is less than or equal to M, the window search producing a respective set of energy results; and

sort the respective set of energy results for each scrambling code i based at least in part on a selected sorting approach, the selected sorting approach being selected from per-receive-antenna-based sorting or per-receive-antenna-pair-based sorting.

19. The system of claim 18, wherein the at least one processor and/or circuit is further configured to:

report the respective sorted set of energy results for each scrambling code i based at least in part on a selected reporting approach; and

wherein:

when the selected sorting approach is per-receive-antenna-based sorting, the selected reporting approach is per-receive-antenna-based reporting; and

when the selected sorting approach is per-receive-antenna-pair-based sorting, the selected reporting approach is selected from per-receive-antenna-based reporting or per-receive-antenna-pair-based reporting.

20. The system of claim 18, wherein the at least one processor and/or circuit is further configured to disable one of a plurality of receive antenna paths for the window search in response to determining that a signal strength associated with the one of the receive antenna paths meets a threshold.