US20110049473A1 - Film Wrapped NFET Nanowire - Google Patents
Film Wrapped NFET Nanowire Download PDFInfo
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- US20110049473A1 US20110049473A1 US12/549,741 US54974109A US2011049473A1 US 20110049473 A1 US20110049473 A1 US 20110049473A1 US 54974109 A US54974109 A US 54974109A US 2011049473 A1 US2011049473 A1 US 2011049473A1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Definitions
- This disclosure relates generally to the field of semiconductor structure, and specifically to inducing tensile stress in a nanostructure of a semiconductor structure.
- a semiconductor structure may comprise a number of field effect transistors (FETs); each FET may include a source, a drain, a channel, and a gate.
- the channel connects the source and the drain, and electrical current flows through the channel from the source to the drain.
- the electrical current flow is induced in the channel by a voltage applied at the gate.
- the size of a FET is related to the electrical conductivity of the material that comprises the channel. If the material that comprises the channel has a relatively high conductivity, the FET may be made correspondingly smaller.
- a FET may comprise an n-channel field effect transistor (NFET) or a p-channel field effect transistor (PFET).
- the electrical conductivity of an NFET is determined by the electron mobility of the NFET channel.
- the electron mobility of the NFET channel is related to the amount of tensile stress in the NFET material; more specifically, increased tensile stress in the NFET material may raise the electron mobility of some NFET materials.
- a channel may comprise a nanostructure, also referred to as a nanowire.
- An exemplary nanowire may have a cross-sectional area of about 20 nanometers (nm) by 20 nm or less. Due to the small size and freestanding nature of a nanowire, inducing tensile stress in a nanowire may present difficulties.
- a semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire.
- NFET n-channel field effect transistor
- a method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.
- NFET n-channel field effect transistor
- FIG. 1 illustrates an embodiment of a cross-section of a semiconductor structure after application of a layer of germanium (Ge).
- FIG. 2 illustrates an embodiment of a cross-section of a semiconductor structure after thermal mixing of silicon (Si) and Ge layers.
- FIG. 3 illustrates an embodiment of a cross-section of a semiconductor structure after application of photoresist.
- FIG. 4 illustrates an embodiment of a cross-section of a semiconductor structure after initial formation of the nanowire regions.
- FIG. 5 illustrates an embodiment of a cross-section of a semiconductor structure after removal of the photoresist and etching of the buried insulator layer.
- FIG. 6 illustrates an embodiment of a cross-section of a semiconductor structure after oxide thinning
- FIG. 7 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si wrapping on the SiGe wire wherein the PFET Si wire is thickened
- FIG. 8 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si wrapping on the SiGe wire wherein the PFET Si wire is not thickened.
- FIG. 9 illustrates an embodiment of a side view of a semiconductor structure comprising a wrapped NFET nanowire.
- FIG. 10 illustrates an embodiment of a method for a process of making a semiconductor structure comprising a wrapped NFET nanowire.
- Embodiments of a wrapped NFET nanowire are provided, with exemplary embodiments being discussed below in detail.
- a film wrapping on an NFET nanowire may enhance tensile stress in the NFET nanowire, enhancing the electron mobility in the NFET nanowire.
- wrapping silicon (Si) around a silicon germanium (SiGe) core may provide tensile stress in an NFET nanowire.
- the cross-sectional area of the SiGe core is 25 nm 2 .
- the SiGe core is relaxed (i.e., has minimal stress) because it is freestanding.
- a silicon film wrapping that conforms to the SiGe core potentially causes a tensile stress in the Si of about 1.75 gigapascals (GPa). This tensile stress may increase the electron mobility of the overall nanowire, which comprises the SiGe core and the Si film wrapping.
- FIG. 1 illustrates an embodiment of a cross-section of a semiconductor structure after application of a layer 50 of Ge.
- Layer 10 comprises a substrate, which may comprise silicon in some embodiments.
- Layer 20 comprises buried insulator, which may comprise a dielectric material such as oxide in some embodiments.
- Layer 50 comprises Ge, and is disposed on Si layer 40 .
- Layer 30 comprises Si.
- FIG. 2 illustrates an embodiment of a cross-section of a semiconductor structure after thermal mixing of Si layer 40 and Ge layer 50 .
- Layers 40 and 50 of FIG. 1 have been thermally mixed, resulting in SiGe layer 60 .
- Layer 30 comprises Si
- layer 20 comprises buried insulator
- layer 10 comprises substrate.
- SiGe layer 60 may be thinned, or Si layer 30 may be thickened, as necessary in order to achieve appropriate dimensions for layers 30 and 60 .
- FIG. 3 illustrates an embodiment of a cross-section of a semiconductor structure after application of photoresist.
- Photoresist layers 70 a and 70 b are placed on SiGe layer 60 and Si layer 30 , respectively, to define nanowire regions.
- Layer 20 comprises buried insulator, and layer 10 comprises substrate.
- FIG. 4 illustrates an embodiment of a cross-section of a semiconductor structure after initial formation of PFET and NFET regions.
- the SiGe layer 60 and Si layer 30 have been etched down to buried insulator layer 20 , leaving SiGe NFET region 61 under photoresist layer 70 a, and Si PFET region 31 under photoresist layer 70 b.
- Layer 10 comprises substrate.
- FIG. 5 illustrates an embodiment of a cross-section of a semiconductor structure after removal of the photoresist and etching of the buried insulator layer.
- the photoresist layers 70 a and 70 b have been etched off, along with a portion of buried insulator layer 20 , resulting in freestanding SiGe NFET region 61 , freestanding Si PFET region 31 , and buried insulator layers 20 a, 20 b, and 20 c.
- Layer 10 comprises substrate.
- NFET region 61 and PFET region 31 are tethered to silicon pads 901 and 903 , as discussed below with regards to FIG. 9 .
- FIG. 6 illustrates an embodiment of a cross-section of a semiconductor structure after oxide thinning.
- Oxide thinning is performed on SiGe NFET region 61 and Si PFET region 31 , resulting in SiGe core 62 and Si wire 32 .
- SiGe core 62 and Si wire 32 may each have a cross-sectional area of about 20 nm by about 20 nm or less.
- Layers 20 a, 20 b , and 20 c comprise buried insulator, and layer 10 comprises substrate.
- FIG. 7 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si film wrapping 80 on SiGe core 62 and thickening of Si wire 32 , resulting in thickened Si PFET nanowire 34 .
- Layers 20 a, 20 b, and 20 c comprise buried insulator, and layer 10 comprises substrate.
- Si film wrapping 80 provides tensile stress in the NFET; together, Si film wrapping 80 and SiGe core 62 form an NFET nanowire.
- Si film wrapping 80 may have a thickness between about 1 and 2 nm.
- FIG. 8 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si film wrapping 80 on SiGe core 62 in which Si wire 32 is not thickened.
- the Si PFET wire 32 of FIG. 6 is masked, and Si film wrapping 80 is grown on SiGe NFET wire 62 .
- Layers 20 a, 20 b, and 20 c comprise buried insulator, and layer 10 comprises substrate.
- Si film wrapping 80 provides tensile stress in the NFET; together, Si film wrapping 80 and SiGe core 62 form an NFET nanowire.
- Si wire 32 comprises a PFET nanowire.
- Si film wrapping 80 may have a thickness between about 1 and 2 nm.
- FIG. 9 illustrates a side view of an embodiment of a semiconductor structure comprising a wrapped NFET nanowire.
- SiGe core 62 is surrounded by Si wrapping 80 , together forming an NFET nanowire.
- Film wrapping 80 provides tensile stress in the NFET nanowire.
- Pad 901 and pedestal 902 are on the source side of the semiconductor structure, and pad 903 and pedestal 904 are on the drain side of the semiconductor structure.
- Electrical current flows through SiGe core 62 and Si film wrapping 80 from source-side pad 901 to drain-side pad 903 according to a voltage applied at gate 905 .
- Layer 20 comprises buried insulator, and layer 10 comprises substrate.
- FIG. 10 illustrates a method 1000 for a process of making a semiconductor structure comprising a film wrapped NFET nanowire.
- a germanium layer is disposed on a portion of an exposed silicon layer, as is shown in FIG. 1 .
- the germanium layer and the silicon layer are thermally mixed, resulting in an exposed SiGe layer and an exposed Si layer, as is shown in FIG. 2 .
- a layer of photoresist is applied to a portion of the SiGe layer, and a layer of photoresist is applied to the Si layer, as is shown in FIG. 3 .
- the exposed SiGe and Si layers are etched down to a buried insulator layer, leaving the portions of the SiGe and the Si located under the photoresist layers, as is shown in FIG. 4 .
- the photoresist is removed, and the buried insulator is etched, resulting in a freestanding SiGe NFET region and a freestanding Si PFET region, as is shown in FIG. 5 .
- the freestanding SiGe NFET region and the freestanding Si PFET region are thinned, resulting in a SiGe NFET core and a Si PFET wire, as is shown in FIG. 6 .
- a Si film wrapping is grown.
- the Si PFET wire is masked, and the Si film wrapping is grown on the SiGe core, forming the NFET nanowire, as is shown in FIG. 8 .
- the Si PFET wire is not masked, and Si is also grown on the Si PFET wire, resulting in a thickened Si PFET nanowire, as is shown in FIG. 7 .
- the Si film wrapping provides tensile stress in the NFET nanowire, resulting in enhanced electrical conductivity in the NFET nanowire.
- the technical effects and benefits of exemplary embodiments include increased tensile stress in an NFET nanowire, thereby increasing the electrical conductivity of the nanowire and allowing for reduction in size of a semiconductor device.
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Abstract
Description
- This disclosure relates generally to the field of semiconductor structure, and specifically to inducing tensile stress in a nanostructure of a semiconductor structure.
- A semiconductor structure may comprise a number of field effect transistors (FETs); each FET may include a source, a drain, a channel, and a gate. The channel connects the source and the drain, and electrical current flows through the channel from the source to the drain. The electrical current flow is induced in the channel by a voltage applied at the gate. The size of a FET is related to the electrical conductivity of the material that comprises the channel. If the material that comprises the channel has a relatively high conductivity, the FET may be made correspondingly smaller.
- A FET may comprise an n-channel field effect transistor (NFET) or a p-channel field effect transistor (PFET). The electrical conductivity of an NFET is determined by the electron mobility of the NFET channel. In some semiconductor materials, the electron mobility of the NFET channel is related to the amount of tensile stress in the NFET material; more specifically, increased tensile stress in the NFET material may raise the electron mobility of some NFET materials.
- In a relatively small FET, a channel may comprise a nanostructure, also referred to as a nanowire. An exemplary nanowire may have a cross-sectional area of about 20 nanometers (nm) by 20 nm or less. Due to the small size and freestanding nature of a nanowire, inducing tensile stress in a nanowire may present difficulties.
- In one aspect, a semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire.
- In one aspect, a method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.
- Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.
- Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:
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FIG. 1 illustrates an embodiment of a cross-section of a semiconductor structure after application of a layer of germanium (Ge). -
FIG. 2 illustrates an embodiment of a cross-section of a semiconductor structure after thermal mixing of silicon (Si) and Ge layers. -
FIG. 3 illustrates an embodiment of a cross-section of a semiconductor structure after application of photoresist. -
FIG. 4 illustrates an embodiment of a cross-section of a semiconductor structure after initial formation of the nanowire regions. -
FIG. 5 illustrates an embodiment of a cross-section of a semiconductor structure after removal of the photoresist and etching of the buried insulator layer. -
FIG. 6 illustrates an embodiment of a cross-section of a semiconductor structure after oxide thinning -
FIG. 7 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si wrapping on the SiGe wire wherein the PFET Si wire is thickened -
FIG. 8 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si wrapping on the SiGe wire wherein the PFET Si wire is not thickened. -
FIG. 9 illustrates an embodiment of a side view of a semiconductor structure comprising a wrapped NFET nanowire. -
FIG. 10 illustrates an embodiment of a method for a process of making a semiconductor structure comprising a wrapped NFET nanowire. - Embodiments of a wrapped NFET nanowire are provided, with exemplary embodiments being discussed below in detail.
- A film wrapping on an NFET nanowire may enhance tensile stress in the NFET nanowire, enhancing the electron mobility in the NFET nanowire. In an exemplary embodiment, wrapping silicon (Si) around a silicon germanium (SiGe) core may provide tensile stress in an NFET nanowire.
- For an example SiGe core with a cross section that comprises a square with a side length of 5 nanometers (nm), the cross-sectional area of the SiGe core is 25 nm2. The SiGe core is relaxed (i.e., has minimal stress) because it is freestanding. A silicon film wrapping that conforms to the SiGe core potentially causes a tensile stress in the Si of about 1.75 gigapascals (GPa). This tensile stress may increase the electron mobility of the overall nanowire, which comprises the SiGe core and the Si film wrapping.
-
FIG. 1 illustrates an embodiment of a cross-section of a semiconductor structure after application of alayer 50 of Ge.Layer 10 comprises a substrate, which may comprise silicon in some embodiments.Layer 20 comprises buried insulator, which may comprise a dielectric material such as oxide in some embodiments.Layer 50 comprises Ge, and is disposed onSi layer 40.Layer 30 comprises Si. -
FIG. 2 illustrates an embodiment of a cross-section of a semiconductor structure after thermal mixing ofSi layer 40 andGe layer 50.Layers FIG. 1 have been thermally mixed, resulting inSiGe layer 60.Layer 30 comprises Si,layer 20 comprises buried insulator, andlayer 10 comprises substrate. In some embodiments,SiGe layer 60 may be thinned, orSi layer 30 may be thickened, as necessary in order to achieve appropriate dimensions forlayers -
FIG. 3 illustrates an embodiment of a cross-section of a semiconductor structure after application of photoresist.Photoresist layers SiGe layer 60 andSi layer 30, respectively, to define nanowire regions.Layer 20 comprises buried insulator, andlayer 10 comprises substrate. -
FIG. 4 illustrates an embodiment of a cross-section of a semiconductor structure after initial formation of PFET and NFET regions. The SiGelayer 60 andSi layer 30 have been etched down to buriedinsulator layer 20, leaving SiGe NFETregion 61 underphotoresist layer 70 a, and Si PFETregion 31 underphotoresist layer 70 b.Layer 10 comprises substrate. -
FIG. 5 illustrates an embodiment of a cross-section of a semiconductor structure after removal of the photoresist and etching of the buried insulator layer. Thephotoresist layers insulator layer 20, resulting in freestanding SiGe NFETregion 61, freestanding SiPFET region 31, and buriedinsulator layers Layer 10 comprises substrate. NFETregion 61 andPFET region 31 are tethered tosilicon pads FIG. 9 . -
FIG. 6 illustrates an embodiment of a cross-section of a semiconductor structure after oxide thinning. Oxide thinning is performed on SiGe NFETregion 61 and SiPFET region 31, resulting inSiGe core 62 andSi wire 32. SiGecore 62 andSi wire 32 may each have a cross-sectional area of about 20 nm by about 20 nm or less.Layers layer 10 comprises substrate. -
FIG. 7 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si film wrapping 80 onSiGe core 62 and thickening ofSi wire 32, resulting in thickenedSi PFET nanowire 34.Layers layer 10 comprises substrate. Si film wrapping 80 provides tensile stress in the NFET; together, Si film wrapping 80 andSiGe core 62 form an NFET nanowire. Si film wrapping 80 may have a thickness between about 1 and 2 nm. -
FIG. 8 illustrates an embodiment of a cross-section of a semiconductor structure after formation of a Si film wrapping 80 onSiGe core 62 in whichSi wire 32 is not thickened. TheSi PFET wire 32 ofFIG. 6 is masked, and Si film wrapping 80 is grown onSiGe NFET wire 62.Layers layer 10 comprises substrate. Si film wrapping 80 provides tensile stress in the NFET; together, Si film wrapping 80 andSiGe core 62 form an NFET nanowire.Si wire 32 comprises a PFET nanowire. Si film wrapping 80 may have a thickness between about 1 and 2 nm. -
FIG. 9 illustrates a side view of an embodiment of a semiconductor structure comprising a wrapped NFET nanowire.SiGe core 62 is surrounded by Si wrapping 80, together forming an NFET nanowire. Film wrapping 80 provides tensile stress in the NFET nanowire.Pad 901 andpedestal 902 are on the source side of the semiconductor structure, andpad 903 andpedestal 904 are on the drain side of the semiconductor structure. Electrical current flows throughSiGe core 62 and Si film wrapping 80 from source-side pad 901 to drain-side pad 903 according to a voltage applied atgate 905.Layer 20 comprises buried insulator, andlayer 10 comprises substrate. -
FIG. 10 illustrates amethod 1000 for a process of making a semiconductor structure comprising a film wrapped NFET nanowire. Inblock 1001, a germanium layer is disposed on a portion of an exposed silicon layer, as is shown inFIG. 1 . Inblock 1002, the germanium layer and the silicon layer are thermally mixed, resulting in an exposed SiGe layer and an exposed Si layer, as is shown inFIG. 2 . Inblock 1003, a layer of photoresist is applied to a portion of the SiGe layer, and a layer of photoresist is applied to the Si layer, as is shown inFIG. 3 . Inblock 1004, the exposed SiGe and Si layers are etched down to a buried insulator layer, leaving the portions of the SiGe and the Si located under the photoresist layers, as is shown inFIG. 4 . Inblock 1005, the photoresist is removed, and the buried insulator is etched, resulting in a freestanding SiGe NFET region and a freestanding Si PFET region, as is shown inFIG. 5 . Inblock 1006, the freestanding SiGe NFET region and the freestanding Si PFET region are thinned, resulting in a SiGe NFET core and a Si PFET wire, as is shown inFIG. 6 . Inblock 1007, a Si film wrapping is grown. In some embodiments, the Si PFET wire is masked, and the Si film wrapping is grown on the SiGe core, forming the NFET nanowire, as is shown inFIG. 8 . In other embodiments, the Si PFET wire is not masked, and Si is also grown on the Si PFET wire, resulting in a thickened Si PFET nanowire, as is shown inFIG. 7 . The Si film wrapping provides tensile stress in the NFET nanowire, resulting in enhanced electrical conductivity in the NFET nanowire. - The technical effects and benefits of exemplary embodiments include increased tensile stress in an NFET nanowire, thereby increasing the electrical conductivity of the nanowire and allowing for reduction in size of a semiconductor device.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (14)
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TW099128899A TW201110353A (en) | 2009-08-28 | 2010-08-27 | Film wrapped NFET nanowire |
US13/184,004 US8232165B2 (en) | 2009-08-28 | 2011-07-15 | Film wrapped NFET nanowire |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110070734A1 (en) * | 2009-09-18 | 2011-03-24 | Commissariat A L'energie Atomique Et Aux Ene. Alt. | Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate |
US20150179781A1 (en) * | 2013-12-20 | 2015-06-25 | International Business Machines Corporation | Strained semiconductor nanowire |
US9196715B2 (en) | 2012-12-28 | 2015-11-24 | Renesas Electronics Corporation | Field effect transistor with channel core modified to reduce leakage current and method of fabrication |
FR3051970A1 (en) * | 2016-05-25 | 2017-12-01 | Commissariat Energie Atomique | IMPLEMENTING A SHAPED CHANNEL STRUCTURE OF A PLURALITY OF CONTAINING SEMICONDUCTOR BARS |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140354455A1 (en) * | 2013-05-31 | 2014-12-04 | Honeywell International Inc. | System and method for increasing situational awareness by displaying altitude filter limit lines on a vertical situation display |
US9607900B1 (en) | 2015-09-10 | 2017-03-28 | International Business Machines Corporation | Method and structure to fabricate closely packed hybrid nanowires at scaled pitch |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020129761A1 (en) * | 2001-01-18 | 2002-09-19 | Tomohide Takami | Nanofiber and method of manufacturing nanofiber |
US20030089899A1 (en) * | 2000-08-22 | 2003-05-15 | Lieber Charles M. | Nanoscale wires and related devices |
US6720240B2 (en) * | 2000-03-29 | 2004-04-13 | Georgia Tech Research Corporation | Silicon based nanospheres and nanowires |
US20040112964A1 (en) * | 2002-09-30 | 2004-06-17 | Nanosys, Inc. | Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites |
US20050064185A1 (en) * | 2003-08-04 | 2005-03-24 | Nanosys, Inc. | System and process for producing nanowire composites and electronic substrates therefrom |
US7186669B2 (en) * | 2001-03-29 | 2007-03-06 | Georgia Tech Research Corporation | Silicon based nanospheres and nanowires |
US20070176824A1 (en) * | 2002-09-30 | 2007-08-02 | Nanosys Inc. | Phased array systems and methods |
US7358160B2 (en) * | 2006-05-30 | 2008-04-15 | Sharp Laboratories Of America, Inc. | Method of selective formation of compound semiconductor-on-silicon wafer with silicon nanowire buffer layer |
US20080135886A1 (en) * | 2006-12-08 | 2008-06-12 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US20080149941A1 (en) * | 2006-05-30 | 2008-06-26 | Tingkai Li | Compound Semiconductor-On-Silicon Wafer with a Silicon Nanowire Buffer Layer |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2442985C (en) * | 2001-03-30 | 2016-05-31 | The Regents Of The University Of California | Methods of fabricating nanostructures and nanowires and devices fabricated therefrom |
WO2007005312A1 (en) * | 2005-06-29 | 2007-01-11 | Amberwave Systems Corporation | Material systems for dielectrics and metal electrodes and methods for formation thereof |
US8063450B2 (en) * | 2006-09-19 | 2011-11-22 | Qunano Ab | Assembly of nanoscaled field effect transistors |
US20100221894A1 (en) | 2006-12-28 | 2010-09-02 | Industry-Academic Cooperation Foundation, Yonsei University | Method for manufacturing nanowires by using a stress-induced growth |
EP2257974A1 (en) * | 2008-02-26 | 2010-12-08 | Nxp B.V. | Method for manufacturing semiconductor device and semiconductor device |
-
2009
- 2009-08-28 US US12/549,741 patent/US20110049473A1/en not_active Abandoned
-
2010
- 2010-08-05 WO PCT/EP2010/061404 patent/WO2011023520A1/en active Application Filing
- 2010-08-27 TW TW099128899A patent/TW201110353A/en unknown
-
2011
- 2011-07-15 US US13/184,004 patent/US8232165B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6720240B2 (en) * | 2000-03-29 | 2004-04-13 | Georgia Tech Research Corporation | Silicon based nanospheres and nanowires |
US20030089899A1 (en) * | 2000-08-22 | 2003-05-15 | Lieber Charles M. | Nanoscale wires and related devices |
US20020129761A1 (en) * | 2001-01-18 | 2002-09-19 | Tomohide Takami | Nanofiber and method of manufacturing nanofiber |
US7186669B2 (en) * | 2001-03-29 | 2007-03-06 | Georgia Tech Research Corporation | Silicon based nanospheres and nanowires |
US20040112964A1 (en) * | 2002-09-30 | 2004-06-17 | Nanosys, Inc. | Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites |
US20070176824A1 (en) * | 2002-09-30 | 2007-08-02 | Nanosys Inc. | Phased array systems and methods |
US20050064185A1 (en) * | 2003-08-04 | 2005-03-24 | Nanosys, Inc. | System and process for producing nanowire composites and electronic substrates therefrom |
US7358160B2 (en) * | 2006-05-30 | 2008-04-15 | Sharp Laboratories Of America, Inc. | Method of selective formation of compound semiconductor-on-silicon wafer with silicon nanowire buffer layer |
US20080149941A1 (en) * | 2006-05-30 | 2008-06-26 | Tingkai Li | Compound Semiconductor-On-Silicon Wafer with a Silicon Nanowire Buffer Layer |
US20080135886A1 (en) * | 2006-12-08 | 2008-06-12 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110070734A1 (en) * | 2009-09-18 | 2011-03-24 | Commissariat A L'energie Atomique Et Aux Ene. Alt. | Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate |
US8513125B2 (en) * | 2009-09-18 | 2013-08-20 | Commissariat a l'energie atomique et aux alternatives | Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate |
US9196715B2 (en) | 2012-12-28 | 2015-11-24 | Renesas Electronics Corporation | Field effect transistor with channel core modified to reduce leakage current and method of fabrication |
US20150179781A1 (en) * | 2013-12-20 | 2015-06-25 | International Business Machines Corporation | Strained semiconductor nanowire |
US9530876B2 (en) * | 2013-12-20 | 2016-12-27 | International Business Machines Corporation | Strained semiconductor nanowire |
US20170084745A1 (en) * | 2013-12-20 | 2017-03-23 | International Business Machines Corporation | Strained semiconductor nanowire |
US10056487B2 (en) * | 2013-12-20 | 2018-08-21 | International Business Machines Corporation | Strained semiconductor nanowire |
US20180254345A1 (en) * | 2013-12-20 | 2018-09-06 | International Business Machines Corporation | Strained semiconductor nanowire |
US10580894B2 (en) * | 2013-12-20 | 2020-03-03 | International Business Machines Corporation | Strained semiconductor nanowire |
FR3051970A1 (en) * | 2016-05-25 | 2017-12-01 | Commissariat Energie Atomique | IMPLEMENTING A SHAPED CHANNEL STRUCTURE OF A PLURALITY OF CONTAINING SEMICONDUCTOR BARS |
US10141424B2 (en) | 2016-05-25 | 2018-11-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of producing a channel structure formed from a plurality of strained semiconductor bars |
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US8232165B2 (en) | 2012-07-31 |
US20110275198A1 (en) | 2011-11-10 |
TW201110353A (en) | 2011-03-16 |
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