TWI662711B - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A preferred embodiment of the present invention is to disclose a semiconductor device including a substrate, a gold oxide semiconductor transistor disposed in the substrate, and a shallow trench isolation provided in the substrate and disposed around the gold oxide semiconductor transistor. The shallow trench isolation is made of a stress material.

Description

Semiconductor element and manufacturing method thereof

The present invention relates to a semiconductor element, and more particularly to a semiconductor element having a stress shallow trench isolation or a stress contact plug.

The conventional Metal Oxide Semiconductor (MOS) transistor usually includes a substrate, a source region, a drain region, a channel between the source region and the drain region, and a gate on the channel. Up. The gate system includes a gate dielectric layer on the channel, a gate conductive layer on the gate dielectric layer, and a side wall on the side wall of the gate conductive layer. Generally speaking, under a fixed electric field, the amount of driving current flowing through the channel of the MOS transistor is proportional to the carrier mobility in the channel. Therefore, how to improve the carrier mobility in the existing process equipment to increase the switching speed of the MOS transistor has become a major issue in the current semiconductor technology field.

An epitaxial growth process, such as a silicon germanium source / drain process, utilizes epitaxial formation of silicon germanium epitaxial layers in the semiconductor substrate adjacent to each sidewall after the sidewalls are formed. It uses the different characteristics of the lattice constant of silicon germanium layer and silicon to make silicon epitaxial structure strain in the silicon substrate to form strained silicon. Due to the lattice constant of the silicon germanium layer (lattice Constant) is larger than silicon, which changes the band structure of silicon, which results in increased carrier mobility. Therefore, the switching speed of the MOS transistor can be increased to improve the efficiency and speed of the integrated circuit.

In addition to the application of epitaxial layers, as semiconductor processes enter the deep sub-micron era, the use of high-stress films in semiconductor processes to increase the drive current of MOS transistors has gradually become a hot topic. At present, the use of high-stress films to increase the driving current of metal oxide semiconductor transistors can be roughly divided into two aspects: one is a polycrystalline silicon stress layer (poly stressor) applied before the formation of metal silicides such as silicon nickel oxide; the other is It is used in contact etch stop layer (CESL) after the formation of metal silicides such as silicon nickel oxide.

However, the use of epitaxial layers or high-stress films to improve the carrier flow in the channel region of metal oxide semiconductor transistors has reached a bottleneck. Therefore, how to improve the performance of the entire semiconductor device in addition to the processes widely used today? It is an important issue today.

Therefore, the present invention provides a semiconductor device, which mainly improves the carrier mobility in the channel region of a MOS transistor by using shallow trench isolation or contact plugs with stress.

A preferred embodiment of the present invention is to disclose a semiconductor device including a substrate, a gold oxide semiconductor transistor disposed in the substrate, and a shallow trench isolation provided in the substrate and disposed around the gold oxide semiconductor transistor. The shallow trench isolation is made of a stress material.

Another embodiment of the present invention is to disclose a semiconductor device including a substrate; a metal oxide semiconductor transistor is disposed in the substrate; a dielectric layer is disposed on the substrate and covers the metal oxide semiconductor transistor; and at least one stress interposer A plug is disposed in the dielectric layer and is disposed around the gold-oxide semiconductor transistor. The contact plug is made of a stress material.

Another embodiment of the present invention discloses a method for manufacturing a semiconductor device. First, a substrate is provided, and then a metal oxide semiconductor transistor is formed in the substrate, a dielectric layer is formed on the substrate to cover the metal oxide semiconductor transistor, and at least one contact hole is formed in the dielectric layer and provided in the substrate. Metal oxide semiconductors around. Finally, the contact hole is filled with a stress material.

10‧‧‧ substrate

12‧‧‧ groove

14‧‧‧ Stress Materials

16‧‧‧ Shallow trench isolation

18‧‧‧Gate structure

20‧‧‧Gate dielectric layer

22‧‧‧Gate electrode

24‧‧‧ Offset side wall

26‧‧‧Main side wall

28‧‧‧ lightly doped drain

30‧‧‧Source / Drain

32‧‧‧ silicided metal layer

34‧‧‧stress layer

36‧‧‧ Interlayer dielectric layer

38‧‧‧contact plug

60‧‧‧ substrate

68‧‧‧Gate structure

70‧‧‧Gate dielectric layer

72‧‧‧Gate electrode

74‧‧‧eccentric side wall

76‧‧‧ main wall

78‧‧‧ lightly doped drain

80‧‧‧Source / Drain

82‧‧‧ silicided metal layer

84‧‧‧stress layer

86‧‧‧Interlayer dielectric layer

88‧‧‧contact hole

90‧‧‧ Stress Plug

92‧‧‧active area

94‧‧‧ shallow trench isolation

96‧‧‧contact plug

FIG. 1 is a schematic diagram of manufacturing a semiconductor device according to a preferred embodiment of the present invention.

FIG. 2 is a top view of a semiconductor device according to another embodiment of the present invention.

Fig. 3 is a schematic sectional view of Fig. 2 taken along a tangent line AA '.

FIG. 4 is a top view of coexistence of a stress plug and a contact plug according to another embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of manufacturing a semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 10 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. Then a shallow trench isolation (STI) process is performed. For example, one or more lithography and etching processes are used to form a groove 12 in the substrate to separate or surround each active area. A stress material 14 is formed on the surface of the substrate 10 and fills the grooves 12, and then a planarization process is performed, for example, a chemical mechanical polishing process is used to remove part of the stress material 14 on the surface of the substrate 10 so that the stress material 14 in the grooves 12 and the substrate 10 The surface is flush, forming a shallow trench isolation 16 structure filled with stress material 14.

According to a preferred embodiment of the present invention, the stress material 14 filling the groove 12 can be selected from the group consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxycarbide, and fills the shallow trench isolation. The stress material 14 of 16 may be a single material layer, or a plurality of layers of the same or different material layers, which shall all fall within the scope of the present invention. The stress of silicon nitride is between -3.5GPa and 2.0GPa; the stress of boron nitride is between -1GPa and -2GPa. Since boron nitride is stable in air, vacuum or inert gas and is an insulator with excellent thermal conductivity, the present invention preferably uses boron nitride as a stress material for filling the groove 12.

Next, a gold-oxygen semiconductor transistor process is performed. For example, a gate structure 18 is formed on the substrate 10 on both sides of the shallow trench isolation 16 in FIG. 1. The gate structure 18 may include a gate dielectric layer 20 and a gate electrode 22. Then, an offset side wall 24 and a main side wall 26 are formed on the side walls of each gate structure 18, and a light conductive material of a corresponding conductivity type is formed in the substrate 10 on both sides of the offset side wall 24 and the main side wall 26, respectively. The hybrid drain 28 and the source / drain 30.

Subsequently, a selective epitaxial growth process may be performed to form an epitaxial layer (not shown) in the substrate 10 on both sides of the main sidewall 26. The material of the epitaxial layer may be different according to the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the epitaxial layer preferably includes silicon carbide; and if the prepared transistor is a PMOS transistor, the epitaxial layer preferably includes silicon germanium.

Then, a silicidation metal process can be performed. For example, a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, molybdenum, or a combination thereof is formed on the substrate 10 and covers the source / drain 30. And the epitaxial layer, and then use at least one rapid thermal annealing (RTP) process to react the metal layer with the source / drain 30 and the epitaxial layer to form a surface on the surface of the substrate 10 on both sides of the main sidewall 26 Siliconized metal layer 32. Finally, unreacted metals are removed.

Subsequently, a stress layer 34 may be formed and cover the surfaces of the substrate 10 and the gate structure 18. The material of the stress layer 34 may also be different depending on the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the stress layer is preferably a tensile stress layer; The transistor is a PMOS transistor, and the stress layer is preferably a compressive stress layer. The stress layer 34 can also be used as an etch stop layer when etching a contact hole.

An interlayer dielectric layer 36 may then be formed on the substrate 10 and cover the stress layer 34, and then a plurality of contact holes are formed in the interlayer dielectric layer 36 and the stress layer 34 and filled with a metal material such as tungsten to form a plurality of connections. The contact plug 38 of the source / drain 30. This completes the fabrication of a semiconductor device, which is one of the preferred embodiments of the present invention.

In this embodiment, the metal oxide semiconductor transistors on both sides of the shallow trench isolation are preferably metal oxide semiconductor transistors of the same conductivity type, such as NMOS transistors or PMOS transistors, so that The stressing material 14 can simultaneously provide NMOS transistors on both sides to give a tensile stress, or PMOS transistors on both sides to give a compressive stress at the same time.

Please refer to FIG. 2 and FIG. 3. FIG. 2 is another embodiment of the present invention. A top view of the semiconductor device and FIG. 3 is a schematic cross-sectional view of FIG. 2 along a tangent line AA '. As shown in the figure, a substrate 60 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate 60 has at least one active region 92, and a shallow trench isolation 94 for isolation is provided around the substrate 60. The shallow trench isolation 94 can also be a shallow trench isolation with stress as disclosed in the preferred embodiment of FIG. 1 of the present invention. structure.

Then, at least one gate structure 68 is formed on the substrate 60, wherein the gate structure 68 may include a gate dielectric layer 70 and a gate electrode 72. Then, an offset sidewall 74 and a main sidewall 76 are formed on the sidewalls of the gate structures 68, respectively, and a lightly doped drain electrode 78 and a substrate 60 on both sides of the offset sidewall 74 and the main sidewall 76 are formed. Source / Drain 80.

Then, a selective epitaxial growth process may be performed to form an epitaxial layer in the substrate 60 on both sides of the main sidewall 76 (not shown). The material of the epitaxial layer may be different according to the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the epitaxial layer preferably includes silicon carbide; and if the prepared transistor is a PMOS transistor, the epitaxial layer preferably includes silicon germanium.

Then, a metal silicide process can be performed. For example, a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, molybdenum, etc. is formed on the substrate 60 and covered with the source / drain 80 and the epitaxial. Layer, and then using at least one rapid thermal annealing (RTP) process to react the metal layer with the source / drain 80 and epitaxial layers to form a silicided metal layer on the surface of the substrate 60 on both sides of the main sidewall 76 82. Finally, unreacted metals are removed.

Subsequently, a stress layer 84 may be selectively formed to cover the substrate 60 and the gate structure 68. surface. The material of the stress layer 84 may also be different depending on the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the stress layer 84 is preferably a tensile stress layer; The prepared transistor is a PMOS transistor, and the stress layer 84 is preferably a compressive stress layer. The stress layer 34 can also be used as an etch stop layer when etching a contact hole.

Next, an interlayer dielectric layer 86 is formed on the substrate 60 and covers the stress layer 84, and then one or more etching processes are performed to form a plurality of contact holes 88 in the interlayer dielectric layer 86 and the stress layer 84. A contact material 88 is then filled in a stress material to form a plurality of stress plugs 90 with stress in the contact hole 88. It should be noted that, unlike a contact plug of a source / drain 80 in a general connection substrate, a stress plug 90 having a stress in this embodiment is mainly disposed around the entire MOS transistor and is not electrically connected to the source / drain. The pole 80 is mainly used to apply the required stress to the entire MOS transistor channel area, rather than to be used for electrical connection. Therefore, the setting position of the stress plug 90 of the present invention is preferably the extension direction of the parallel gate structure 68 , Which is the width of the parallel channel. Moreover, the metal oxide semiconductor transistors on both sides of the stress plug 90 are preferably metal oxide semiconductor transistors of the same conductivity type, such as the same NMOS transistor or PMOS transistor, so that the stress plug 90 can provide NMOS on both sides at the same time. The transistor is given a tensile stress, or the PMOS transistor on both sides is given a compressive stress at the same time.

According to a preferred embodiment of the present invention, the stress material filling the contact hole 88 may be selected from the group consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxycarbide. The stress of silicon nitride is between -3.5GPa and 2.0GPa; the stress of boron nitride is between -1GPa and -2GPa. Since boron nitride is stable in air, vacuum, or inert gas and is an insulator with excellent thermal conductivity, the present invention preferably uses boron nitride as a stress material for filling the contact hole 88. This completes one of the preferred embodiments of the present invention Fabrication of semiconductor devices.

Then, one or more etching processes are performed to form a plurality of contact holes (not shown) in the interlayer dielectric layer 86 and the stress layer 84. A conductive material is then used to fill the contact holes to form a plurality of contact plugs (not shown) with conductive capabilities in the contact holes. It is worth noting that the contact plugs for electrical connection can be located anywhere in the active area 92 for electrically connecting the source / drain 80, for example, provided in the gate structure 68 and the stress plug 90. In the meantime, either the stress plug 90 is located between the gate structure 68 and the contact plug, or the contact plug is disposed in the stress plug 90 and passes through the stress plug 90 to electrically connect the source / drain 80. Please refer to FIG. 4 at the same time, which is a top view of a coexistence of a stress plug and a contact plug. As shown in the figure, in the present invention, a plurality of contact plugs 96 can be disposed between the stress plug 90 and the gate structure 68 to obtain a situation where the stress plug 90 and the contact plug 96 coexist. It should be noted that the position of the contact plug 96 is not limited to that shown in the figure, and may be set at any position of the active area 92, for example, the position near the tail end of the stress plug 90. This embodiment also It is within the scope of the present invention.

In summary, the present invention is preferably filled with a stress material when a shallow trench isolation is formed in the substrate or a contact hole is formed in the interlayer dielectric layer, so as to produce a shallow trench isolation structure or a contact plug with stress. In addition to the epitaxial layer and the stress layer, the carrier mobility of the entire MOS transistor in the channel region is better improved. In addition, the above methods for forming shallow trench isolation or contact plugs with stress can be arbitrarily matched with various processes and applied to different components, such as memory components or high-voltage components. Secondly, the transistor disclosed in the present invention may include a transistor composed of a polysilicon gate or a metal gate, and the metal gate may be selected from a gate first process and a gate last according to a process requirement. ) Process, former Takasuke High-k first process and high-k last process.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

Claims (12)

A semiconductor device includes: a substrate; a transistor is disposed in the substrate, wherein the transistor includes a gate structure, a sidewall is disposed on a sidewall of the gate structure, and a source / drain is disposed on the substrate; In the substrate on both sides of the gate structure; a dielectric layer is disposed on the substrate and covers the transistor; at least one stress plug is disposed in the dielectric layer and disposed around the transistor, and the stress plug system is It is composed of a stress material; and at least one contact plug is disposed on the substrate and is connected to the source / drain, the stress plug surrounds the gate structure, and the contact plug is disposed on the gate structure And the stress plug, wherein the contact plug does not directly contact the stress plug. The semiconductor device according to item 1 of the scope of patent application, wherein the stress material is selected from the group consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxycarbide. According to the semiconductor device described in item 2 of the patent application scope, the stress of the silicon nitride is between -3.5 GPa and 2.0 GPa. The semiconductor device according to item 2 of the scope of the patent application, wherein the stress of the boron nitride is between -1 GPa and -2 GPa. The semiconductor device described in item 1 of the patent application scope further includes a stress layer disposed on the substrate and the gate structure surface. The semiconductor device according to item 1 of the patent application scope, wherein the gate structure is a metal gate or a polycrystalline silicon gate. A method for manufacturing a semiconductor device includes: providing a substrate; forming a transistor in the substrate, wherein the transistor includes a gate structure, a sidewall is disposed on a sidewall of the gate structure, and a source / A drain electrode is disposed in the substrate on both sides of the gate structure; a dielectric layer is formed on the substrate and covers the transistor; at least one contact hole is formed in the dielectric layer and disposed around the transistor; Filling the contact hole with a stress material; and forming at least one contact plug on the substrate and connecting the source / drain, the stress plug surrounds the gate structure, and the contact plug is disposed on the gate Between the gate structure and the stress plug, wherein the contact plug does not directly contact the stress plug. The method according to item 7 of the application, wherein the stress material is selected from the group consisting of silicon nitride, boron nitride, silicon oxide, silicon carbide, and silicon oxycarbide. The method according to item 8 of the scope of patent application, wherein the stress of the silicon nitride is between -3.5 GPa and 2.0 GPa. The method as described in item 8 of the scope of patent application, wherein the stress of the boron nitride is between -1 GPa and -2 GPa. The method according to item 7 of the scope of patent application, further comprising forming a stress layer on the substrate and the gate structure surface. The method according to item 7 of the scope of patent application, wherein the gate structure is a metal gate or a polycrystalline silicon gate.