US20090162991A1 - Process for assembling substrates with low-temperature heat treatments - Google Patents
Process for assembling substrates with low-temperature heat treatments Download PDFInfo
- Publication number
- US20090162991A1 US20090162991A1 US12/296,250 US29625007A US2009162991A1 US 20090162991 A1 US20090162991 A1 US 20090162991A1 US 29625007 A US29625007 A US 29625007A US 2009162991 A1 US2009162991 A1 US 2009162991A1
- Authority
- US
- United States
- Prior art keywords
- temperature
- process according
- levels
- substrate
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000010438 heat treatment Methods 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims abstract description 68
- 230000008569 process Effects 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 238000011282 treatment Methods 0.000 claims description 58
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 15
- 230000001186 cumulative effect Effects 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000002209 hydrophobic effect Effects 0.000 claims description 6
- 230000003014 reinforcing effect Effects 0.000 claims description 5
- 238000004320 controlled atmosphere Methods 0.000 claims description 4
- 230000001939 inductive effect Effects 0.000 claims description 3
- 230000010070 molecular adhesion Effects 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 38
- 208000010392 Bone Fractures Diseases 0.000 description 19
- 206010017076 Fracture Diseases 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 238000002360 preparation method Methods 0.000 description 12
- 238000000137 annealing Methods 0.000 description 10
- 239000010408 film Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000007872 degassing Methods 0.000 description 9
- 230000002787 reinforcement Effects 0.000 description 9
- 230000008859 change Effects 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 229910008045 Si-Si Inorganic materials 0.000 description 5
- 229910006411 Si—Si Inorganic materials 0.000 description 5
- 239000006227 byproduct Substances 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 238000003957 acoustic microscopy Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000002045 lasting effect Effects 0.000 description 4
- 210000002381 plasma Anatomy 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007596 consolidation process Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 230000005660 hydrophilic surface Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005305 interferometry Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- -1 Ammonium Peroxide Chemical class 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000005661 hydrophobic surface Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- JRKICGRDRMAZLK-UHFFFAOYSA-N peroxydisulfuric acid Chemical compound OS(=O)(=O)OOS(O)(=O)=O JRKICGRDRMAZLK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000678 plasma activation Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000011272 standard treatment Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
- C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
- C09J5/06—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1059—Splitting sheet lamina in plane intermediate of faces
Definitions
- the invention relates to techniques for assembling substrates.
- These are, for example, silicon plates, plain or covered with fine silicon oxide, with a thickness below 50 nm.
- Substrates 1 and 2 are assembled, one on the other, by the assembly faces 6 and 8 prepared before.
- a complementary treatment, of the bonding or fracture reinforcement type does not necessarily immediately follow a treatment according to the invention.
- a step of another intermediate treatment may take place in the meantime.
- an implantation is produced at a dose of 6 ⁇ 10 16 H + ions at 210 keV through a thermal oxide, which will enable the transfer of 1.56 ⁇ m of Si.
Abstract
The invention relates to a process for producing a bond between a first and a second substrate (2, 4), comprising:
-
- a) a step of preparing surfaces (6, 8) to be assembled,
- b) an assembly of these two surfaces, by direct molecular bonding,
- c) a heat treatment step involving at least maintaining the temperature within the range of 50° C. to 100° C. for at least one hour.
Description
- The invention relates to techniques for assembling substrates.
- In general, a bond between two substrates or surfaces can be obtained after a preparation of the surfaces giving them a hydrophilic or hydrophobic character.
- The use of heat treatments to reinforce the direct bonding can cause, for a certain number of bonded structures, the appearance of defects at the bonding interface. These defects are due to the degassing of by-products of the molecular bonding reaction: for example, water, hydrogen or hydrocarbon molecules.
- For a certain number of bonded structures, it is known that these defects can be resorbed by heat treatments performed at very high temperatures. These temperatures are, for example, between 900° C. and 1300° C. and are based on the preparation of surfaces before bonding. Unfortunately, for other bonded structures, this solution cannot be used.
- The limitation of the surface oxide thickness or the presence of various materials facilitates the appearance of defects at the bonding interface.
- In the case of thin films (with a thickness below around ten μm or several dozen nm), heat treatments, at temperatures below 1000° C., for example between 600° C. and 800° C., cause the formation of bonding defects in the form of blisters or zones without adherent film. These defects cannot be suppressed by higher-temperature heat treatments. For example, the bursting of bubbles is promoted by the fineness of the layers. These defects make the structures produced unusable. Currently, this phenomenon limits the production of oxide film structures, embedded at the bonding interface, that are fine (thickness below 50 nm) or ultra-fine or even Si layers directly bonded to Si plates.
- Similarly, for heterostructures (for example P-doped Si bonded to N-doped Si), heat treatments cause the formation of bonding defects under certain conditions. A high-temperature heat treatment (1000° C.) would cause interdiffusion of the doping agents.
- For certain heterostructures, if the damage is excessive in heat treatments within the temperature range below 800° C., this damage can no longer be repaired by a treatment between 1100° C. and 1300° C.
- When the heat treatments at higher temperatures cannot be used (incompatibility with the component production process in progress, for example), the bonding defects are then prohibitive.
- This therefore raises the problem of reducing or even eliminating, in the case of (direct) molecular bonding, the defects due to degassing at the bonding interface.
- The solutions currently used to overcome the formation of defects involve primarily the removal of water at the bonding interface by using, in particular, ultra high vacuum (UHV) bonding techniques. However, these techniques are not suitable for industrial use. There are also techniques that consist of forming channels at the bonding interface in order to evacuate the by-products of the molecular bonding reaction. Unfortunately, such techniques are destructive and present usage problems.
- A problem is therefore to find a treatment solution for reducing defects that enables industrial implementation while using the entire surface.
- According to the invention, a process for producing a bond between a first and a second substrate comprises:
- a) a step of preparing surfaces to be assembled,
- b) an assembly of these two surfaces, by direct molecular bonding,
- c) a heat treatment step involving at least maintaining the temperature of the surface or of the bonding interface within the range of 50° C. to 100° C. for at least one hour.
- Step c) also comprises, after the step of maintaining the temperature within the range [50 to 100° C.] for at least one hour, a step of maintaining the temperature within the range strictly above 100° C., and below 500° C. (i.e. within the range ]100° C. to 500° C.]) for at least one hour.
- The term “substrate” refers to a massive substrate or a substrate consisting of a stack of a plurality of layers of different types.
- This heat treatment according to the invention enables good preparation of the conditions for degassing the surfaces in contact by molecular adhesion.
- It makes it possible to minimise the defect density at the bonding interface. At lower temperatures, such a heat treatment makes it possible to more easily eliminate the by-products of the degassing of the interface, by diffusion at the bonding interface.
- The standard heat treatments, at higher temperatures, make it possible to increase the bonding energies of structures, and/or to create a fracture in a zone implanted by one (or more) species, for example gaseous, prior to the bonding. A treatment according to the invention can therefore be a complement to the standard heat treatments, at higher temperatures, which reinforce the bonding.
- Treatment steps at one or more temperature(s) above 100° C. can also have been performed prior to a treatment according to step c) of the invention.
- According to one embodiment, the invention involves the use of successive or cumulative heat treatments, by levels, for example starting at low temperatures, below 100° C. or 200° C.
- A level can comprise a ramp and the actual level temperature, the temperature at which the system is maintained for a certain period. All of these parameters (temperature ramp as a function of time, temperatures, duration of levels) may vary in relatively wide ranges.
- For example:
-
- a ramp can be as slow as 0.1° C./min,
- the successive temperatures can be spaced by 1° C. or by several ° C. only,
- the duration of a level can be as short as several tenths of a second and as long as several hours.
- Such a multi-level treatment makes it possible to progressively raise the temperature from the low range of 50° C. to 100° C., and further promotes the elimination of interface degassing by-products.
- The invention also relates to a process for producing a bond between a first and second substrate, comprising:
-
- an assembly of these two surfaces, by direct molecular bonding,
- a heat treatment step, by successive or cumulative levels.
- Such a treatment makes it possible to reduce the defect density at the bonding interface.
- Again, a level can comprise a ramp and the actual level temperature, the temperature at which the system is maintained for a certain period. All of these parameters (temperature ramp as a function of time, temperatures, duration of levels) may vary in relatively wide ranges.
- For example:
-
- a ramp can be as slow as 0.1° C./min,
- the successive temperatures can be spaced by 1° C. or by several ° C. only,
- the duration of a level can be as short as several tenths of a second and as long as several hours.
- Such a multi-level treatment makes it possible to progressively raise the temperature, for example from a low range such as the range of 50° C. to 100° C., and promotes the elimination of interface degassing by-products.
- One of the levels is, for example, around 100° C. for at least 3 or at least 4 or at least 5 hours.
- Regardless of the embodiment of the invention, at least one of the surfaces to be assembled may have previously been subjected to a preparation step for the purpose of assembly, for example a treatment step giving it a hydrophilic or hydrophobic character.
- In every case, the assembly can be performed by bonding, under a controlled atmosphere.
- The heat treatments according to the invention, by successive or cumulative levels, can be performed at progressive temperatures. Increases or levels at increasing temperatures can be performed, optionally with returns to a lower temperature, for example room temperature, between two levels.
- The invention therefore relates in particular to the use of specific heat treatments, short or long, but successive, at low temperatures, preferably below 200° C. or 100° C., as a complement to the standard heat treatments.
- For example, specific heat treatments are carried out, with each level lasting around two hours, successively at the following temperature levels: 50° C., then 100° C., then 125° C., then 150° C., and finally 200° C.
- According to another example, heat treatments according to the invention are carried out cumulatively. For example, a first level is performed for two hours at 100° C.; then, the temperature is returned to room temperature, then maintained at a second level, for two hours, at 150° C. It is then returned to room temperature, then again maintained at a third level, for two hours, but at 200° C. The temperature is then returned to room temperature.
- These successive heat treatments can in particular be adjusted by modifying the speeds (or ramps) of increase (or decrease) in temperature, until the desired temperature is reached.
- Advantageously, slow increase (or decrease) speeds will be used. For example, speeds below 5° C. per minute, or below 1° C. per minute, or below 0.1° C. per minute, will be chosen.
- These heat treatments, successive or cumulative, can be used in combination with effective surface preparations making it possible to obtain structures free of defects at the bonding interface of the hydrophilic or hydrophobic surfaces. These treatments can be a series of surface preparations such as plasmas, or rapid annealings, or bonding environments under various atmospheres and various pressures or temperature bondings.
- Heat treatments according to the invention can be followed, for example uninterruptedly, by one or more heat treatments, at one or more temperatures, for example, above the heat treatment temperatures according to the invention, in particular for the purpose of energy reinforcement (bonding).
- The invention also relates to a process for producing a thin film on a first substrate, comprising a process for producing a bond between the first substrate and a second substrate as described above, then a step of thinning the second substrate.
- The thinning step can be performed by chemical and/or mechanical thinning, or by fracture of the second substrate.
- In the latter case, the second substrate can be pre-implanted by one (or more) species, advantageously gaseous, in order to create a zone of weakness or fracture. This species is preferably implanted at a dose above the minimum dose enabling the fracture.
- For example, the species can be hydrogen.
- The implantation can be ionic.
- In the case of a crystalline plate, for example made of a semiconductor material such as silicon, the implantation can be performed at a dose above the minimum dose. The fracture can then be induced at a temperature below the temperature normally necessary to cause the fracture at the minimum dose.
- If the species implanted is hydrogen, the dose implanted will be, for example, greater than or equal to 6×1016H+·cm−2.
- Even for “standard” doses (and therefore not only in the case of an overdose), a heat treatment according to the invention has a benefit, in particular for the “Smart Cut®” process, by limiting the number of defects.
- A process according to the invention is particularly suitable for the assembly of two silicon substrates, or two silicon dioxide substrates (or substrates covered with silicon dioxide), or a substrate made of (or covered by) silicon dioxide and a silicon substrate.
- A process according to the invention makes it possible in particular to obtain a thin (thickness below 50 nm) or even ultra-fine oxide film, embedded at the bonding interface.
- A process according to the invention also makes it possible to obtain very thin layers of Si (thickness below 150 nm) or of SiO2 (thickness below 50 nm) directly bonded on Si or SiO2 plates.
- In addition, the bonding surfaces can be diverse, for example chosen from semiconductors (Si, SiGe, Ge, III-V, etc.) conductors (Ni, Co, W, Ti, Ta, Pt, Pd, etc.) or insulators (SiO2, Si3N4, AlN, Al2O3, diamond, etc.) alone or in combination.
- This invention can be better understood on reading the description of examples of embodiments provided purely for indicative and non-limiting purposes, in reference to the appended drawings, in which:
-
FIG. 1 shows a pair of substrates to be assembled, -
FIGS. 2 to 4 and 12 show various changes in temperature as a function of time for various heat treatment processes according to this invention, -
FIGS. 5A and 5B show two acoustic microscopy images, one (FIG. 5A ) after a standard heat treatment (400° C./2 h), and the other (FIG. 5B ) after an additional slow-ramp heat treatment, and followed by the samestandard heat treatment 400° C./2 h, -
FIG. 6 shows the change in the defect density at the interface, due to the degassing of the species, as a function of the temperature T of a bonding consolidation heat treatment, with a heat treatment according to the invention (squares), and without a heat treatment according to the invention (circles), -
FIG. 7 shows an acoustic microscopy image of the interface of an Si—Si bond after a heat treatment according to the invention and a consolidation heat treatment at 700° C. for 2 h, without defects, -
FIG. 8 is an example of defectiveness observed in interferometry for structures having thin films treated only by a “standard” process, -
FIG. 9 is an example of defectiveness observed in interferometry for a structure having a thin film obtained by a process according to the invention, -
FIG. 10 shows a thin film on a substrate, -
FIGS. 11A and 11B show steps of a process for obtaining a structure as shown inFIG. 10 . - Identical, similar or equivalent parts of the various figures described below use the same numeric references for the sake of consistency between figures.
- The various parts shown in the figures are not necessarily shown according to a uniform scale, in order to make the figures easier to read.
- An example of an embodiment of the invention will be given in relation to
FIG. 1 , in which references 2 and 4 designate two substrates to be assembled, withrespective assembly surfaces - These are, for example, silicon plates, plain or covered with fine silicon oxide, with a thickness below 50 nm.
-
Surfaces substrates - For example, a preparation of a surface with a hydrophilic character comprises a chemical treatment of the Sulfo-Peroxide Mixture (SPM) and/or Ammonium Peroxide Mixture (APM) type and/or a treatment enabling for example a cleaning, such as a (water and/or hydrocarbons) degassing heat treatment, and/or an activation of the surfaces by UV, and/or Ozone and/or by plasma, for example RIE or microwave, or ICP, etc., under various atmospheres.
- The bonding can take place under various pressures, with or without thermalisation (the latter can be performed, for example, at between 200° C. and 300° C.).
- According to another example, a preparation of a surface with a hydrophobic character comprises a surface deoxidation treatment; in the case of a silicon surface, it can be a HF liquid chemical attack.
-
Substrates - To improve the removal of species at the bonding interface, it is also possible to perform the bonding under a controlled atmosphere (vacuum or N2 atmosphere), with or without thermalisation.
- Once the bonding has been performed, the structure is subjected, according to the invention, to a heat treatment involving maintaining the temperature in the range of 50° C. to 100° C. for at least one hour. In this range, the temperature can change or be constant. For example, it can be equal to 100° C. for one hour, or change, starting at 50° C., according to a thermal ramp of 50° C./h, thus passing 100° C. after one hour (
solid line 10 ofFIG. 12 ). - The time passed between 50° C. and 100° C. can also be above 1 hour, or 1.5 h, or 2 h, or 2.5 h or 3 h.
- The temperature is also maintained for at least one hour, at a temperature strictly above 100° C., and, for example, below 500° C.
- An example of a treatment according to the invention involves at least maintaining the temperature in the range of 50° C. to 200° C. or between 100° C. and 200° C. or between 200° C. and 250° C., for at least one hour or two hours or three hours in order to satisfy the conditions set forth above (temperature between 50° C. and 100° C. for at least one hour and, for at least one hour, temperature strictly above 100° C., for example below 500° C.).
- The system can previously have been subjected to treatments at higher or lower temperatures. Consequently, it is also possible to have a preliminary treatment at over 100° C. or 150° C. or 200° C., then a return of the temperature to between 50° C. and 100° C., and a treatment according to the invention in particular while maintaining the temperature in this range of 50° C. to 100° C. for at least one hour or two hours or three hours.
- Such a treatment according to the invention can be followed by another treatment, for example at a higher temperature, in order to reinforce the bonding or fracturing of one of the substrates as explained below.
- The treatment according to the invention led, aside from the maintenance of the temperature at between 50° C. and 100° C. for at least one hour, to bringing the system to higher temperatures, for example 200° C., and/or 300° C. and/or other temperatures (this is the case for treatments with levels as explained below) A treatment according to the invention can also be followed by a treatment at least at a temperature below the temperature of one of the levels.
- A complementary treatment, of the bonding or fracture reinforcement type, does not necessarily immediately follow a treatment according to the invention. A step of another intermediate treatment may take place in the meantime.
-
FIG. 12 shows an example of a treatment comprising: -
- a preliminary treatment phase at a temperature T3, for example to perform the bonding,
- then a treatment according to the invention (phase I), comprising:
- a) maintaining the system for at least one hour at between 50° C. and 100° C. (in fact, the system is maintained in this temperature range for a period longer than one hour, since it is maintained at 100° C. also during phase I′),
- b) and, in the particular case represented, a treatment step at a temperature T4, above 100° C.,
-
- finally, a complementary treatment (phase II), for example to reinforce the bonding, at a temperature equal to, above (T6) or below (T5) one of the temperatures of the treatment according to the invention.
- The treatment phase I according to the invention can comprise a ramp, shown with the dotted line in
FIG. 12 , during which the system slowly goes from 50° C. to 100° C. over at least one hour. The system is also maintained for at least one hour, at a temperature strictly above 100° C., as shown in the zone located in zone I, but beyond I′ (between times t3 and t4), as well as zone II. - An example of a heat treatment according to the invention is in fact a treatment by levels.
- Below, we will describe the levels of a heat treatment according to the invention as:
-
- successive, when one follows another, without returning to room temperature or to a lower temperature (for example shown diagrammatically in
FIGS. 2 and 3 ), - cumulative, when one follows another with a return, between two levels, to a lower temperature, for example room temperature (for example the treatment shown diagrammatically in
FIG. 4 ).
- successive, when one follows another, without returning to room temperature or to a lower temperature (for example shown diagrammatically in
- The heat treatment according to the invention can consist of a combination of successive and/or cumulative levels.
- For example, for Si—Si bondings, the low temperature of the levels of a heat treatment according to the invention will be below 200° C. and more advantageously below 150° C., for example, equal to or close to 50° C., then 100° C., then 125° C. or 145° C.
- The steps or levels of a heat treatment according to the invention are long when their durations are more than one hour or two hours or, advantageously, more than five hours.
- The duration of a level or a step of a heat treatment according to the invention includes both the duration of the increase from room temperature, the duration of maintaining the temperature of the level and the duration of decreases from the treatment level temperature to, for example, room temperature.
- A heat treatment according to the invention, by levels, can involve, as in the treatments described above, maintaining the temperature within the range of 50° C. to 100° C. for at least one hour. In this range, the temperature can change, or be constant. For example, it can be equal to 100° C. for one hour or change, starting at 50° C., according to a thermal ramp of 50° C./h, thus passing 100° C. after one hour (dotted
line 10 ofFIG. 12 ). - The time passed between 50° C. and 100° C. can also be above 1 hour, or 1.5 h, or 2 h, or 2.5 h or 3 h.
- Another treatment according to the invention, by levels, involves maintaining the temperature within the range of 50° C. to 200° C. or between 100° C. and 200° C., or between 200° C. and 250° C., for at least one hour or two hours or three hours. We will also seek to satisfy the conditions set forth above (temperature for at least one hour between 50° C. and 100° C. and, for at least one hour, strictly above 100° C., and for example below 500° C.).
- According to an example, a treatment of the two
substrates FIG. 1 comprises successive temperature levels at low temperatures. - For example, this treatment is performed for a period of around 5 hours for each level, and successively at increasing temperatures. A first level can be T1=50° C., a second T2=100° C., a third T3=150° C., and a fourth T4=200° C. The change in temperature as a function of time is shown in
FIG. 2 . It is then possible to progress further by levels of 100° C., until reaching a temperature, T, of a bonding reinforcement heat treatment. - According to an alternative, it is possible to implement a very slow temperature increase ramp making it possible to very gradually raise the temperature to the levels T1, then T2, then T3, then T4, for example with a slope of 1° C./min, or even advantageously 0.1° C./min. Advantageously, the temperature is maintained at successive heat levels T1, T2, T3 and T4, starting at low temperatures, for example at 100° C., with each level being maintained, for example, for 10 hours. Such a treatment is shown in
FIG. 3 . - One or more heat treatments can thus be defined, all enabling a total heat treatment according to the invention.
- A heat treatment according to the invention, by successive or cumulative levels, can be followed by a heat treatment reinforcing the assembly of the two substrates, for example at a temperature above that of the heat treatment levels according to the invention.
- Another treatment according to the invention is shown in
FIG. 4 : levels are set at temperatures T1, T2, T3 and T4, with returns, between each level, to a lower temperature TO, for example room temperature, for example at 20° C. - Thus, a cumulative heat treatment can have the following form, starting at room temperature (for example: 20° C.):
-
- a first level for a period of 2 hours at 50° C., followed by a return to a lower temperature (for example: room temperature),
- then a second level for 2 hours at 100° C., followed by a return to a lower temperature (for example: room temperature),
- then a third level for 2 hours at 150° C., followed by a return to a lower temperature (for example: room temperature),
- then a fourth level for 2 hours at 200° C., followed by a return to a lower temperature (for example: room temperature),
- then a standard bonding reinforcement heat treatment at a temperature T, for example 400° C., for 2 hours.
- Another example of a heat treatment according to the invention is a ramp bringing the temperature of the system progressively from room temperature to a final temperature, which ramp is such that a period of at least one hour is passed in the range of 50° C. to 100° C. The duration passed between these two temperatures can also be above 1 h, or 1.5 h, or 2 h, or 2.5 h or 3 h. The treatment is then completed by the treatment steps according to the invention (maintaining the temperature in the range strictly above 100° C. and below or equal to 500° C. for at least one hour).
- Heat treatments according to the invention have been carried out with a wet chemical hydrophilic surface preparation (SPM and APM).
- The effects of the various heat treatments according to the invention can be compared in terms of defect density.
- 1) in the first case (table 1), the following were compared:
-
- a heat treatment according to the invention, of the type of
FIG. 3 , with a slow ramp of 1° C./min, starting at room temperature, with levels each lasting 10 h, at 100° C., then at 200° C., then at 300° C., and finally at 400° C., - and a bonding reinforcement heat treatment, referred to as the “standard” treatment, which is quasi-isothermal at 400° C.
- a heat treatment according to the invention, of the type of
- Table I shows a defect density at the bonding interface that is clearly lower than in the case of the treatment according to the invention.
- The images shown in
FIGS. 5A and 5B are images of the bonding interface obtained by acoustic microscopy. InFIG. 5A , it is an image after the “standard” heat treatment alone. InFIG. 5B , it is an image after the heat treatment according to the invention and after the same standard heat treatment as that ofFIG. 5A .FIG. 5B shows, with respect toFIG. 5A , an improvement, with the treatment according to the invention, of the defectiveness, by a factor greater than 8 (FIGS. 5A and 5B relate to the results of table I). - The repair of bonding defects, at high temperature (for example above 1100° C.) is therefore largely facilitated in a preliminary application of a treatment according to the invention.
- When such a high-temperature repair treatment is not possible, for example due to the presence of components in one of the substrates, the treatment according to the invention makes it possible to considerably limit the defect density in the final assembly.
-
TABLE I Defect density at the bonding interface Standard heat treatment alone 88% (400° C./2 h). Additional heat treatment with 10.60% slow ramp before the standard treatment at 400° C. - 2) in the second case, the following were compared:
-
- a heat treatment according to the invention, consisting of long successive levels lasting 5 hours at 50° C./min, followed by 5 hours at 100° C., followed by 5 hours at 150° C., followed by a heat treatment at temperature T (bonding reinforcement temperature),
- and a standard quasi-isothermal heat treatment at temperature T=200° C. (or 300° C. or 400° C.) for around 2 hours, for reinforcement of the interface.
- An improvement in the defectiveness by at least a factor of 4 is noted owing to the heat treatment according to the invention, and for each standard interface reinforcement heat treatment temperature (at 200° C. or 300° C. or 400° C.).
-
FIG. 6 shows the change in defect density as a function of the annealing temperature, with a treatment according to the invention (squares) and without a treatment according to the invention (circles). The example is that of an Si—Si bond, with a wet chemical preparation (SPM, APM). - Other application examples can be given.
- By optimising the preliminary surface preparations, for example by preparing
surfaces FIG. 7 ) under the following conditions: -
- a heat treatment according to the invention is first performed, which treatment comprises a slow ramp of 1° C./min, starting at room temperature, then having levels of a duration of 10 hours each at 100° C., then at 200° C., then at 300° C., and so on by levels of 100° C. until reaching the final temperature of 700° C.,
- a “standard” bonding reinforcement heat treatment, in the range of 600 to 700° C.
-
FIG. 7 shows an acoustic microscopy image of this Si—Si bonding interface, after heat treatment by levels according to the invention, followed by a consolidation treatment at 700° C. for 2 hours. This interface is free of defects. - By chemically preparing the surfaces, for example with an attack by HF in solution, so that they become hydrophobic, it was possible, with a heat treatment according to the invention, to obtain defect-free bonding interfaces at up to 500° C. and more. The heat treatment according to the invention is a slow ramp, of 0.15° C./min, starting at room temperature, combined with levels, each lasting 10 hours, at 100° C., then at 200° C., then at 300° C., and so on by levels of 100° C. until reaching the final temperature of 500° C.
- Various other applications of a process according to the invention can be mentioned.
- The use of additional heat treatments according to the invention makes it possible to produce stacked structures by molecular bonding with minimal or even no bonding defects. Among the various applications, it is then possible to produce thin films (for example below 100 μm or 1 μm or 0.1 μm) is possible.
- For example, the initial structure is obtained by bonding two
thick plates 2 and 4 (FIG. 1 ), followed by a heat treatment by levels according to the invention, and optionally a reinforcing heat treatment. It is then possible to use mechanical thinning technology (lapping, grinding, etc.) and/or a chemical thinning technique (chemical attack, lift off, etc.) and/or other techniques alone or in combination. The structure ofFIG. 10 is then obtained with asubstrate 2 and athin film 40. - According to another example, at least one of the two
thick plates FIG. 11A ). Then a heat treatment by levels according to the invention is carried out, and optionally a reinforcing heat treatment. - It is then possible to use the technology known as “Smart Cut” (registered trademark): after the bonding of the two thick plates (
FIG. 11B ), a separation is caused, for example in a heat treatment, at the level of theweakness zone 21, and thethin film 40, which remains adhered to theplate 2, is detached (FIG. 10 ). - The process according to the invention can also advantageously be used in the following fields of application:
- 1. Productions of stacked structures by molecular adhesion, including thin or ultra-thin layers, with a thickness for example below 2 μm or even 0.1 μm, for example; the production of silicon-on-insulator (SOI) structures with films of silicon and fine buried oxides (BOX). In particular, the thickness of the oxide at the bonding interface is typically below 50 nm. Since the oxide does not have the ability to absorb the degassing products of the bonding, the heat treatments according to the invention enable these products to disappear without damaging the bonding interface.
- 2. The production of certain heterostructures, obtained by direct bonding, which poorly withstand, or do not withstand, high-temperature repair heat treatments, for example:
-
- two
substrates - two substrates or
plates plates - two substrates or
plates
- two
- The process according to the invention can also advantageously be used in the following application.
- According to the usual processes described as “standard”, the production of thin-layer films can be complex when the thickness of the films becomes very low, on the order of several nanometres, or between 1 nm and 10 μm. Indeed, production defects appear on or in the films produced (holes, folds, bubbles/blisters, etc.) in the production of films or in annealings that make it possible to stabilise the new structures produced.
FIG. 8 is an example of defectiveness observed with a “Magic Mirror” apparatus of Hologenix, for structures of thin films treated by the “standard” process. Several hundred defects make the structure industrially “unusable”. - This problem concerns in particular the production of SOI (silicon-on-insulator: structure Si/SiO2/Si) materials; it also concerns the production of SIS (semiconductor-insulator-support) materials comprising a thin semiconductor layer (from several nanometres, for example 5 nm, to several μm, for example 5 μm or 10 μm, in thickness), which conducts the electric current according to certain electrical conditions (voltage/current, for example), on an insulator. The latter makes it possible to insulate the thin layer semiconductor from the underlying support (SiO2, Si3N4, diamond, etc.). The support makes it possible to maintain the preceding two thin layers stacked in order to create the final industrialised structure.
- According to the invention, the defect problems inherent to the so-called “standard” process are solved.
- In the case of a heat treatment inducing a fracture, the temperature at which the plates are put in the detachment oven is carefully chosen: advantageously, the plates will be introduced at a temperature above room temperature, for example 50° C. or 80° C. or 100° C., or between 50° C. and 80° C. or between 80° C. and 100° C., for example at the temperature of the first temperature level in a heat treatment by levels, for example at 50° C. or 80° C. or 100° C. The use of a relatively long time, on the order of at least 3 hours or at least 4 hours or at least 5 hours, at one or more relatively low temperature(s), for example on the order of 50° C. or 80° C. or 100° C. or 150° C., or for example between 50° C. and 80° C. or between 80° C. and 100° C. or between 100° C. and 150° C. makes it possible to reduce the number of defects for plates subjected to plasma activation before bonding.
- The substrate fracture can be obtained using the Smart Cut™ or substrate fracture technology, described, for example, in “Silicon Wafer Bonding Technology”, edited by S S Iyer and A J Auberton-Hervé, INSPEC, Institute of Electrical Engineers, London, 2002,
Chapter 3, p. 35 and following, by B. Aspar and A. J. Auberton-Hervé, in the following way: - It is possible first to implant a dose much higher than that generally required—at least 20% higher (for example a dose of 8×1016H+·cm2 for the hydrogen implanted in the silicon oxide, whereas the usual process uses only 5×1016H+·cm2). It is then possible to use the annealing previously described, with a placement in a low-temperature oven (below 100° C.). Slow and long temperature increase ramps (0.25° C./min for example) enable the thin film structure of the “Smart Cut” type to be released at a lower temperature than the usual process (for example in the case of hydrogen in silicon at a temperature below 400° C., for example 300° C., whereas the fracture normally occurs at 500° C.).
- This process (overdose of the species implanted at depth for transfer to a lower temperature for slow and long annealing) makes it possible to produce a structure several nanometres in thickness with a minimum number of defects.
- The fracture is therefore obtained at a lower temperature than for the standard process. It is therefore possible to produce, for example at temperatures below, or on the order of, 400° C., for example 300° C., a fracture in structures that are not compatible with the usual fracture temperatures (around 500° C.). This is the case in particular for a processed structure (i.e. comprising, in or on the thin film to be transferred or the receiving substrate, all or some electronic components (CMOS, for example) or others (MEMS, MOEMS, etc.) or comprising metal interconnections, etc.).
- Thus, in
FIG. 9 , it is noted that a thin layer obtained by a process according to the invention contains fewer than 10 defects, whereas more than one thousand defects are observed in the “standard” process (FIG. 8 ). - Consequently, according to an embodiment of the invention, favourable ion implantation conditions are selected: overdosed implanted species, for example at a dose above the minimum dose enabling a fracture (above 6×1016 H+·cm2 or 7×1016 H+·cm2, for example, for hydrogen). These conditions make it possible, at low temperature, to produce structures having very low film thicknesses (of several nanometres) with a considerably reduced defect density, from several hundred or several thousand to just several units, or even without defects.
- It is thus possible to produce thin film structures (semiconductor, for example) on a thin film (insulator or not), all on a support.
- An example of the use of an annealing process is as follows. As explained above, it is sought to overdose an ion or atom implantation in order to produce a fracture at a lower temperature than in the known processes.
- According to this example, a silicon oxide plate is implanted with H+ ions at a dose of 8×1016 H+·cm−2 and an energy of 50 keV.
- It is bonded to another Si plate, by an oxide layer, and a Si/SiO2/Si structure is thus obtained, for example with an oxide thickness of 12 nm.
- Then, the following annealing cycle is carried out:
-
- the temperature is initially 100° C., then the isotherm 100° C. is maintained for 10 hours,
- a ramp at 0.25° C./min is then produced, until reaching the
isotherm 200° C., maintained for 10 hours, - a ramp at 0.25° C./min is then produced, until reaching the
isotherm 300° C., maintained for 10 hours, - again a ramp at 0.25° C./min is produced until reaching the isotherm at 400° C., maintained for 10 hours; the fracturing of the substrate is produced during this step,
- again a ramp at 0.25° C./min is produced, and an output temperature of 200° C. is reached.
- According to an alternative, an implantation is performed with a dose of 8×1016 H+·cm2 at 76 keV, which will enable the transfer of 700 nanometres of Si.
- The annealing cycle is as follows:
-
- the temperature is initially at 100° C., then the isotherm is maintained at 100° C. for 10 hours.
- a ramp at 0.25° C./min is then produced, until reaching the
isotherm 200° C., maintained for 10 hours, - a ramp at 0.25° C./min is then produced, until reaching the
isotherm 300° C., maintained for 15 hours; the fracturing of the substrate is performed before this step, - again a ramp at 0.25° C./min is produced, and an output temperature of 200° C. is reached.
- According to yet another example, an implantation is produced at a dose of 6×1016 H+ ions at 210 keV through a thermal oxide, which will enable the transfer of 1.56 μm of Si.
- Two plates or
substrates zone 21 ofFIG. 11A , which will subsequently enable a thin layer to be separated from the remainder of the substrate. - The two plates are then cleaned by RCA chemistry and their surface is activated by plasma.
- The plates are then placed under vacuum (10−3 mbar) with a temperature increase to 300° C. (heat ramp of 20° C./min). They are maintained at this temperature for 10 minutes.
- The bonding is then induced at this temperature for a period of two hours, then the system is returned to room temperature.
- A treatment according to the invention is then applied, with a temperature ramp of 1° C./min, starting at room temperature, up to 100° C. The following is then performed:
-
- the temperature is maintained at 100° C. for 10 hours,
- then a level at 200° C. for 10 hours,
- then a level at 300° C. for 10 hours,
- then a level at 400° C. for 10 hours.
- The fracture treatment is then induced during the final level at 400° C., resulting in a transfer of a silicon film of 1.56 μm.
- In this example, the system is subjected, before the heat treatment according to the invention, to a treatment at a temperature above 100° C.
- The invention also relates to the case of “standard” implantation doses (and therefore not only overdose cases as in the examples already provided); a heat treatment according to the invention then has an interest in the implementation of the “Smart Cut®” process, by limiting the number of defects. An example will be provided, which shows the detachment annealing of bonded plates, for a transfer according to the “Smart Cut®” process:
-
- the silicon donor plate has an oxide layer on the order of 50 nm of thickness,
- it is activated by an O2 plasma treatment at 535 W for 45 s,
- it is implanted with hydrogen at a dose on the order of 1016 H+ ions/cm2 and an energy on the order of 30 keV,
- the detachment annealing is performed by exposing the plates to a temperature of around 100° C., for at least 5 hours, then an increase in temperature by 0.5° C./min to 200° C., then maintaining the temperature at 200° C. for 2 hours, and, finally, increasing the temperature by 0.5° C./min to 500° C.
- The transfer of the layer to the receiving plate is thus performed with fewer than 5 pinhole-type defects.
- In all of the experiments and examples described, no additional mechanical force is applied to create the fracture of the implanted substrate.
Claims (31)
1-30. (canceled)
31. Process for producing a bond between a first and a second substrate, comprising:
a) a step of preparing surfaces to be assembled,
b) an assembly of these two surfaces, by direct molecular bonding,
c) a heat treatment step involving at least maintaining the temperature within the range of 50° C. to 100° C. for at least one hour, then maintaining the temperature in the range strictly above 100° C. and below or equal to 500° C. for at least one hour.
32. Process according to claim 31 , said step c) comprising a passage through successive and/or cumulative temperature levels.
33. Process according to claim 32 , said temperature levels being successive, without a return to room temperature.
34. Process according to claim 32 , said temperature levels being cumulative, with, between two successive temperature levels, a return to a temperature below the temperatures of two levels.
35. Process according to claim 34 , the lower temperatures between two successive levels being all identical.
36. Process according to claim 35 , the lower temperatures between two successive levels being all equal to room temperature.
37. Process according to claim 32 , the temperature levels being produced at temperatures increasing over time.
38. Process according to claim 32 , at least one of the temperature levels comprising a rate of temperature increase below 5° C. per minute.
39. Process according to claim 31 , said step of preparing the surfaces being a hydrophilic or hydrophobic treatment step.
40. Process according to claim 31 , said assembly being produced by bonding, under a controlled atmosphere.
41. Process according to claim 31 , at least one of the two substrates being a semiconductor material.
42. Process according to claim 31 , at least one of the two substrates being made of silicon.
43. Process according to claim 31 , the two substrates being made of silicon.
44. Process according to claim 31 , the two substrates at least having a silicon dioxide surface.
45. Process according to claim 31 , one of the two substrates having at least a surface of silicon dioxide and the other is silicon.
46. Process according to claim 31 , the two substrates being made of materials with different heat expansion coefficients.
47. Process according to claim 31 , at least one of the two substrates comprising at least one component.
48. Process according to claim 31 , the bonding being performed under a controlled atmosphere, under controlled pressure, with or without thermalisation.
49. Process according to claim 31 , the temperature at the end of step c) being a heat treatment temperature for reinforcing molecular bonding and/or inducing a fracture in a substrate.
50. Process according to claim 31 , also comprising a step:
d) of reinforcing the bonding by molecular adhesion and/or inducing a fracture in a substrate.
51. Process according to claim 50 , step d) being performed by a heat treatment at a temperature above the temperatures of step c).
52. Process according to claim 50 , wherein, during step c), the system is brought, for example by one or more temperature levels, to a temperature above 100° C., with step d) being performed at least at a temperature above, or equal, or below this temperature above 100° C.
53. Process for producing a thin film on a first substrate, comprising a process for producing a bond between the first substrate and a second substrate according to claim 31 , then a step of thinning the second substrate.
54. Process according to claim 53 , the thinning step being performed by chemical and/or mechanical thinning.
55. Process according to claim 54 , the thinning step being performed by fracturing the second substrate.
56. Process according to claim 54 , the second substrate being pre-implanted by one or more atomic or ionic species in order to create in it a weakness zone.
57. Process according to claim 56 , the atomic or ionic species being implanted at a dose above the minimum dose enabling the fracture, which is performed at a temperature below or equal to the temperature normally associated with the minimum dose.
58. Process according to claim 57 , the fracture being performed at one or more temperature(s) between 50° C. and 150° C., for at least 3 hours.
59. Process according to claim 57 , the ionic species, H+, being implanted in silicon at a dose above 6×1016 H+·cm−2.
60. Process according to claim 53 , the thin film obtained having a thickness below 1 μm or 100 nm or 50 nm.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0651290 | 2006-04-10 | ||
FR0651290A FR2899594A1 (en) | 2006-04-10 | 2006-04-10 | METHOD FOR ASSEMBLING SUBSTRATES WITH THERMAL TREATMENTS AT LOW TEMPERATURES |
PCT/EP2007/053428 WO2007116038A1 (en) | 2006-04-10 | 2007-04-06 | Method of assembling substrates with heat treatments at low temperatures |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2007/053428 A-371-Of-International WO2007116038A1 (en) | 2006-04-10 | 2007-04-06 | Method of assembling substrates with heat treatments at low temperatures |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/273,982 Continuation US8530331B2 (en) | 2006-04-10 | 2011-10-14 | Process for assembling substrates with low-temperature heat treatments |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090162991A1 true US20090162991A1 (en) | 2009-06-25 |
Family
ID=37544382
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/296,250 Abandoned US20090162991A1 (en) | 2006-04-10 | 2007-04-06 | Process for assembling substrates with low-temperature heat treatments |
US13/273,982 Active US8530331B2 (en) | 2006-04-10 | 2011-10-14 | Process for assembling substrates with low-temperature heat treatments |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/273,982 Active US8530331B2 (en) | 2006-04-10 | 2011-10-14 | Process for assembling substrates with low-temperature heat treatments |
Country Status (7)
Country | Link |
---|---|
US (2) | US20090162991A1 (en) |
EP (1) | EP2004768B1 (en) |
JP (1) | JP5230601B2 (en) |
AT (1) | ATE440922T1 (en) |
DE (1) | DE602007002178D1 (en) |
FR (1) | FR2899594A1 (en) |
WO (1) | WO2007116038A1 (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080277266A1 (en) * | 2007-05-11 | 2008-11-13 | Layman Frederick P | Shape of cone and air input annulus |
WO2011081834A1 (en) * | 2009-12-15 | 2011-07-07 | Sdcmaterials Llc | Pinning and affixing nano-active material |
US8470112B1 (en) | 2009-12-15 | 2013-06-25 | SDCmaterials, Inc. | Workflow for novel composite materials |
US8481449B1 (en) | 2007-10-15 | 2013-07-09 | SDCmaterials, Inc. | Method and system for forming plug and play oxide catalysts |
US8545652B1 (en) | 2009-12-15 | 2013-10-01 | SDCmaterials, Inc. | Impact resistant material |
US8557727B2 (en) | 2009-12-15 | 2013-10-15 | SDCmaterials, Inc. | Method of forming a catalyst with inhibited mobility of nano-active material |
US8669202B2 (en) | 2011-02-23 | 2014-03-11 | SDCmaterials, Inc. | Wet chemical and plasma methods of forming stable PtPd catalysts |
US8668803B1 (en) | 2009-12-15 | 2014-03-11 | SDCmaterials, Inc. | Sandwich of impact resistant material |
US8679433B2 (en) | 2011-08-19 | 2014-03-25 | SDCmaterials, Inc. | Coated substrates for use in catalysis and catalytic converters and methods of coating substrates with washcoat compositions |
US8803025B2 (en) | 2009-12-15 | 2014-08-12 | SDCmaterials, Inc. | Non-plugging D.C. plasma gun |
US9126191B2 (en) | 2009-12-15 | 2015-09-08 | SDCmaterials, Inc. | Advanced catalysts for automotive applications |
US9149797B2 (en) | 2009-12-15 | 2015-10-06 | SDCmaterials, Inc. | Catalyst production method and system |
US9156025B2 (en) | 2012-11-21 | 2015-10-13 | SDCmaterials, Inc. | Three-way catalytic converter using nanoparticles |
US9427732B2 (en) | 2013-10-22 | 2016-08-30 | SDCmaterials, Inc. | Catalyst design for heavy-duty diesel combustion engines |
US9437474B2 (en) | 2012-09-05 | 2016-09-06 | Commissariat à l'énergie atomique et aux énergies alternative | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions |
US9511352B2 (en) | 2012-11-21 | 2016-12-06 | SDCmaterials, Inc. | Three-way catalytic converter using nanoparticles |
US9517448B2 (en) | 2013-10-22 | 2016-12-13 | SDCmaterials, Inc. | Compositions of lean NOx trap (LNT) systems and methods of making and using same |
US9586179B2 (en) | 2013-07-25 | 2017-03-07 | SDCmaterials, Inc. | Washcoats and coated substrates for catalytic converters and methods of making and using same |
US9687811B2 (en) | 2014-03-21 | 2017-06-27 | SDCmaterials, Inc. | Compositions for passive NOx adsorption (PNA) systems and methods of making and using same |
US11081463B2 (en) | 2018-11-09 | 2021-08-03 | Commissariat à l'énergie atomique et aux énergies alternatives | Bonding method with electron-stimulated desorption |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010045156A (en) * | 2008-08-12 | 2010-02-25 | Toshiba Corp | Method of producing semiconductor device |
FR2938119B1 (en) * | 2008-10-30 | 2011-04-22 | Soitec Silicon On Insulator | METHOD FOR DETACHING LOW TEMPERATURE SEMICONDUCTOR LAYERS |
FR2942910B1 (en) * | 2009-03-06 | 2011-09-30 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A HETEROSTRUCTURE TO REDUCE THE STRAIN STRENGTH OF THE DONOR SUBSTRATE |
FR2990054B1 (en) * | 2012-04-27 | 2014-05-02 | Commissariat Energie Atomique | METHOD FOR BONDING IN A GAS ATMOSPHERE HAVING A NEGATIVE JOULE-THOMSON COEFFICIENT |
JP2014103291A (en) * | 2012-11-21 | 2014-06-05 | Renesas Electronics Corp | Semiconductor device manufacturing method |
FR3040108B1 (en) | 2015-08-12 | 2017-08-11 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE WITH TEMPORARY DIRECT COLLAGE OPERATING A POROUS LAYER |
FR3085957B1 (en) | 2018-09-14 | 2021-01-29 | Commissariat Energie Atomique | TEMPORARY BONDING PROCESS WITH THERMOPLASTIC ADHESIVE INCORPORATING A RIGID CROWN |
Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US514235A (en) * | 1894-02-06 | Patrick molyneux | ||
US5152857A (en) * | 1990-03-29 | 1992-10-06 | Shin-Etsu Handotai Co., Ltd. | Method for preparing a substrate for semiconductor devices |
US5395788A (en) * | 1991-03-15 | 1995-03-07 | Shin Etsu Handotai Co., Ltd. | Method of producing semiconductor substrate |
US5539245A (en) * | 1991-11-18 | 1996-07-23 | Mitsubishi Materials Silicon Corporation | Semiconductor substrate having a gettering layer |
US5834812A (en) * | 1994-11-30 | 1998-11-10 | Sibond, L.L.C. | Edge stripped BESOI wafer |
US5869386A (en) * | 1995-09-28 | 1999-02-09 | Nec Corporation | Method of fabricating a composite silicon-on-insulator substrate |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
US6010579A (en) * | 1997-05-12 | 2000-01-04 | Silicon Genesis Corporation | Reusable substrate for thin film separation |
US6303468B1 (en) * | 1997-08-12 | 2001-10-16 | Commissariat A L'energie Atomique | Method for making a thin film of solid material |
US6309950B1 (en) * | 1998-08-04 | 2001-10-30 | Micron Technology, Inc. | Methods for making silicon-on-insulator structures |
US6326279B1 (en) * | 1999-03-26 | 2001-12-04 | Canon Kabushiki Kaisha | Process for producing semiconductor article |
US6387815B2 (en) * | 1993-06-07 | 2002-05-14 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor substrate |
US20020068419A1 (en) * | 1997-12-26 | 2002-06-06 | Kiyofumi Sakaguchi | Semiconductor article and method of manufacturing the same |
US20020187595A1 (en) * | 1999-08-04 | 2002-12-12 | Silicon Evolution, Inc. | Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality |
US20030008478A1 (en) * | 2000-03-29 | 2003-01-09 | Takao Abe | Production method for silicon wafer and soi wafer, and soi wafer |
US20030092244A1 (en) * | 2000-04-28 | 2003-05-15 | Hiroyuki Oi | Method and apparatus for producing bonded dielectric separation wafer |
US20030094674A1 (en) * | 2000-10-25 | 2003-05-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor wafer |
US20030113984A1 (en) * | 2000-05-16 | 2003-06-19 | Mamoru Okada | Semiconductor wafer thinning method, and thin semiconductor wafer |
US6624047B1 (en) * | 1999-02-02 | 2003-09-23 | Canon Kabushiki Kaisha | Substrate and method of manufacturing the same |
US6664169B1 (en) * | 1999-06-08 | 2003-12-16 | Canon Kabushiki Kaisha | Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus |
US20040206444A1 (en) * | 2003-03-14 | 2004-10-21 | Fabrice Letertre | Methods for forming an assembly for transfer of a useful layer |
US20040212557A1 (en) * | 2001-01-18 | 2004-10-28 | Bon-Cheol Koo | Plasma display panel and driving method thereof |
US6815309B2 (en) * | 2001-12-21 | 2004-11-09 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Support-integrated donor wafers for repeated thin donor layer separation |
US6828216B2 (en) * | 2002-05-02 | 2004-12-07 | S.O.I. Tec Silicon On Insulator Technologies S.A. | Process for detaching layers of material |
US6838358B2 (en) * | 2003-05-26 | 2005-01-04 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Method of manufacturing a wafer |
US6841848B2 (en) * | 2003-06-06 | 2005-01-11 | Analog Devices, Inc. | Composite semiconductor wafer and a method for forming the composite semiconductor wafer |
US6936523B2 (en) * | 2002-12-10 | 2005-08-30 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Two-stage annealing method for manufacturing semiconductor substrates |
US20060055003A1 (en) * | 2004-05-19 | 2006-03-16 | Sumco Corporation | Bonded SOI substrate, and method for manufacturing the same |
US7205211B2 (en) * | 2002-03-28 | 2007-04-17 | Commisariat L'energie Atomique | Method for handling semiconductor layers in such a way as to thin same |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62179110A (en) | 1986-02-03 | 1987-08-06 | Toshiba Corp | Manufacture of direct bonding type semiconductor substrate |
JP2535957B2 (en) | 1987-09-29 | 1996-09-18 | ソニー株式会社 | Semiconductor substrate |
JPH02194519A (en) | 1989-01-23 | 1990-08-01 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor substrate and manufacture thereof |
JPH0389519A (en) | 1989-08-31 | 1991-04-15 | Sony Corp | Manufacture of semiconductor substrate |
JP2662495B2 (en) | 1993-06-28 | 1997-10-15 | 住友シチックス株式会社 | Method for manufacturing bonded semiconductor substrate |
JP2856030B2 (en) | 1993-06-29 | 1999-02-10 | 信越半導体株式会社 | Method for manufacturing bonded wafer |
JPH0917984A (en) | 1995-06-29 | 1997-01-17 | Sumitomo Sitix Corp | Bonded soi substrate manufacturing method |
JP3352896B2 (en) | 1997-01-17 | 2002-12-03 | 信越半導体株式会社 | Manufacturing method of bonded substrate |
JP3352902B2 (en) | 1997-02-21 | 2002-12-03 | 信越半導体株式会社 | Manufacturing method of bonded substrate |
JP3132425B2 (en) | 1997-06-20 | 2001-02-05 | 日本電気株式会社 | Communication time reduction method for satellite intranet service |
SG78332A1 (en) | 1998-02-04 | 2001-02-20 | Canon Kk | Semiconductor substrate and method of manufacturing the same |
JP3635200B2 (en) | 1998-06-04 | 2005-04-06 | 信越半導体株式会社 | Manufacturing method of SOI wafer |
JPH11354761A (en) | 1998-06-09 | 1999-12-24 | Sumitomo Metal Ind Ltd | Soi substrate and its production |
JP3515917B2 (en) | 1998-12-01 | 2004-04-05 | シャープ株式会社 | Method for manufacturing semiconductor device |
DE19943101C2 (en) | 1999-09-09 | 2002-06-20 | Wacker Siltronic Halbleitermat | Method of manufacturing a bonded semiconductor wafer |
JP3632531B2 (en) | 1999-11-17 | 2005-03-23 | 株式会社デンソー | Manufacturing method of semiconductor substrate |
KR100789205B1 (en) | 2000-03-29 | 2007-12-31 | 신에쯔 한도타이 가부시키가이샤 | Production method for silicon wafer and soi wafer, and soi wafer |
JP2003078115A (en) | 2001-08-30 | 2003-03-14 | Shin Etsu Handotai Co Ltd | Soi wafer laser mark printing method and soi wafer |
WO2003098695A1 (en) | 2002-05-20 | 2003-11-27 | Sumitomo Mitsubishi Silicon Corporation | Laminated substrate, method of manufacturing the substrate, and wafer outer periphery pressing jigs used for the method |
EP1523773B1 (en) | 2002-07-17 | 2010-09-22 | S.O.I.Tec Silicon on Insulator Technologies | Method of smoothing the outline of a useful layer of material transferred onto a support substrate |
FR2852445B1 (en) | 2003-03-14 | 2005-05-20 | Soitec Silicon On Insulator | PROCESS FOR PRODUCING SUBSTRATES OR COMPONENTS ON SUBSTRATES WITH USEFUL LAYER TRANSFER FOR MICROELECTRONICS, OPTOELECTRONICS OR OPTICS |
US7713838B2 (en) * | 2003-09-08 | 2010-05-11 | Sumco Corporation | SOI wafer and its manufacturing method |
FR2860842B1 (en) * | 2003-10-14 | 2007-11-02 | Tracit Technologies | PROCESS FOR PREPARING AND ASSEMBLING SUBSTRATES |
JP4918229B2 (en) | 2005-05-31 | 2012-04-18 | 信越半導体株式会社 | Manufacturing method of bonded wafer |
FR2935535B1 (en) | 2008-09-02 | 2010-12-10 | S O I Tec Silicon On Insulator Tech | METHOD FOR JOINT DETOURING. |
-
2006
- 2006-04-10 FR FR0651290A patent/FR2899594A1/en not_active Withdrawn
-
2007
- 2007-04-06 WO PCT/EP2007/053428 patent/WO2007116038A1/en active Application Filing
- 2007-04-06 AT AT07727896T patent/ATE440922T1/en not_active IP Right Cessation
- 2007-04-06 US US12/296,250 patent/US20090162991A1/en not_active Abandoned
- 2007-04-06 JP JP2009504710A patent/JP5230601B2/en active Active
- 2007-04-06 DE DE602007002178T patent/DE602007002178D1/en active Active
- 2007-04-06 EP EP07727896A patent/EP2004768B1/en active Active
-
2011
- 2011-10-14 US US13/273,982 patent/US8530331B2/en active Active
Patent Citations (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US514235A (en) * | 1894-02-06 | Patrick molyneux | ||
US5152857A (en) * | 1990-03-29 | 1992-10-06 | Shin-Etsu Handotai Co., Ltd. | Method for preparing a substrate for semiconductor devices |
US5395788A (en) * | 1991-03-15 | 1995-03-07 | Shin Etsu Handotai Co., Ltd. | Method of producing semiconductor substrate |
US5539245A (en) * | 1991-11-18 | 1996-07-23 | Mitsubishi Materials Silicon Corporation | Semiconductor substrate having a gettering layer |
US6387815B2 (en) * | 1993-06-07 | 2002-05-14 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor substrate |
US5834812A (en) * | 1994-11-30 | 1998-11-10 | Sibond, L.L.C. | Edge stripped BESOI wafer |
US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
US5869386A (en) * | 1995-09-28 | 1999-02-09 | Nec Corporation | Method of fabricating a composite silicon-on-insulator substrate |
US6632724B2 (en) * | 1997-05-12 | 2003-10-14 | Silicon Genesis Corporation | Controlled cleaving process |
US6010579A (en) * | 1997-05-12 | 2000-01-04 | Silicon Genesis Corporation | Reusable substrate for thin film separation |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US6303468B1 (en) * | 1997-08-12 | 2001-10-16 | Commissariat A L'energie Atomique | Method for making a thin film of solid material |
US20020068419A1 (en) * | 1997-12-26 | 2002-06-06 | Kiyofumi Sakaguchi | Semiconductor article and method of manufacturing the same |
US6309950B1 (en) * | 1998-08-04 | 2001-10-30 | Micron Technology, Inc. | Methods for making silicon-on-insulator structures |
US6624047B1 (en) * | 1999-02-02 | 2003-09-23 | Canon Kabushiki Kaisha | Substrate and method of manufacturing the same |
US6326279B1 (en) * | 1999-03-26 | 2001-12-04 | Canon Kabushiki Kaisha | Process for producing semiconductor article |
US20040055894A1 (en) * | 1999-06-08 | 2004-03-25 | Canon Kabushiki Kaisha | Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus |
US6664169B1 (en) * | 1999-06-08 | 2003-12-16 | Canon Kabushiki Kaisha | Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus |
US20020187595A1 (en) * | 1999-08-04 | 2002-12-12 | Silicon Evolution, Inc. | Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality |
US20030008478A1 (en) * | 2000-03-29 | 2003-01-09 | Takao Abe | Production method for silicon wafer and soi wafer, and soi wafer |
US20030092244A1 (en) * | 2000-04-28 | 2003-05-15 | Hiroyuki Oi | Method and apparatus for producing bonded dielectric separation wafer |
US20030113984A1 (en) * | 2000-05-16 | 2003-06-19 | Mamoru Okada | Semiconductor wafer thinning method, and thin semiconductor wafer |
US20030094674A1 (en) * | 2000-10-25 | 2003-05-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor wafer |
US20040212557A1 (en) * | 2001-01-18 | 2004-10-28 | Bon-Cheol Koo | Plasma display panel and driving method thereof |
US6815309B2 (en) * | 2001-12-21 | 2004-11-09 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Support-integrated donor wafers for repeated thin donor layer separation |
US7205211B2 (en) * | 2002-03-28 | 2007-04-17 | Commisariat L'energie Atomique | Method for handling semiconductor layers in such a way as to thin same |
US6828216B2 (en) * | 2002-05-02 | 2004-12-07 | S.O.I. Tec Silicon On Insulator Technologies S.A. | Process for detaching layers of material |
US6936523B2 (en) * | 2002-12-10 | 2005-08-30 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Two-stage annealing method for manufacturing semiconductor substrates |
US20040206444A1 (en) * | 2003-03-14 | 2004-10-21 | Fabrice Letertre | Methods for forming an assembly for transfer of a useful layer |
US6838358B2 (en) * | 2003-05-26 | 2005-01-04 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Method of manufacturing a wafer |
US6841848B2 (en) * | 2003-06-06 | 2005-01-11 | Analog Devices, Inc. | Composite semiconductor wafer and a method for forming the composite semiconductor wafer |
US20060055003A1 (en) * | 2004-05-19 | 2006-03-16 | Sumco Corporation | Bonded SOI substrate, and method for manufacturing the same |
Cited By (70)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9023754B2 (en) | 2005-04-19 | 2015-05-05 | SDCmaterials, Inc. | Nano-skeletal catalyst |
US9180423B2 (en) | 2005-04-19 | 2015-11-10 | SDCmaterials, Inc. | Highly turbulent quench chamber |
US9132404B2 (en) | 2005-04-19 | 2015-09-15 | SDCmaterials, Inc. | Gas delivery system with constant overpressure relative to ambient to system with varying vacuum suction |
US9599405B2 (en) | 2005-04-19 | 2017-03-21 | SDCmaterials, Inc. | Highly turbulent quench chamber |
US9216398B2 (en) | 2005-04-19 | 2015-12-22 | SDCmaterials, Inc. | Method and apparatus for making uniform and ultrasmall nanoparticles |
US9719727B2 (en) | 2005-04-19 | 2017-08-01 | SDCmaterials, Inc. | Fluid recirculation system for use in vapor phase particle production system |
US8524631B2 (en) | 2007-05-11 | 2013-09-03 | SDCmaterials, Inc. | Nano-skeletal catalyst |
US8906316B2 (en) | 2007-05-11 | 2014-12-09 | SDCmaterials, Inc. | Fluid recirculation system for use in vapor phase particle production system |
US20080277266A1 (en) * | 2007-05-11 | 2008-11-13 | Layman Frederick P | Shape of cone and air input annulus |
US8956574B2 (en) | 2007-05-11 | 2015-02-17 | SDCmaterials, Inc. | Gas delivery system with constant overpressure relative to ambient to system with varying vacuum suction |
US8142619B2 (en) | 2007-05-11 | 2012-03-27 | Sdc Materials Inc. | Shape of cone and air input annulus |
US8051724B1 (en) | 2007-05-11 | 2011-11-08 | SDCmaterials, Inc. | Long cool-down tube with air input joints |
US8574408B2 (en) | 2007-05-11 | 2013-11-05 | SDCmaterials, Inc. | Fluid recirculation system for use in vapor phase particle production system |
US8604398B1 (en) | 2007-05-11 | 2013-12-10 | SDCmaterials, Inc. | Microwave purification process |
US8893651B1 (en) | 2007-05-11 | 2014-11-25 | SDCmaterials, Inc. | Plasma-arc vaporization chamber with wide bore |
US8663571B2 (en) | 2007-05-11 | 2014-03-04 | SDCmaterials, Inc. | Method and apparatus for making uniform and ultrasmall nanoparticles |
US8507402B1 (en) | 2007-10-15 | 2013-08-13 | SDCmaterials, Inc. | Method and system for forming plug and play metal catalysts |
US9186663B2 (en) | 2007-10-15 | 2015-11-17 | SDCmaterials, Inc. | Method and system for forming plug and play metal compound catalysts |
US9737878B2 (en) | 2007-10-15 | 2017-08-22 | SDCmaterials, Inc. | Method and system for forming plug and play metal catalysts |
US8759248B2 (en) | 2007-10-15 | 2014-06-24 | SDCmaterials, Inc. | Method and system for forming plug and play metal catalysts |
US9597662B2 (en) | 2007-10-15 | 2017-03-21 | SDCmaterials, Inc. | Method and system for forming plug and play metal compound catalysts |
US8575059B1 (en) | 2007-10-15 | 2013-11-05 | SDCmaterials, Inc. | Method and system for forming plug and play metal compound catalysts |
US9089840B2 (en) | 2007-10-15 | 2015-07-28 | SDCmaterials, Inc. | Method and system for forming plug and play oxide catalysts |
US8507401B1 (en) | 2007-10-15 | 2013-08-13 | SDCmaterials, Inc. | Method and system for forming plug and play metal catalysts |
US8481449B1 (en) | 2007-10-15 | 2013-07-09 | SDCmaterials, Inc. | Method and system for forming plug and play oxide catalysts |
US9302260B2 (en) | 2007-10-15 | 2016-04-05 | SDCmaterials, Inc. | Method and system for forming plug and play metal catalysts |
US9592492B2 (en) | 2007-10-15 | 2017-03-14 | SDCmaterials, Inc. | Method and system for forming plug and play oxide catalysts |
US8865611B2 (en) | 2009-12-15 | 2014-10-21 | SDCmaterials, Inc. | Method of forming a catalyst with inhibited mobility of nano-active material |
US8906498B1 (en) | 2009-12-15 | 2014-12-09 | SDCmaterials, Inc. | Sandwich of impact resistant material |
US8932514B1 (en) | 2009-12-15 | 2015-01-13 | SDCmaterials, Inc. | Fracture toughness of glass |
US8877357B1 (en) | 2009-12-15 | 2014-11-04 | SDCmaterials, Inc. | Impact resistant material |
US9522388B2 (en) | 2009-12-15 | 2016-12-20 | SDCmaterials, Inc. | Pinning and affixing nano-active material |
US8992820B1 (en) | 2009-12-15 | 2015-03-31 | SDCmaterials, Inc. | Fracture toughness of ceramics |
US8859035B1 (en) | 2009-12-15 | 2014-10-14 | SDCmaterials, Inc. | Powder treatment for enhanced flowability |
US9039916B1 (en) | 2009-12-15 | 2015-05-26 | SDCmaterials, Inc. | In situ oxide removal, dispersal and drying for copper copper-oxide |
US9090475B1 (en) | 2009-12-15 | 2015-07-28 | SDCmaterials, Inc. | In situ oxide removal, dispersal and drying for silicon SiO2 |
US8828328B1 (en) | 2009-12-15 | 2014-09-09 | SDCmaterails, Inc. | Methods and apparatuses for nano-materials powder treatment and preservation |
US9119309B1 (en) | 2009-12-15 | 2015-08-25 | SDCmaterials, Inc. | In situ oxide removal, dispersal and drying |
US9126191B2 (en) | 2009-12-15 | 2015-09-08 | SDCmaterials, Inc. | Advanced catalysts for automotive applications |
US8821786B1 (en) | 2009-12-15 | 2014-09-02 | SDCmaterials, Inc. | Method of forming oxide dispersion strengthened alloys |
US9149797B2 (en) | 2009-12-15 | 2015-10-06 | SDCmaterials, Inc. | Catalyst production method and system |
US8803025B2 (en) | 2009-12-15 | 2014-08-12 | SDCmaterials, Inc. | Non-plugging D.C. plasma gun |
US8668803B1 (en) | 2009-12-15 | 2014-03-11 | SDCmaterials, Inc. | Sandwich of impact resistant material |
US8652992B2 (en) | 2009-12-15 | 2014-02-18 | SDCmaterials, Inc. | Pinning and affixing nano-active material |
US8557727B2 (en) | 2009-12-15 | 2013-10-15 | SDCmaterials, Inc. | Method of forming a catalyst with inhibited mobility of nano-active material |
US8545652B1 (en) | 2009-12-15 | 2013-10-01 | SDCmaterials, Inc. | Impact resistant material |
US8470112B1 (en) | 2009-12-15 | 2013-06-25 | SDCmaterials, Inc. | Workflow for novel composite materials |
US9308524B2 (en) | 2009-12-15 | 2016-04-12 | SDCmaterials, Inc. | Advanced catalysts for automotive applications |
US9332636B2 (en) | 2009-12-15 | 2016-05-03 | SDCmaterials, Inc. | Sandwich of impact resistant material |
WO2011081834A1 (en) * | 2009-12-15 | 2011-07-07 | Sdcmaterials Llc | Pinning and affixing nano-active material |
US9533289B2 (en) | 2009-12-15 | 2017-01-03 | SDCmaterials, Inc. | Advanced catalysts for automotive applications |
US8669202B2 (en) | 2011-02-23 | 2014-03-11 | SDCmaterials, Inc. | Wet chemical and plasma methods of forming stable PtPd catalysts |
US9216406B2 (en) | 2011-02-23 | 2015-12-22 | SDCmaterials, Inc. | Wet chemical and plasma methods of forming stable PtPd catalysts |
US9433938B2 (en) | 2011-02-23 | 2016-09-06 | SDCmaterials, Inc. | Wet chemical and plasma methods of forming stable PTPD catalysts |
US8679433B2 (en) | 2011-08-19 | 2014-03-25 | SDCmaterials, Inc. | Coated substrates for use in catalysis and catalytic converters and methods of coating substrates with washcoat compositions |
US8969237B2 (en) | 2011-08-19 | 2015-03-03 | SDCmaterials, Inc. | Coated substrates for use in catalysis and catalytic converters and methods of coating substrates with washcoat compositions |
US9498751B2 (en) | 2011-08-19 | 2016-11-22 | SDCmaterials, Inc. | Coated substrates for use in catalysis and catalytic converters and methods of coating substrates with washcoat compositions |
US9437474B2 (en) | 2012-09-05 | 2016-09-06 | Commissariat à l'énergie atomique et aux énergies alternative | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions |
US9533299B2 (en) | 2012-11-21 | 2017-01-03 | SDCmaterials, Inc. | Three-way catalytic converter using nanoparticles |
US9156025B2 (en) | 2012-11-21 | 2015-10-13 | SDCmaterials, Inc. | Three-way catalytic converter using nanoparticles |
US9511352B2 (en) | 2012-11-21 | 2016-12-06 | SDCmaterials, Inc. | Three-way catalytic converter using nanoparticles |
US9586179B2 (en) | 2013-07-25 | 2017-03-07 | SDCmaterials, Inc. | Washcoats and coated substrates for catalytic converters and methods of making and using same |
US9566568B2 (en) | 2013-10-22 | 2017-02-14 | SDCmaterials, Inc. | Catalyst design for heavy-duty diesel combustion engines |
US9427732B2 (en) | 2013-10-22 | 2016-08-30 | SDCmaterials, Inc. | Catalyst design for heavy-duty diesel combustion engines |
US9517448B2 (en) | 2013-10-22 | 2016-12-13 | SDCmaterials, Inc. | Compositions of lean NOx trap (LNT) systems and methods of making and using same |
US9950316B2 (en) | 2013-10-22 | 2018-04-24 | Umicore Ag & Co. Kg | Catalyst design for heavy-duty diesel combustion engines |
US9687811B2 (en) | 2014-03-21 | 2017-06-27 | SDCmaterials, Inc. | Compositions for passive NOx adsorption (PNA) systems and methods of making and using same |
US10086356B2 (en) | 2014-03-21 | 2018-10-02 | Umicore Ag & Co. Kg | Compositions for passive NOx adsorption (PNA) systems and methods of making and using same |
US10413880B2 (en) | 2014-03-21 | 2019-09-17 | Umicore Ag & Co. Kg | Compositions for passive NOx adsorption (PNA) systems and methods of making and using same |
US11081463B2 (en) | 2018-11-09 | 2021-08-03 | Commissariat à l'énergie atomique et aux énergies alternatives | Bonding method with electron-stimulated desorption |
Also Published As
Publication number | Publication date |
---|---|
JP2009533854A (en) | 2009-09-17 |
EP2004768A1 (en) | 2008-12-24 |
ATE440922T1 (en) | 2009-09-15 |
US8530331B2 (en) | 2013-09-10 |
EP2004768B1 (en) | 2009-08-26 |
DE602007002178D1 (en) | 2009-10-08 |
US20120088352A1 (en) | 2012-04-12 |
WO2007116038A1 (en) | 2007-10-18 |
FR2899594A1 (en) | 2007-10-12 |
JP5230601B2 (en) | 2013-07-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8530331B2 (en) | Process for assembling substrates with low-temperature heat treatments | |
JP4927080B2 (en) | Method for reducing the roughness of thick insulating layers | |
KR100614120B1 (en) | A method of fabricating an soi wafer and soi wafer fabricated by the method | |
US7253080B1 (en) | Silicon-on-insulator semiconductor wafer | |
US20070029043A1 (en) | Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process | |
US8236667B2 (en) | Silicon on insulator (SOI) wafer and process for producing same | |
KR101469282B1 (en) | Method for manufacturing soi wafer | |
KR101335713B1 (en) | Process for producing laminated substrate and laminated substrate | |
TWI492275B (en) | The method of manufacturing the bonded substrate | |
WO2007094233A1 (en) | Soi substrate and method for manufacturing soi substrate | |
US9496130B2 (en) | Reclaiming processing method for delaminated wafer | |
CN110828298A (en) | Single crystal thin film composite substrate and method for manufacturing same | |
WO2007072632A1 (en) | Soi substrate and method for manufacturing soi substrate | |
WO2005124865A1 (en) | Method for manufacturing bonded wafer | |
WO2007127074A2 (en) | Semiconductor on glass insulator made using improved thinning process | |
JP2006210898A (en) | Process for producing soi wafer, and soi wafer | |
JP2006210899A (en) | Process for producing soi wafer, and soi wafer | |
CN104488066B (en) | Joint method in the atmosphere of the gas with negative joule thomson coefficient | |
EP2186126A1 (en) | Semiconductor wafer re-use in an exfoliation process using heat treatment | |
EP1981064B1 (en) | Process for producing a soi wafer | |
WO2005024925A1 (en) | Method for producing soi wafer | |
JPH1187668A (en) | Manufacture of soi board | |
KR20090042139A (en) | Method for manufacturing semiconductor substrate | |
CN102224568A (en) | Method for manufacturing bonded wafer | |
JP2009253184A (en) | Manufacturing method for laminated substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE,FRANCE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BENEYTON, REMI;MORICEAU, HUBERT;FOURNEL, FRANK;AND OTHERS;REEL/FRAME:021931/0820 Effective date: 20081103 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |