US20090057684A1 - Nitride semiconductor device and method for producing nitride semiconductor device - Google Patents
Nitride semiconductor device and method for producing nitride semiconductor device Download PDFInfo
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- US20090057684A1 US20090057684A1 US12/222,462 US22246208A US2009057684A1 US 20090057684 A1 US20090057684 A1 US 20090057684A1 US 22246208 A US22246208 A US 22246208A US 2009057684 A1 US2009057684 A1 US 2009057684A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 211
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 156
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 193
- 238000002161 passivation Methods 0.000 claims description 9
- 229910002704 AlGaN Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 177
- 229910002601 GaN Inorganic materials 0.000 description 66
- 230000005533 two-dimensional electron gas Effects 0.000 description 33
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- 239000010931 gold Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 239000010936 titanium Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229910001020 Au alloy Inorganic materials 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
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- 229910001252 Pd alloy Inorganic materials 0.000 description 3
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- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
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- 239000000463 material Substances 0.000 description 3
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
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- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 239000000395 magnesium oxide Substances 0.000 description 2
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- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- 235000012245 magnesium oxide Nutrition 0.000 description 2
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- HYXGAEYDKFCVMU-UHFFFAOYSA-N scandium(III) oxide Inorganic materials O=[Sc]O[Sc]=O HYXGAEYDKFCVMU-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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- H01L29/2003—Nitride compounds
Definitions
- the present invention relates to a nitride semiconductor device employing a group III nitride semiconductor and a method for producing the same.
- CAVET Current Aperture Vertical Electron Transistor
- HEMT High Electron Mobility Transistor
- FIG. 3 is a schematic sectional view of a conventional CAVET.
- This CAVET includes a GaN (gallium nitride) substrate 101 , a high-resistance layer (an n ⁇ -type GaN (gallium nitride) layer 102 in FIG. 3 ) having a low n-type impurity concentration stacked on a principal growth plane 101 a of the GaN substrate 101 and a layer (an AlGaN (aluminum gallium nitride) layer 103 in FIG. 3 , for example), having a different lattice constant from the n ⁇ -type GaN layer 102 , laminated on the n ⁇ -type GaN layer 102 , for example.
- the n ⁇ -type GaN layer 102 and the AlGaN layer 103 are successively epitaxially grown in order on the GaN substrate 101 with the interface parallel to the principal growth plane 101 a.
- a p-type GaN layer 104 provided with an opening 105 on a position opposed to the AlGaN layer 103 is formed on an intermediate portion of the n ⁇ -type GaN layer 102 in the thickness direction.
- two-dimensional electron gas 106 parallel to the principal growth plane 101 a is formed in the n ⁇ -type GaN layer 102 due to the heterojunction therebetween.
- a gate electrode 107 is formed on the AlGaN layer 103 , to form a Schottky junction with the AlGaN layer 103 .
- Two source electrode 108 are formed to be opposed to each other through the gate electrode 107 , to form ohmic contact with the AlGaN layer 103 or the n ⁇ -type GaN layer 102 .
- a drain electrode 109 is formed on the back surface of the GaN substrate 101 opposite to the principal growth plane lola, to form ohmic contact with the GaN substrate 101 .
- the source electrodes 108 and the drain electrode 109 are opposed to each other through the GaN substrate 101 , to constitute the CAVET having a vertical structure.
- the electrons reaching the opening 105 flow in the n ⁇ -type GaN layer 102 through the opening 105 to flow into the GaN substrate 101 , due to the potential of the drain electrode 109 .
- the electrons flowing into the GaN substrate 101 reach the drain electrode 109 through the GaN substrate 101 .
- the current flows from the drain electrode 109 to the source electrode 108 , to allow the source and the drain to conduct.
- the aforementioned CAVET capable of implementing the vertical structure has the so-called normally-on characteristic with a gate threshold voltage V th of ⁇ 16 V. In order to turn off the CAVET, therefore, a negative voltage must be applied to the gate electrode 107 , to pinch off the two-dimensional electron gas 106 .
- the principal growth plane 101 a of the GaN substrate 101 may be defined by a nonpolar plane (an a-plane or an m-plane).
- a nonpolar plane an a-plane or an m-plane.
- An object of the present invention is to provide a normally-off type nitride semiconductor device and a method for producing the same.
- a nitride semiconductor device of the present invention includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a ⁇ c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III nitride semiconductor layers; and a drain electrode formed on a back surface of the semiconductor base layer opposite to the principal plane.
- the insulating layer having the aperture partially exposing the principal plane (nonpolar or semipolar plane) of the semiconductor base layer is formed on the principal plane of the semiconductor base layer.
- the nitride semiconductor multilayer structure portion made of group III nitride semiconductors, having the parallel surface, the first inclined surface and the second inclined surface is formed on the region extending onto the insulating layer from the aperture of the insulating layer.
- the nitride semiconductor multilayer structure portion includes the two types of group III nitride semiconductor layers at least having different lattice constants.
- the gate electrode is opposed to the second inclined surface of the nitride semiconductor multilayer structure portion.
- the two types of group III nitride semiconductor layers having different lattice constants are electrically connected with the source electrode.
- the drain electrode is formed on the back surface of the semiconductor base layer opposite to the principal plane thereof, and electrically connected with the semiconductor base layer.
- two-dimensional electron gas is formed in the vicinity of the interface therebetween due to the heterojunction of these layers.
- this two-dimensional electron gas is employed as a current channel.
- the source electrode and the drain electrode are opposed to each other through the semiconductor base layer, to constitute a vertical nitride semiconductor device (CAVET: Current Aperture Vertical Electron Transistor).
- the group III nitride semiconductors constituting the semiconductor base layer and the nitride semiconductor multi player structure portion can be generally expressed as Al x In y Ga 1-x-y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 and 0 ⁇ x+y ⁇ 1) respectively.
- the conductive group III nitride semiconductor employed for the semiconductor base layer can be prepared from GaN (gallium nitride) or InN (indium nitride), for example.
- a GaN layer and an AlGaN layer for example, can be combined with each other.
- an AlGaN layer and another AlGaN layer may be combined with each other, so far as the AlGaN layers have different lattice constants.
- semiconductor layers of the same composition formed by modulation doping varying impurity concentrations may be combined with each other.
- the surface of the group III nitride semiconductor layer on which the source electrode is formed is preferably the parallel surface of the nitride semiconductor multilayer structure portion.
- this GaN layer can be formed by an i-type GaN layer containing no impurity, a high-resistance layer containing Fe (iron) or the like or a high-resistance n ⁇ -type GaN layer containing an impurity in a low concentration, for example.
- the gate electrode is opposed to the second inclined surface of the nitride semiconductor multilayer structure portion, whereby a depletion layer can spread from this gate electrode into the nitride semiconductor multilayer structure portion. Thereafter, a proper value is set to the thickness of the layer on the side of the second inclined surface in the layer forming the two-dimensional electron gas and the layer closer to the surface layer of the nitride semiconductor multilayer structure portion. Due to the depletion layer spreading in the nitride semiconductor multilayer structure portion, it is possible to annihilate (pinch off) the two-dimensional electron gas formed in the vicinity of the interface between the group III nitride semiconductor layers.
- the principal plane of the semiconductor base layer is defined by a nonpolar or semipolar plane, whereby threading dislocations (spiral dislocations, for example) in the c-axis direction present in the semiconductor base layer parallelly or inclinatorily extend with respect to the principal plane of the semiconductor base layer.
- threading dislocations spiral dislocations, for example
- the nitride semiconductor multilayer structure portion is formed by epitaxially growing the group III nitride semiconductors from the principal plane of the semiconductor base layer, for example, transfer of the threading dislocations from the semiconductor base layer to the nitride semiconductor multilayer structure portion can be suppressed. Therefore, the threading dislocations in the semiconductor base layer can be prevented from generating a leakage current, whereby the device characteristics of the nitride semiconductor device can be improved.
- the second inclined surface opposed to the gate electrode is defined by a plane of the ⁇ c-axis side inclined with respect to the principal plane of the semiconductor base layer.
- the former is higher than the latter.
- the nitride semiconductor multilayer structure portion is formed by forming a mask having an aperture partially exposing the principal plane of the semiconductor base layer on the principal plane and growing the group III nitride semiconductor layers from the aperture of the mask, therefore, an interface parallel to the second inclined surface can be positioned closer to the aperture of the mask than an interface parallel to the first inclined surface.
- the mask employed for growing the group III nitride semiconductor layers can be utilized as the insulating layer.
- nitride semiconductor device In order to operate this nitride semiconductor device, a bias voltage positive on the drain side is applied between the source and the drain. In this nitride semiconductor device, the depletion layer spreading from the gate electrode pinches off the two-dimensional electron gas (channel portion) on the side of the second inclined surface, as hereinabove described.
- one of the two types of group III nitride semiconductor layers having different lattice constants is an i-type or high-resistance n ⁇ -type GaN layer, electrons in the two-dimensional electron gas on the side of the first inclined surface do not flow into the semiconductor base layer through the GaN layer.
- the source and the drain are cut off from each other.
- a bias voltage of not less than a prescribed value (gate threshold voltage) positive with reference to the potential of the source electrode is applied to the gate electrode from this state, the two-dimensional electron gas is released from the pinch-off state.
- the two-dimensional electron gas moves and electrons reach a portion around an edge of the aperture of the insulating layer closer to the second inclined surface.
- the electrons reaching the portion around the edge of the aperture closer to the second inclined surface flow in the group III nitride semiconductor layers located in the aperture due to the potential of the drain electrode, to flow into the semiconductor base layer.
- the electrons reach the drain electrode through the semiconductor base layer, to allow the source and the drain to conduct.
- the source and the drain are allowed to conduct when a bias voltage is applied to the gate electrode while the source and the drain are cut off from each other when no bias voltage is applied to the gate electrode, to achieve a normally-off operation.
- the second inclined surface is inclined with respect to the principal plane (nonpolar or semipolar plane) of the semiconductor base layer, whereby the surface parallel to the second inclined surface is polarized. Therefore, the part of the two-dimensional electron gas along the second inclined surface can be inhibited from reduction in electron density. Consequently, the nitride semiconductor device can be inhibited from reduction in channel mobility.
- the semiconductor base layer may include an m-plane GaN substrate having a principal plane defined by an m-plane or an a-plane GaN substrate having a principal plane defined by an a-plane.
- m-plane GaN substrate or the a-plane GaN substrate threading dislocations (spiral dislocations, for example) in the c-axis direction present in the substrate extend parallelly to the principal plane (m- or a-plane).
- the semiconductorbase layer is formed by an m-plane GaN substrate or an a-plane GaN substrate, therefore, even if the nitride semiconductor multilayer structure portion is formed by epitaxy, for example, transfer of the threading dislocations from the GaN substrate to the nitride semiconductor multilayer structure portion can be further suppressed.
- the second inclined surface is defined by a -c-plane.
- the electron density of the part of the two-dimensional electron gas along the second inclined surface can be further increased, whereby a nitride semiconductor device having excellent channel mobility can be implemented.
- the nitride semiconductor device further includes a passivation film made of SiN formed in contact with the surface of the nitride semiconductor multilayer structure portion.
- the passivation film made of SiN is formed in contact with the surface of the nitride semiconductor multilayer structure portion, whereby surface charge of the nitride semiconductor multilayer structure portion can be suppressed. Consequently, the quantity of trap levels on the surface of the nitride semiconductor multilayer structure portion can be reduced, whereby current collapse can be suppressed.
- SiN is interposed between the second inclined surface and the gate electrode in the nitride semiconductor device.
- the nitride semiconductor device has the so-called MIS (Metal Insulator Semiconductor) structure.
- MIS Metal Insulator Semiconductor
- surface charge (interface charge) around the interface between the nitride semiconductor multilayer structure portion and SiN can be suppressed. Consequently, current collapse as well as generation of a leakage current can be suppressed.
- a portion of the interface between the two types of group III nitride semiconductor layers at least having different lattice constants parallel to the second inclined surface is positioned closer to the aperture than a portion, included in the interface, parallel to the first inclined surface.
- the nitride semiconductor multilayer structure portion has a mesa shape including an upper wall parallel to the principal plane of the semiconductor base layer and sidewalls of a +c-axis side and a ⁇ c-axis side inclined with respect to the principal plane of the semiconductor base layer, and in this case, the surface of the upper wall forms the parallel surface, the sidewall of the +c-side side forms the first inclined surface, and the sidewall of the ⁇ c-axis side forms the second inclined surface.
- the two types of group III nitride semiconductor layers at least having different lattice constants are in a multilayer structure of an n ⁇ -type GaN layer provided on the side of the semiconductor base layer and an n + -type AlGaN layer having a different lattice constant from the n ⁇ -type GaN layer.
- the insulating layer is made of anoxide, a nitride or an oxynitride in the nitride semiconductor device.
- a method for producing a nitride semiconductor device of the present invention includes the steps of: forming an insulating layer having an aperture partially exposing a principal plane of a semiconductor base layer on the principal plane, defined by a nonpolar plane or a semipolar plane, of the semiconductor base layer made of a conductive group III nitride semiconductor; growing two types of group III nitride semiconductor layers at least having different lattice constants from the aperture successively from the side of the principal plane of the semiconductor base layer through the insulating layer employed as a mask and stopping the growth when a mesa structure having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a first inclined surface of a+c-axis side and a second inclined surface of a ⁇ c-axis side inclined with respect to the principal plane of the semiconductor base layer is formed on a region of the insulating layer; forming a gate electrode to be opposed to the second inclined surface; forming a source electrode to be electrically connected with the group III nitride
- the former is higher than the latter, as hereinabove described. If the growth of the group III nitride semiconductor layers is stopped when the mesa structure having the parallel surface, the first inclined surface of the +c-axis side and the second inclined surface of the ⁇ c-axis side is formed on the region of the insulating layer as in this method, therefore, such a nitride semiconductor multilayer structure that a portion of an interface between the two types of group III nitride semiconductor layers having different lattice constants parallel to the second inclined surface is positioned closer to an aperture of the insulating layer than portion, included in the interface, parallel to the first inclined surface is obtained.
- the aforementioned nitride semiconductor device can be prepared according to this method through the difference between the growth rates of the group III nitride semiconductors in the +c-axis direction and the ⁇ c-axi
- FIG. 1 is a schematic sectional view of a CAVET according to an embodiment of the present invention.
- FIGS. 2A to 2D are schematic sectional views successively showing the steps for producing the CAVET shown in FIG. 1 .
- FIG. 3 is a schematic sectional view of a conventional CAVET.
- FIG. 1 is a schematic sectional view of a CAVET according to an embodiment of the present invention.
- This CAVET Current Aperture Vertical Electron Transistor
- HEMT High Electron Mobility Transistor
- HEMT High Electron Mobility Transistor
- the CAVET includes an n + -type GaN substrate 1 (semiconductor base layer), an insulating film 2 (insulating layer) formed on a principal plane 1 a of this n + -type GaN substrate 1 with an aperture 3 partially exposing the principal plane 1 a , and a nitride semiconductor multilayer structure portion 4 formed on a region extending onto the insulating film 2 from the aperture 3 of the insulating film 2 .
- the principal plane 1 a of the n + -type GaN substrate 1 is defined by a nonpolar plane or a semipolar plane, more specifically, a nonpolar plane such as an m-plane ( 10 - 10 ) or an a-plane ( 11 - 20 ) or asemipolarplanesuch as ( 10 - 13 ), ( 10 - 11 ) or ( 11 - 22 ).
- This plane orientation is selected in response to the types of group III nitride semiconductors crystal-grown from the principal plane 1 a .
- the principal plane 1 a of the n + -type GaN substrate 1 is defined by an m-plane.
- the n + -type GaN substrate 1 has a high n-type impurity concentration of 1 ⁇ 10 cm ⁇ 3 to 5 ⁇ 10 18 cm ⁇ 3 ,for example.
- the insulating film 2 is in the form of a plurality of (two in FIG. 1 ) stripes extending in the a-axis direction, and these stripes hold the aperture 3 partially exposing the principal plane 1 a of the n + -type GaN substrate 1 therebetween.
- the insulating film 2 can be prepared from an oxide, a nitride or an oxynitride such as SiO 2 (silicon oxide), Ga 2 O 3 (gallium oxide), MgO (magnesiumoxide), Sc 2 O 3 (scandium oxide), SiN (silicon nitride), SiON (silicon oxynitride) or the like, for example.
- SiO 2 is employed in this embodiment.
- stress on the group III nitride semiconductors grown from the principal plane 1 a of the n + -type GaN substrate 1 can be controlled. Therefore, cracks in the group III nitride semiconductors can be suppressed. Further, the insulating film 2 can be relatively easily formed by lithography or etching.
- the thickness of the insulating film 2 is 50 nm to 500 nm, for example. This thickness is preferably changed to the optimum value in response to the area of the aperture 3 or the thickness of an n ⁇ -type GaN layer 5 described later.
- the opening width of the aperture 3 (width in the c-axis direction) is 1 ⁇ m to 10 ⁇ m, for example.
- the nitride semiconductor multilayer structure portion 4 has an upper wall parallel to the principal plane la of the n + -type GaN substrate 1 and sidewalls of the +c-axis side and the ⁇ c-axis side inclined with respect to the principal plane 1 a on the region extending onto the insulating film 2 from the aperture 3 of the insulating film 2 .
- the nitride semiconductor multilayer structure portion 4 is mesa-shaped in sectional view.
- the nitride semiconductor multilayer structure portion 4 is in the form of stripes extending in the a-axis direction, similarly to the insulating film 2 .
- the surface of the upper wall forms a parallel surface 7 parallel to the principal plane 1 a
- the surface of the sidewall on the +c-axis side forms a +c-axis side inclined surface 8 (first inclined surface)
- the surface of the sidewall on the ⁇ c-axisside forms a ⁇ c-axis side inclined surface 9 (second inclined surface).
- the +c-axis side inclined surface 8 and the ⁇ c-axis side inclined surface 9 inclined with respect to the principal plane 1 a (m-plane) are defined by semipolar planes such as ( 10 - 13 ), ( 10 - 11 ) or ( 11 - 22 ), for example.
- the nitride semiconductor multilayer structure portion 4 includes the n -type GaN layer 5 and an n + -type AlGaN layer 6 having a different lattice constant from the n ⁇ -type GaN layer 5 .
- the n ⁇ -type GaN layer 5 and the n + -type AlGaN layer 6 are laminated in this order through an interface 15 parallel to the parallel surface 7 (m-plane), the +c-axis side inclined surface 8 and the ⁇ c-axis side inclined surface 9 of the nitride semiconductor multilayer structure portion 4 .
- the lower n ⁇ -type GaN layer 5 is mesa-shaped in section, with an upper wall parallel to the upper wall of the nitride semiconductor multilayer structure portion 4 and sidewalls parallel to the sidewalls of the +c-axis side and the ⁇ c-axis side.
- the upper n + -type AlGaN layer 6 has an upper wall in contact with the upper wall of the n ⁇ -type GaN layer 5 and sidewalls in contact with the sidewalls of the n ⁇ -type GaN layer 5 . Further, the n + -type AlGaN layer 6 forms the outermost layer of this multilayer structure, and hence the surface (upper surface) of the upper wall and the surfaces (side surfaces) of the sidewalls thereof form the parallel surface 7 (m-plane), the +c-axis side inclined surface 8 and the ⁇ c-axis side inclined surface 9 of the nitride semiconductor multilayer structure portion 4 respectively.
- the thickness of the n ⁇ -type GaN layer 5 is 1 ⁇ m to 2 ⁇ m, for example.
- the thickness (in the m-axis direction) of the upper wall of the n + -type AlGaN layer 6 is 10 nm to 30 nm, for example.
- the thickness of the sidewall on the +c-axis side is 10 nm to 30 nm, for example.
- the thickness of the sidewall on the ⁇ c-axis side is 10 nm to 30 nm, for example.
- a portion of the interface 15 (GaN/AlGaN interface) between the n ⁇ -type GaN layer 5 and the n + -type AlGaN layer 6 on the ⁇ c-axis side is positioned closer to the aperture 3 than a portion on the +c-axis side.
- the distance L 1 between the lower end of the portion of the interface 15 on the +c-axis side in the m-axis direction and an end of the aperture 3 of the insulating film 2 on the +c-axis side is larger than the distance L 2 between the lower end of the portion of the interface 15 on the ⁇ c-axis side in the m-axis direction and an end of the aperture 3 of the insulating film 2 on the ⁇ c-axis side.
- the distances L 1 and L 2 are 1 ⁇ m to 100 ⁇ m and 0.1 ⁇ m to 10 ⁇ m respectively, for example. These distances L 1 and L 2 are properly selected in response to the types of the group III nitride semiconductors constituting the nitride semiconductor multilayer structure portion 4 .
- two-dimensional electron gas 14 (2DEG) is formed around the interface 15 (GaN/AlGaN interface).
- This two-dimensional electron gas 14 results from the heterojunction of the n ⁇ -type GaN layer 5 and the n + -type AlGaN layer 6 , and is present generally over a region of the n ⁇ -type GaN layer 5 around the interface 15 in the nitride semiconductor multilayer structure portion 4 .
- this two-dimensional electron gas 14 is employed as a current channel.
- the two-dimensional electron gas 14 has a concentration of about 10 13 cm ⁇ 2 in a portion parallel to the c-plane when the Al composition in the n + -type AlGaN layer 6 is 20%, for example.
- a source electrode 11 is formed in contact with the upper wall (upper surface) of the n + -type AlGaN layer 6 .
- the source electrode 11 is so formed as to attain ohmic contact between the same and the n + -type AlGaN layer 6 , and electrically connected to the two-dimensional electron gas 14 through the n + -type AlGaN layer 6 and the n ⁇ -type GaN layer 5 .
- the source electrode 11 can be constituted of a multilayer structure of Ti/Al (lower layer/upper layer), for example.
- the source electrode 11 can be excellently brought into ohmic contact with the n + -type AlGaN layer 6 by a treatment such as thermal alloying (annealing), for example.
- a gate electrode 10 is formed on the ⁇ c-axis side inclined surface 9 , a portion of the upper wall of the n + -type AlGaN layer 6 opposed to the aperture 3 of the insulating film 2 and an edge portion of the insulating film 2 closer to the ⁇ c-axis side inclined surface 9 , to be opposed thereto.
- the gate electrode 10 can be made of a conductive material such as Pt (platinum), Al (aluminum), Ni/Au (alloy of nickel and gold), Ni/Ti/Au (alloy of nickel, titanium and gold), Pd/Au (alloy of palladium and gold), Pd/Ti/Au (alloy of palladium, titanium and gold), Pd/Pt/Au (alloy of palladium, platinum and gold) or polysilicon, for example.
- a conductive material such as Pt (platinum), Al (aluminum), Ni/Au (alloy of nickel and gold), Ni/Ti/Au (alloy of nickel, titanium and gold), Pd/Au (alloy of palladium and gold), Pd/Ti/Au (alloy of palladium, platinum and gold) or polysilicon, for example.
- a drain electrode 12 is formed in contact with the back surface of the n + -type GaN substrate 1 opposite to the principal plane 1 a , to entirely cover the back surface.
- the drain electrode 12 is electrically connected with the n + -type GaN substrate 1 .
- the drain electrode 12 can be constituted of a multilayer structure of Ti/Al (layer closer to the n + -type GaN substrate 1 /layer farther from the n + -type GaN substrate 1 ), for example.
- a passivation film 13 made of SiN is formed on the surfaces of the nitride semiconductor multilayer structure portion 4 and the insulating film 2 , to entirely cover these surfaces.
- the sidewall on the ⁇ c-axis side of the n + -type AlGaN layer 6 has the thickness of 10 nm to 30 nm, for example, whereby a depletion layer spreads from the gate electrode 10 up to a region shown by broken slant lines B in FIG. 1 . Therefore, the part of the two-dimensional electron gas 14 closer to the ⁇ c-axis side inclined surface 9 is pinched off.
- the distance L 1 is larger than the distance L 2 and the n ⁇ -type GaN layer 5 is a high-resistance layer, whereby electrons in the part of the two-dimensional electron gas 14 closer to the +c-axis side inclined surface 8 do not move in the n ⁇ -type GaN layer 5 to flow into n + -type GaN substrate 1 .
- a bias voltage positive on the drain side is applied between the source and the drain.
- a bias voltage of not less than a prescribed value (gate threshold voltage) positive with reference to the potential of the source electrode 11 is applied to the gate electrode 10 from this state, whereby the two-dimensional electron gas 14 is released from the pinch-off state, and a current flows in a direction shown by solid arrow D in FIG. 1 .
- the two-dimensional electron gas 14 released from the pinch-off state so moves that electrons reach a portion around an edge portion of the aperture 3 of the insulating film 2 closer to the ⁇ c-axis side inclined surface 9 .
- the electrons reaching the portion around the edge portion of the aperture 3 of the insulating film 2 closer to the ⁇ c-axis side inclined surface 9 flow in the portion of the n ⁇ -type GaN layer 5 located in the aperture 3 to flow into the n + -type GaN substrate 1 , due to the potential of the drain electrode 12 .
- the electrons reach the drain electrode 12 through the n + -type GaN substrate 1 , to allow the source and the drain to conduct.
- the source and the drain are allowed to conduct when a bias voltage is applied to the gate electrode 10 while the source and the drain are cut off from each other when no bias voltage is applied to the gate electrode 10 , to achieve a normally-off operation.
- FIGS. 2A to 2D are schematic sectional views successively showing the steps for producing the CAVET shown in FIG. 1 .
- an insulating film made of SiO 2 is first formed on the overall principal plane 1 a of the n + -type GaN substrate 1 by PECVD (Plasma Enhanced Chemical Vapor Deposition), for example. Then, a photoresist film having an opening corresponding to the aperture 3 is formed on the insulating film by well-known photolithography. Then, the insulating film is dry-etched through the photoresist film serving as a mask, whereby the aperture 3 is formed in the insulating film and the insulating film 2 is formed as the stripes extending in the a-axis direction, as shown in FIG. 2A .
- PECVD Pullasma Enhanced Chemical Vapor Deposition
- group III nitride semiconductors are epitaxially grown from the principal plane 1 a of the n + -type GaN substrate 1 partially exposed from the aperture 3 by the so-called ELO (Epitaxial Lateral Overgrowth).
- the group III nitride semiconductors can be grown by MOCVD (Metal Organic Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy), VPE (Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy) or the like, for example.
- MOCVD Metal Organic Chemical Vapor Deposition
- LPE Liquid Phase Epitaxy
- VPE Vapor Phase Epitaxy
- MBE Molecular Beam Epitaxy
- n ⁇ -type GaN is first grown from the principal plane 1 a of the n + -type GaN substrate 1 .
- This n ⁇ -type GaN is first grown on the region in the aperture 3 of the insulating film 2 under conditions (growth temperature of 1000° C. to 1100° C. and growth pressure of 30 Torr to 300 Torr, for example) facilitating growth in the m-axis direction.
- the n ⁇ -type GaN is grown on the region extending onto the insulating film 2 from the aperture 3 in the m-axis direction and the c-axis direction under conditions (growth temperature of 950° C. to 1050° C.
- n ⁇ -type GaN is grown in the +c-axis direction and the ⁇ c-axis direction through the aperture 3 extending in the a-axis direction.
- n ⁇ -type GaN is mesa-shaped in sectional view with an upper wall parallel to the principal plane 1 a of the n + -type GaN substrate 1 and sidewalls of the +c-axis side and the ⁇ c-axis side inclined with respect to the principal plane 1 a on the region of the insulating film 2 .
- n ⁇ -type GaN layer 5 extending onto the insulating film 2 from the aperture 3 is formed as shown in FIG. 2B . Thereafter n + -type AlGaN is grown from the surface of the n ⁇ -type GaN layer 5 .
- This n + -type AlGaN is grown in the m-axis direction and the c-axis direction similarly to the n ⁇ -type GaN, and the growth thereof is stopped when the grown n + -type AlGaN is mesa-shaped in sectional view with an upper wall parallel to the principal plane 1 a of the n + -type GaN substrate 1 and sidewalls of the +c-axis side and the ⁇ c-axis side inclined with respect to the principal plane 1 a on the region of the insulating film 2 .
- the n + -type AlGaN layer 6 is formed on the n ⁇ -type GaN layer 5 , thereby forming the nitride semiconductor multilayer structure portion 4 having the parallel surface 7 parallel to the principal plane 1 a of the n + -type GaN substrate 1 , the +c-axis side inclined surface 8 and the ⁇ c-axis side inclined surface 9 .
- Si for example, may be employed as an n-type impurity for growing the n ⁇ -type GaN and the n + -type AlGaN.
- the former is higher than the latter.
- the n ⁇ -type GaN and the n + -type AlGaN are grown up to positions farther from the aperture 3 in the +c-axis direction, as compared with the ⁇ c-axis direction.
- the portion of the interface 15 (GaN/AlGaN interface) between the n ⁇ -type GaN layer 5 and the n + -type AlGaN layer 6 on the ⁇ c-axis side can be positioned closer to the aperture 3 than the portion on the +c-axis side.
- the source electrode 11 is formed on the upper wall (upper surface) of the n + -type AlGaN layer 6 , as shown in FIG. 2C .
- a photoresist film (not shown) having an aperture in a region for forming the source electrode 11 is formed by well-known photolithography.
- metals Ti and Al, for example
- the photoresist film is removed, thereby lifting off unnecessary portions (other than the source electrode 11 ) of the metals along with the photoresist film.
- the source electrode 11 is formed in contact with the upper wall (upper surface) of the n + -type AlGaN layer 6 through these steps. After the formation of the source electrode 11 , thermal alloying (annealing) is so performed that the source electrode 11 and the n + -type AlGaN layer 6 are in ohmic contact with each other.
- a photoresist film (not shown) having an aperture in a region for forming the gate electrode 10 is formed by well-known photolithography. Then, a metal (the aforementioned conductive material, for example) employed as the material for the gate electrode 10 is sputtered from above this photoresist film. Thereafter the photoresist film is removed, thereby lifting off unnecessary portions (other than the gate electrode 10 ) of the metal along with the photoresist film.
- an insulating film made of SiN is formed to cover the overall surface of the structure provided on the n + -type GaN substrate 1 .
- This insulating film is formed by ECR (Electron Cyclotron Resonance) sputtering, for example.
- contact holes exposing the source electrode 11 and the gate electrode 10 respectively are formed in the insulating film. These contact holes are formed by dry etching with the aforementioned etching gas, for example. Due to the formation of these contact holes, the insulating film of SiN forms the passivation film 13 covering the overall surfaces of the nitride semiconductor multilayer structure portion 4 and the insulating film 2 , as shown in FIG. 2D .
- the drain electrode 12 is formed in contact with the overall back surface of the n + -type GaN substrate 1 opposite to the principal plane la, as shown in FIG. 2D .
- thermal alloying annealing
- the CAVET having the structure shown in FIG. 1 can be obtained in this manner.
- the two-dimensional electron gas 14 results from the heterojunction between the n ⁇ -type GaN layer 5 and the n + -type AlGaN layer 6 , and hence the description thereof is omitted in relation to the steps shown in FIGS. 2A to 2D .
- a CAVET capable of a normally-off operation can be implemented.
- the principal plane 1 a of the n + -type GaN substrate 1 is defined by the m-plane (nonpolar plane), and hence threading dislocations (spiral dislocations, for example) in the c-axis direction present in the n + -type GaN substrate 1 extend parallelly to the principal plane 1 a .
- the n ⁇ -type GaN is grown in the m-axis direction in the region in the aperture 3 of the insulating film 2 , therefore, transfer of the through locations from the n + -type GaN substrate 1 to the n ⁇ -type GaN can be suppressed.
- the threading dislocations in the n + -type GaN substrate 1 can be prevented from generating a leakage current flowing to the nitride semiconductor multilayer structure portion 4 , whereby the device characteristics of the CAVET can be improved.
- the principal plane 1 a of the n + -type GaN substrate 1 is defined by the m-plane as in this embodiment, transfer of the threading dislocations to the nitride semiconductor multilayer structure portion 4 can be further suppressed.
- the ⁇ c-axis side inclined surface 9 is defined by the semipolar plane such as ( 10 - 13 ), ( 10 - 11 ) or ( 11 - 22 ) inclined with respect to the principal plane 1 a (m-plane) of the n + -type GaN substrate 1 . Therefore, the surface parallel to the ⁇ c-axis side inclined surface 9 is polarized. Thus, the part, serving as the current channel in this CAVET, of the two-dimensional electron gas 14 along the ⁇ c-axis side inclined surface 9 can be inhibited from reduction in electron density. Consequently, the CAVET can be inhibited from reduction in channel mobility.
- the passivation film 13 made of SiN is so formed as to cover the overall surfaces of the nitride semiconductor multilayer structure portion 4 and the insulating film 2 .
- surface charge in the nitride semiconductor multilayer structure portion 4 can be suppressed by forming the passivation film 13 in contact with the surface of the nitride semiconductor multilayer structure portion 4 . Consequently, the quantity of trap levels on the surface of the nitride semiconductor multilayer structure portion 4 can be reduced, whereby current collapse can be suppressed.
- the two-dimensional electron gas 14 may be formed on an i-type GaN layer containing no impurity, in place of the n ⁇ -type GaN layer 5 .
- the nitride semiconductor multilayer structure portion 4 may not have the GaN/AlGaN interface, so far as the same includes two types of group III nitride semiconductor layers at least having different lattice constants with an interface forming the two-dimensional electron gas 14 .
- the nitride semiconductor multilayer structure portion 4 may have the other layers of group III nitride semiconductor on two types of group III nitride semiconductor layers at least having different lattice constants with an interface.
- the source electrode 11 may have another structure, so far as the same is electrically connected with the two-dimensional electron gas 14 .
- the nitride semiconductor multilayer structure portion 4 includes group III nitride semiconductor layers other than the n-type GaN layer 5 and the n + -type AlGaN layer 6 , for example, the source electrode 11 may be formed on either one of the upper walls (upper surfaces) of the group III nitride semiconductor layers parallel to the principal plane 1 a of the n + -type GaN substrate 1 .
- the gate electrode 10 may be formed through a gate insulating film made of SiN or the like.
- the CAVET has the so-called MIS (Metal Insulator Semiconductor) structure.
- MIS Metal Insulator Semiconductor
- surface charge (interface charge) around the interface between the nitride semiconductor multilayer structure portion 4 and SiN can be suppressed, whereby current collapse as well as generation of a leakage current can be suppressed.
- the n + -type GaN substrate 1 may be replaced with a substrate such as an InN (nitride indium) substrate, for example, consisting of a conductive group III nitride semiconductor.
- a substrate such as an InN (nitride indium) substrate, for example, consisting of a conductive group III nitride semiconductor.
- the ⁇ c-axis side inclined surface 9 can be defined by a ⁇ c-plane by employing an n + -type GaN substrate having a principal plane defined by a semipolar plane and growing a group III nitride semiconductor from this principal plane.
- the ⁇ c-axis side inclined surface 9 is defined by a ⁇ c-plane, the electron density of the part of the two-dimensional electron gas 14 along the ⁇ c-axis side inclined surface 9 can be more increased, whereby a CAVET having excellent channel mobility can be implemented.
- the Al composition may be uniform, or portions having different Al compositions may be distributed.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a nitride semiconductor device employing a group III nitride semiconductor and a method for producing the same.
- 2. Description of Related Art
- Conventionally, the so-called CAVET (Current Aperture Vertical Electron Transistor) is known as a vertical transistor employing two-dimensional electron gas resulting from a semiconductor heterojunction as a channel such as an HEMT (High Electron Mobility Transistor).
-
FIG. 3 is a schematic sectional view of a conventional CAVET. - This CAVET includes a GaN (gallium nitride)
substrate 101, a high-resistance layer (an n−-type GaN (gallium nitride)layer 102 inFIG. 3 ) having a low n-type impurity concentration stacked on aprincipal growth plane 101 a of theGaN substrate 101 and a layer (an AlGaN (aluminum gallium nitride)layer 103 inFIG. 3 , for example), having a different lattice constant from the n−-type GaN layer 102, laminated on the n−-type GaN layer 102, for example. In other words, the n−-type GaN layer 102 and the AlGaNlayer 103 are successively epitaxially grown in order on theGaN substrate 101 with the interface parallel to theprincipal growth plane 101 a. - A p-
type GaN layer 104 provided with anopening 105 on a position opposed to the AlGaNlayer 103 is formed on an intermediate portion of the n−-type GaN layer 102 in the thickness direction. - In the vicinity of the interface between a portion located above the p-
type GaN layer 104 and theAlGaN layer 103, two-dimensional electron gas 106 parallel to theprincipal growth plane 101 a is formed in the n−-type GaN layer 102 due to the heterojunction therebetween. - A
gate electrode 107 is formed on theAlGaN layer 103, to form a Schottky junction with theAlGaN layer 103. Twosource electrode 108 are formed to be opposed to each other through thegate electrode 107, to form ohmic contact with the AlGaNlayer 103 or the n−-type GaN layer 102. - A
drain electrode 109 is formed on the back surface of theGaN substrate 101 opposite to the principal growth plane lola, to form ohmic contact with theGaN substrate 101. - Thus, the
source electrodes 108 and thedrain electrode 109 are opposed to each other through theGaN substrate 101, to constitute the CAVET having a vertical structure. - When a bias voltage positive on the drain side is applied between the source and the drain in the CAVET having the aforementioned vertical structure, a potential difference is caused between the source and the drain, and a current flows from the
drain electrode 109 to thesource electrode 108. More specifically, when the bias voltage is applied between the source and the drain, the two-dimensional electron gas 106 moves due to the potential difference therebetween, and electrons reach theopening 105 of the p-type GaN layer 104. - The electrons reaching the opening 105 flow in the n−-
type GaN layer 102 through theopening 105 to flow into theGaN substrate 101, due to the potential of thedrain electrode 109. The electrons flowing into theGaN substrate 101 reach thedrain electrode 109 through theGaN substrate 101. - Thus, the current flows from the
drain electrode 109 to thesource electrode 108, to allow the source and the drain to conduct. - However, the aforementioned CAVET capable of implementing the vertical structure has the so-called normally-on characteristic with a gate threshold voltage Vth of −16 V. In order to turn off the CAVET, therefore, a negative voltage must be applied to the
gate electrode 107, to pinch off the two-dimensional electron gas 106. - Therefore, the
principal growth plane 101 a of the GaNsubstrate 101 may be defined by a nonpolar plane (an a-plane or an m-plane). When theprincipal growth plane 101 a of theGaN substrate 101 is defined by a nonpolar plane, the two-dimensional electron gas 106 formed in the n−-type GaN layer 102 parallel to the nonpolar plane is utilized. - However, no remarkable polarization takes place on the nonpolar plane, and hence the two-
dimensional electron gas 106 has a low electron density. This leads to such another disadvantage that the channel mobility of the CAVET is reduced, although the CAVET approaches the so-called normally-off characteristic with the gate threshold voltage Vth exhibiting a positive value. - An object of the present invention is to provide a normally-off type nitride semiconductor device and a method for producing the same.
- A nitride semiconductor device of the present invention includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a −c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III nitride semiconductor layers; and a drain electrode formed on a back surface of the semiconductor base layer opposite to the principal plane.
- According to this structure, the insulating layer having the aperture partially exposing the principal plane (nonpolar or semipolar plane) of the semiconductor base layer is formed on the principal plane of the semiconductor base layer. The nitride semiconductor multilayer structure portion, made of group III nitride semiconductors, having the parallel surface, the first inclined surface and the second inclined surface is formed on the region extending onto the insulating layer from the aperture of the insulating layer. The nitride semiconductor multilayer structure portion includes the two types of group III nitride semiconductor layers at least having different lattice constants. The gate electrode is opposed to the second inclined surface of the nitride semiconductor multilayer structure portion. The two types of group III nitride semiconductor layers having different lattice constants are electrically connected with the source electrode. The drain electrode is formed on the back surface of the semiconductor base layer opposite to the principal plane thereof, and electrically connected with the semiconductor base layer.
- In one of the two types of group III nitride semiconductor layers having different lattice constants, two-dimensional electron gas is formed in the vicinity of the interface therebetween due to the heterojunction of these layers. In the nitride semiconductor device, this two-dimensional electron gas is employed as a current channel. Thus, the source electrode and the drain electrode are opposed to each other through the semiconductor base layer, to constitute a vertical nitride semiconductor device (CAVET: Current Aperture Vertical Electron Transistor).
- The group III nitride semiconductors constituting the semiconductor base layer and the nitride semiconductor multi player structure portion can be generally expressed as AlxInyGa1-x-yN (0≦x≦1, 0≦y≦1 and 0≦x+y≦1) respectively. Among the group III nitride semiconductors expressed in this manner, the conductive group III nitride semiconductor employed for the semiconductor base layer can be prepared from GaN (gallium nitride) or InN (indium nitride), for example. As the two types of group III nitride semiconductor layers having different lattice constants, a GaN layer and an AlGaN layer, for example, can be combined with each other. Alternatively, an AlGaN layer and another AlGaN layer may be combined with each other, so far as the AlGaN layers have different lattice constants.
- As the two types of group III nitride semiconductor layers having different lattice constants, further, semiconductor layers of the same composition formed by modulation doping varying impurity concentrations may be combined with each other.
- When the source electrode is formed on the group III nitride semiconductor layer corresponding to the outermost layer of the nitride semiconductor multilayer structure portion, the surface of the group III nitride semiconductor layer on which the source electrode is formed is preferably the parallel surface of the nitride semiconductor multilayer structure portion.
- When one of the two types of group III nitride semiconductor layers having different lattice constants is a GaN layer, this GaN layer can be formed by an i-type GaN layer containing no impurity, a high-resistance layer containing Fe (iron) or the like or a high-resistance n−-type GaN layer containing an impurity in a low concentration, for example.
- In this nitride semiconductor device, the gate electrode is opposed to the second inclined surface of the nitride semiconductor multilayer structure portion, whereby a depletion layer can spread from this gate electrode into the nitride semiconductor multilayer structure portion. Thereafter, a proper value is set to the thickness of the layer on the side of the second inclined surface in the layer forming the two-dimensional electron gas and the layer closer to the surface layer of the nitride semiconductor multilayer structure portion. Due to the depletion layer spreading in the nitride semiconductor multilayer structure portion, it is possible to annihilate (pinch off) the two-dimensional electron gas formed in the vicinity of the interface between the group III nitride semiconductor layers.
- The principal plane of the semiconductor base layer is defined by a nonpolar or semipolar plane, whereby threading dislocations (spiral dislocations, for example) in the c-axis direction present in the semiconductor base layer parallelly or inclinatorily extend with respect to the principal plane of the semiconductor base layer. When the nitride semiconductor multilayer structure portion is formed by epitaxially growing the group III nitride semiconductors from the principal plane of the semiconductor base layer, for example, transfer of the threading dislocations from the semiconductor base layer to the nitride semiconductor multilayer structure portion can be suppressed. Therefore, the threading dislocations in the semiconductor base layer can be prevented from generating a leakage current, whereby the device characteristics of the nitride semiconductor device can be improved.
- Further, the second inclined surface opposed to the gate electrode is defined by a plane of the −c-axis side inclined with respect to the principal plane of the semiconductor base layer.
- Comparing the growth rates of a group III nitride semiconductor in the +c-axis direction and the −c-axis direction with each other, the former is higher than the latter. When the nitride semiconductor multilayer structure portion is formed by forming a mask having an aperture partially exposing the principal plane of the semiconductor base layer on the principal plane and growing the group III nitride semiconductor layers from the aperture of the mask, therefore, an interface parallel to the second inclined surface can be positioned closer to the aperture of the mask than an interface parallel to the first inclined surface. In this case, the mask employed for growing the group III nitride semiconductor layers can be utilized as the insulating layer.
- The operation of the nitride semiconductor device is now described. In order to operate this nitride semiconductor device, a bias voltage positive on the drain side is applied between the source and the drain. In this nitride semiconductor device, the depletion layer spreading from the gate electrode pinches off the two-dimensional electron gas (channel portion) on the side of the second inclined surface, as hereinabove described.
- When the interface parallel to the second inclined surface is positioned closer to the aperture of the insulating layer than the interface parallel to the first inclined surface and one of the two types of group III nitride semiconductor layers having different lattice constants is an i-type or high-resistance n−-type GaN layer, electrons in the two-dimensional electron gas on the side of the first inclined surface do not flow into the semiconductor base layer through the GaN layer.
- When the two-dimensional electron gas on the side of the second inclined surface is pinched off, therefore, the source and the drain are cut off from each other. When a bias voltage of not less than a prescribed value (gate threshold voltage) positive with reference to the potential of the source electrode is applied to the gate electrode from this state, the two-dimensional electron gas is released from the pinch-off state.
- When released from the pinch-off state, the two-dimensional electron gas moves and electrons reach a portion around an edge of the aperture of the insulating layer closer to the second inclined surface. The electrons reaching the portion around the edge of the aperture closer to the second inclined surface flow in the group III nitride semiconductor layers located in the aperture due to the potential of the drain electrode, to flow into the semiconductor base layer.
- Then, the electrons reach the drain electrode through the semiconductor base layer, to allow the source and the drain to conduct.
- Thus, the source and the drain are allowed to conduct when a bias voltage is applied to the gate electrode while the source and the drain are cut off from each other when no bias voltage is applied to the gate electrode, to achieve a normally-off operation.
- The second inclined surface is inclined with respect to the principal plane (nonpolar or semipolar plane) of the semiconductor base layer, whereby the surface parallel to the second inclined surface is polarized. Therefore, the part of the two-dimensional electron gas along the second inclined surface can be inhibited from reduction in electron density. Consequently, the nitride semiconductor device can be inhibited from reduction in channel mobility.
- The semiconductor base layer may include an m-plane GaN substrate having a principal plane defined by an m-plane or an a-plane GaN substrate having a principal plane defined by an a-plane. In the m-plane GaN substrate or the a-plane GaN substrate, threading dislocations (spiral dislocations, for example) in the c-axis direction present in the substrate extend parallelly to the principal plane (m- or a-plane). When the semiconductorbase layer is formed by an m-plane GaN substrate or an a-plane GaN substrate, therefore, even if the nitride semiconductor multilayer structure portion is formed by epitaxy, for example, transfer of the threading dislocations from the GaN substrate to the nitride semiconductor multilayer structure portion can be further suppressed.
- Preferably, the second inclined surface is defined by a -c-plane. When the second inclined surface is defined by a -c-plane (polar plane), the electron density of the part of the two-dimensional electron gas along the second inclined surface can be further increased, whereby a nitride semiconductor device having excellent channel mobility can be implemented.
- Preferably, the nitride semiconductor device further includes a passivation film made of SiN formed in contact with the surface of the nitride semiconductor multilayer structure portion.
- According to this structure, the passivation film made of SiN is formed in contact with the surface of the nitride semiconductor multilayer structure portion, whereby surface charge of the nitride semiconductor multilayer structure portion can be suppressed. Consequently, the quantity of trap levels on the surface of the nitride semiconductor multilayer structure portion can be reduced, whereby current collapse can be suppressed.
- Preferably, SiN is interposed between the second inclined surface and the gate electrode in the nitride semiconductor device.
- According to this structure, SiN is so interposed between the second inclined surface and the gate electrode that the nitride semiconductor device has the so-called MIS (Metal Insulator Semiconductor) structure. When the nitride semiconductor device has the MIS structure, surface charge (interface charge) around the interface between the nitride semiconductor multilayer structure portion and SiN can be suppressed. Consequently, current collapse as well as generation of a leakage current can be suppressed.
- Preferably, a portion of the interface between the two types of group III nitride semiconductor layers at least having different lattice constants parallel to the second inclined surface is positioned closer to the aperture than a portion, included in the interface, parallel to the first inclined surface.
- Preferably, the nitride semiconductor multilayer structure portion has a mesa shape including an upper wall parallel to the principal plane of the semiconductor base layer and sidewalls of a +c-axis side and a −c-axis side inclined with respect to the principal plane of the semiconductor base layer, and in this case, the surface of the upper wall forms the parallel surface, the sidewall of the +c-side side forms the first inclined surface, and the sidewall of the −c-axis side forms the second inclined surface.
- Preferably, the two types of group III nitride semiconductor layers at least having different lattice constants are in a multilayer structure of an n−-type GaN layer provided on the side of the semiconductor base layer and an n+-type AlGaN layer having a different lattice constant from the n−-type GaN layer.
- Preferably, the insulating layer is made of anoxide, a nitride or an oxynitride in the nitride semiconductor device.
- A method for producing a nitride semiconductor device of the present invention includes the steps of: forming an insulating layer having an aperture partially exposing a principal plane of a semiconductor base layer on the principal plane, defined by a nonpolar plane or a semipolar plane, of the semiconductor base layer made of a conductive group III nitride semiconductor; growing two types of group III nitride semiconductor layers at least having different lattice constants from the aperture successively from the side of the principal plane of the semiconductor base layer through the insulating layer employed as a mask and stopping the growth when a mesa structure having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a first inclined surface of a+c-axis side and a second inclined surface of a −c-axis side inclined with respect to the principal plane of the semiconductor base layer is formed on a region of the insulating layer; forming a gate electrode to be opposed to the second inclined surface; forming a source electrode to be electrically connected with the group III nitride semiconductor layers; and forming a drain electrode on a back surface of the semiconductor base layer opposite to the principal plane.
- Comparing the growth rates of a group III nitride semiconductor in the +c-axis direction and the −c-axis direction with each other, the former is higher than the latter, as hereinabove described. If the growth of the group III nitride semiconductor layers is stopped when the mesa structure having the parallel surface, the first inclined surface of the +c-axis side and the second inclined surface of the −c-axis side is formed on the region of the insulating layer as in this method, therefore, such a nitride semiconductor multilayer structure that a portion of an interface between the two types of group III nitride semiconductor layers having different lattice constants parallel to the second inclined surface is positioned closer to an aperture of the insulating layer than portion, included in the interface, parallel to the first inclined surface is obtained. In other words, the aforementioned nitride semiconductor device can be prepared according to this method through the difference between the growth rates of the group III nitride semiconductors in the +c-axis direction and the −c-axis direction.
- The foregoing and other objects, features and effects of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings.
-
FIG. 1 is a schematic sectional view of a CAVET according to an embodiment of the present invention. -
FIGS. 2A to 2D are schematic sectional views successively showing the steps for producing the CAVET shown inFIG. 1 . -
FIG. 3 is a schematic sectional view of a conventional CAVET. -
FIG. 1 is a schematic sectional view of a CAVET according to an embodiment of the present invention. - This CAVET (Current Aperture Vertical Electron Transistor) is a kind of HEMT (High Electron Mobility Transistor) employing two-dimensional electron gas resulting from a semiconductor heterojunction as a current channel, and used as a low-noise amplifier loaded on an antenna for receiving satellite broadcasting, a car navigation system or the like, for example.
- Referring to
FIG. 1 , the CAVET includes an n+-type GaN substrate 1 (semiconductor base layer), an insulating film 2 (insulating layer) formed on aprincipal plane 1 a of this n+-type GaN substrate 1 with anaperture 3 partially exposing theprincipal plane 1 a, and a nitride semiconductormultilayer structure portion 4 formed on a region extending onto the insulatingfilm 2 from theaperture 3 of the insulatingfilm 2. - The
principal plane 1 a of the n+-type GaN substrate 1 is defined by a nonpolar plane or a semipolar plane, more specifically, a nonpolar plane such as an m-plane (10-10) or an a-plane (11-20) or asemipolarplanesuch as (10-13), (10-11) or (11-22). This plane orientation is selected in response to the types of group III nitride semiconductors crystal-grown from theprincipal plane 1 a. According to this embodiment, theprincipal plane 1 a of the n+-type GaN substrate 1 is defined by an m-plane. The n+-type GaN substrate 1 has a high n-type impurity concentration of 1×10 cm−3to 5×1018 cm−3,for example. - The insulating
film 2 is in the form of a plurality of (two inFIG. 1 ) stripes extending in the a-axis direction, and these stripes hold theaperture 3 partially exposing theprincipal plane 1 a of the n+-type GaN substrate 1 therebetween. - The insulating
film 2 can be prepared from an oxide, a nitride or an oxynitride such as SiO2 (silicon oxide), Ga2O3 (gallium oxide), MgO (magnesiumoxide), Sc2O3 (scandium oxide), SiN (silicon nitride), SiON (silicon oxynitride) or the like, for example. Among these materials, SiO2 is employed in this embodiment. When the insulatingfilm 2 is prepared from an oxide, a nitride or an oxynitride, stress on the group III nitride semiconductors grown from theprincipal plane 1 a of the n+-type GaN substrate 1 can be controlled. Therefore, cracks in the group III nitride semiconductors can be suppressed. Further, the insulatingfilm 2 can be relatively easily formed by lithography or etching. - The thickness of the insulating
film 2 is 50 nm to 500 nm, for example. This thickness is preferably changed to the optimum value in response to the area of theaperture 3 or the thickness of an n−-type GaN layer 5 described later. The opening width of the aperture 3 (width in the c-axis direction) is 1 μm to 10 μm, for example. - The nitride semiconductor
multilayer structure portion 4 has an upper wall parallel to the principal plane la of the n+-type GaN substrate 1 and sidewalls of the +c-axis side and the −c-axis side inclined with respect to theprincipal plane 1 a on the region extending onto the insulatingfilm 2 from theaperture 3 of the insulatingfilm 2. The nitride semiconductormultilayer structure portion 4 is mesa-shaped in sectional view. - In plan view, on the other hand, the nitride semiconductor
multilayer structure portion 4 is in the form of stripes extending in the a-axis direction, similarly to the insulatingfilm 2. In this nitride semiconductormultilayer structure portion 4, the surface of the upper wall forms aparallel surface 7 parallel to theprincipal plane 1 a, the surface of the sidewall on the +c-axis side forms a +c-axis side inclined surface 8 (first inclined surface), and the surface of the sidewall on the −c-axisside forms a −c-axis side inclined surface 9 (second inclined surface). The +c-axis side inclinedsurface 8 and the −c-axis side inclinedsurface 9 inclined with respect to theprincipal plane 1 a (m-plane) are defined by semipolar planes such as (10-13), (10-11) or (11-22), for example. - More specifically, the nitride semiconductor
multilayer structure portion 4 includes the n -type GaN layer 5 and an n+-type AlGaN layer 6 having a different lattice constant from the n−-type GaN layer 5. - The n−-type GaN layer 5 and the n+-type AlGaN layer 6 are laminated in this order through an
interface 15 parallel to the parallel surface 7 (m-plane), the +c-axis side inclinedsurface 8 and the −c-axis side inclinedsurface 9 of the nitride semiconductormultilayer structure portion 4. In other words, the lower n−-type GaN layer 5 is mesa-shaped in section, with an upper wall parallel to the upper wall of the nitride semiconductormultilayer structure portion 4 and sidewalls parallel to the sidewalls of the +c-axis side and the −c-axis side. - On the other hand, the upper n+-type AlGaN layer 6 has an upper wall in contact with the upper wall of the n−-type GaN layer 5 and sidewalls in contact with the sidewalls of the n−-type GaN layer 5. Further, the n+-type AlGaN layer 6 forms the outermost layer of this multilayer structure, and hence the surface (upper surface) of the upper wall and the surfaces (side surfaces) of the sidewalls thereof form the parallel surface 7 (m-plane), the +c-axis side inclined
surface 8 and the −c-axis side inclinedsurface 9 of the nitride semiconductormultilayer structure portion 4 respectively. - The thickness of the n−-type GaN layer 5 is 1 μm to 2 μm, for example. On the other hand, the thickness (in the m-axis direction) of the upper wall of the n+-type AlGaN layer 6 is 10 nm to 30 nm, for example. The thickness of the sidewall on the +c-axis side is 10 nm to 30 nm, for example. The thickness of the sidewall on the −c-axis side is 10 nm to 30 nm, for example.
- In the nitride semiconductor
multilayer structure portion 4, a portion of the interface 15 (GaN/AlGaN interface) between the n−-type GaN layer 5 and the n+-type AlGaN layer 6 on the −c-axis side is positioned closer to theaperture 3 than a portion on the +c-axis side. More specifically, the distance L1 between the lower end of the portion of theinterface 15 on the +c-axis side in the m-axis direction and an end of theaperture 3 of the insulatingfilm 2 on the +c-axis side is larger than the distance L2 between the lower end of the portion of theinterface 15 on the −c-axis side in the m-axis direction and an end of theaperture 3 of the insulatingfilm 2 on the −c-axis side. The distances L1 and L2 are 1 μm to 100 μm and 0.1 μm to 10 μm respectively, for example. These distances L1 and L2 are properly selected in response to the types of the group III nitride semiconductors constituting the nitride semiconductormultilayer structure portion 4. - In the n−-type GaN layer 5, two-dimensional electron gas 14 (2DEG) is formed around the interface 15 (GaN/AlGaN interface). This two-dimensional electron gas 14 results from the heterojunction of the n−-type GaN layer 5 and the n+-type AlGaN layer 6, and is present generally over a region of the n−-type GaN layer 5 around the
interface 15 in the nitride semiconductormultilayer structure portion 4. In this CAVET, this two-dimensional electron gas 14 is employed as a current channel. The two-dimensional electron gas 14 has a concentration of about 1013 cm−2 in a portion parallel to the c-plane when the Al composition in the n+-type AlGaN layer 6 is 20%, for example. - A
source electrode 11 is formed in contact with the upper wall (upper surface) of the n+-type AlGaN layer 6. - The
source electrode 11 is so formed as to attain ohmic contact between the same and the n+-type AlGaN layer 6, and electrically connected to the two-dimensional electron gas 14 through the n+-type AlGaN layer 6 and the n−-type GaN layer 5. The source electrode 11 can be constituted of a multilayer structure of Ti/Al (lower layer/upper layer), for example. When the lower layer of the multilayer structure is made of Ni, thesource electrode 11 can be excellently brought into ohmic contact with the n+-type AlGaN layer 6 by a treatment such as thermal alloying (annealing), for example. - A
gate electrode 10 is formed on the −c-axis side inclinedsurface 9, a portion of the upper wall of the n+-type AlGaN layer 6 opposed to theaperture 3 of the insulatingfilm 2 and an edge portion of the insulatingfilm 2 closer to the −c-axis side inclinedsurface 9, to be opposed thereto. Thegate electrode 10 can be made of a conductive material such as Pt (platinum), Al (aluminum), Ni/Au (alloy of nickel and gold), Ni/Ti/Au (alloy of nickel, titanium and gold), Pd/Au (alloy of palladium and gold), Pd/Ti/Au (alloy of palladium, titanium and gold), Pd/Pt/Au (alloy of palladium, platinum and gold) or polysilicon, for example. - A
drain electrode 12 is formed in contact with the back surface of the n+-type GaN substrate 1 opposite to theprincipal plane 1 a, to entirely cover the back surface. Thedrain electrode 12 is electrically connected with the n+-type GaN substrate 1. Thedrain electrode 12 can be constituted of a multilayer structure of Ti/Al (layer closer to the n+-type GaN substrate 1/layer farther from the n+-type GaN substrate 1), for example. - A
passivation film 13 made of SiN is formed on the surfaces of the nitride semiconductormultilayer structure portion 4 and the insulatingfilm 2, to entirely cover these surfaces. - The operation of the CAVET is now described. In this CAVET, the sidewall on the −c-axis side of the n+-type AlGaN layer 6 has the thickness of 10 nm to 30 nm, for example, whereby a depletion layer spreads from the
gate electrode 10 up to a region shown by broken slant lines B inFIG. 1 . Therefore, the part of the two-dimensional electron gas 14 closer to the −c-axis side inclinedsurface 9 is pinched off. Further, the distance L1 is larger than the distance L2 and the n−-type GaN layer 5 is a high-resistance layer, whereby electrons in the part of the two-dimensional electron gas 14 closer to the +c-axis side inclinedsurface 8 do not move in the n−-type GaN layer 5 to flow into n+-type GaN substrate 1. - Therefore, the source and the drain are cutoff from each other. In order to operate the CAVET, a bias voltage positive on the drain side is applied between the source and the drain. In other words, a bias voltage of not less than a prescribed value (gate threshold voltage) positive with reference to the potential of the
source electrode 11 is applied to thegate electrode 10 from this state, whereby the two-dimensional electron gas 14 is released from the pinch-off state, and a current flows in a direction shown by solid arrow D inFIG. 1 . More specifically, the two-dimensional electron gas 14 released from the pinch-off state so moves that electrons reach a portion around an edge portion of theaperture 3 of the insulatingfilm 2 closer to the −c-axis side inclinedsurface 9. The electrons reaching the portion around the edge portion of theaperture 3 of the insulatingfilm 2 closer to the −c-axis side inclinedsurface 9 flow in the portion of the n−-type GaN layer 5 located in theaperture 3 to flow into the n+-type GaN substrate 1, due to the potential of thedrain electrode 12. - Then, the electrons reach the
drain electrode 12 through the n+-type GaN substrate 1, to allow the source and the drain to conduct. Thus, the source and the drain are allowed to conduct when a bias voltage is applied to thegate electrode 10 while the source and the drain are cut off from each other when no bias voltage is applied to thegate electrode 10, to achieve a normally-off operation. -
FIGS. 2A to 2D are schematic sectional views successively showing the steps for producing the CAVET shown inFIG. 1 . - In order to produce this CAVET, an insulating film made of SiO2 is first formed on the overall
principal plane 1 a of the n+-type GaN substrate 1 by PECVD (Plasma Enhanced Chemical Vapor Deposition), for example. Then, a photoresist film having an opening corresponding to theaperture 3 is formed on the insulating film by well-known photolithography. Then, the insulating film is dry-etched through the photoresist film serving as a mask, whereby theaperture 3 is formed in the insulating film and the insulatingfilm 2 is formed as the stripes extending in the a-axis direction, as shown inFIG. 2A . - Then, group III nitride semiconductors are epitaxially grown from the
principal plane 1 a of the n+-type GaN substrate 1 partially exposed from theaperture 3 by the so-called ELO (Epitaxial Lateral Overgrowth). - The group III nitride semiconductors can be grown by MOCVD (Metal Organic Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy), VPE (Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy) or the like, for example.
- More specifically, n−-type GaN is first grown from the
principal plane 1 a of the n+-type GaN substrate 1. This n−-type GaN is first grown on the region in theaperture 3 of the insulatingfilm 2 under conditions (growth temperature of 1000° C. to 1100° C. and growth pressure of 30 Torr to 300 Torr, for example) facilitating growth in the m-axis direction. Thereafter, the n−-type GaN is grown on the region extending onto the insulatingfilm 2 from theaperture 3 in the m-axis direction and the c-axis direction under conditions (growth temperature of 950° C. to 1050° C. and growth pressure of 300 Torr to 760 Torr, for example) facilitating growth in the c-axis direction. In the c-axis direction, n−-type GaN is grown in the +c-axis direction and the −c-axis direction through theaperture 3 extending in the a-axis direction. - The growth of n−-type GaN is continued until the grown n−-type GaN is mesa-shaped in sectional view with an upper wall parallel to the
principal plane 1 a of the n+-type GaN substrate 1 and sidewalls of the +c-axis side and the −c-axis side inclined with respect to theprincipal plane 1 a on the region of the insulatingfilm 2. - Thus, the n−-type GaN layer 5 extending onto the insulating
film 2 from theaperture 3 is formed as shown inFIG. 2B . Thereafter n+-type AlGaN is grown from the surface of the n−-type GaN layer 5. This n+-type AlGaN is grown in the m-axis direction and the c-axis direction similarly to the n−-type GaN, and the growth thereof is stopped when the grown n+-type AlGaN is mesa-shaped in sectional view with an upper wall parallel to theprincipal plane 1 a of the n+-type GaN substrate 1 and sidewalls of the +c-axis side and the −c-axis side inclined with respect to theprincipal plane 1 a on the region of the insulatingfilm 2. - Thus, the n+-type AlGaN layer 6 is formed on the n−-type GaN layer 5, thereby forming the nitride semiconductor
multilayer structure portion 4 having theparallel surface 7 parallel to theprincipal plane 1 a of the n+-type GaN substrate 1, the +c-axis side inclinedsurface 8 and the −c-axis side inclinedsurface 9. Si, for example, may be employed as an n-type impurity for growing the n−-type GaN and the n+-type AlGaN. - Comparing the growth rates in the +c-axis direction and the −c-axis direction with each other in relation to epitaxy of a group III nitride semiconductor, the former is higher than the latter. On the region of the insulating
film 2, therefore, the n−-type GaN and the n+-type AlGaN are grown up to positions farther from theaperture 3 in the +c-axis direction, as compared with the −c-axis direction. In the nitride semiconductormultilayer structure portion 4 formed by epitaxy, therefore, the portion of the interface 15 (GaN/AlGaN interface) between the n−-type GaN layer 5 and the n+-type AlGaN layer 6 on the −c-axis side can be positioned closer to theaperture 3 than the portion on the +c-axis side. - Then, the
source electrode 11 is formed on the upper wall (upper surface) of the n+-type AlGaN layer 6, as shown inFIG. 2C . In order to form thesource electrode 11, a photoresist film (not shown) having an aperture in a region for forming thesource electrode 11 is formed by well-known photolithography. Then, metals (Ti and Al, for example) employed as the materials for thesource electrode 11 are sputtered from above this photoresist film in the order of Ti and Al. Thereafter the photoresist film is removed, thereby lifting off unnecessary portions (other than the source electrode 11) of the metals along with the photoresist film. Thesource electrode 11 is formed in contact with the upper wall (upper surface) of the n+-type AlGaN layer 6 through these steps. After the formation of thesource electrode 11, thermal alloying (annealing) is so performed that thesource electrode 11 and the n+-type AlGaN layer 6 are in ohmic contact with each other. - Then, a photoresist film (not shown) having an aperture in a region for forming the
gate electrode 10 is formed by well-known photolithography. Then, a metal (the aforementioned conductive material, for example) employed as the material for thegate electrode 10 is sputtered from above this photoresist film. Thereafter the photoresist film is removed, thereby lifting off unnecessary portions (other than the gate electrode 10) of the metal along with the photoresist film. Thegate electrode 10 opposed to the −c-axis side inclinedsurface 9, the portion of the upper wall of the n+-type AlGaN layer 6 opposed to theaperture 3 of the insulatingfilm 2 and the edge portion of the insulatingfilm 2 closer to the −c-axis side inclinedsurface 9 is formed through these steps, as shown inFIG. 2C . - Thereafter an insulating film made of SiN is formed to cover the overall surface of the structure provided on the n+-
type GaN substrate 1. This insulating film is formed by ECR (Electron Cyclotron Resonance) sputtering, for example. Then, contact holes exposing thesource electrode 11 and thegate electrode 10 respectively are formed in the insulating film. These contact holes are formed by dry etching with the aforementioned etching gas, for example. Due to the formation of these contact holes, the insulating film of SiN forms thepassivation film 13 covering the overall surfaces of the nitride semiconductormultilayer structure portion 4 and the insulatingfilm 2, as shown inFIG. 2D . - Then, the
drain electrode 12 is formed in contact with the overall back surface of the n+-type GaN substrate 1 opposite to the principal plane la, as shown inFIG. 2D . After the formation of thedrain electrode 12, thermal alloying (annealing) is so performed that thedrain electrode 12 and the n+-type GaN substrate 1 are in ohmic contact with each other. The CAVET having the structure shown inFIG. 1 can be obtained in this manner. The two-dimensional electron gas 14 results from the heterojunction between the n−-type GaN layer 5 and the n+-type AlGaN layer 6, and hence the description thereof is omitted in relation to the steps shown inFIGS. 2A to 2D . - According to this embodiment, as hereinabove described, a CAVET capable of a normally-off operation can be implemented. Further, the
principal plane 1 a of the n+-type GaN substrate 1 is defined by the m-plane (nonpolar plane), and hence threading dislocations (spiral dislocations, for example) in the c-axis direction present in the n+-type GaN substrate 1 extend parallelly to theprincipal plane 1 a. When the n−-type GaN is grown in the m-axis direction in the region in theaperture 3 of the insulatingfilm 2, therefore, transfer of the through locations from the n+-type GaN substrate 1 to the n−-type GaN can be suppressed. Therefore, the threading dislocations in the n+-type GaN substrate 1 can be prevented from generating a leakage current flowing to the nitride semiconductormultilayer structure portion 4, whereby the device characteristics of the CAVET can be improved. Particularly when theprincipal plane 1 a of the n+-type GaN substrate 1 is defined by the m-plane as in this embodiment, transfer of the threading dislocations to the nitride semiconductormultilayer structure portion 4 can be further suppressed. - Further, the −c-axis side inclined
surface 9 is defined by the semipolar plane such as (10-13), (10-11) or (11-22) inclined with respect to theprincipal plane 1 a (m-plane) of the n+-type GaN substrate 1. Therefore, the surface parallel to the −c-axis side inclinedsurface 9 is polarized. Thus, the part, serving as the current channel in this CAVET, of the two-dimensional electron gas 14 along the −c-axis side inclinedsurface 9 can be inhibited from reduction in electron density. Consequently, the CAVET can be inhibited from reduction in channel mobility. - In this CAVET, in addition, the
passivation film 13 made of SiN is so formed as to cover the overall surfaces of the nitride semiconductormultilayer structure portion 4 and the insulatingfilm 2. Thus, surface charge in the nitride semiconductormultilayer structure portion 4 can be suppressed by forming thepassivation film 13 in contact with the surface of the nitride semiconductormultilayer structure portion 4. Consequently, the quantity of trap levels on the surface of the nitride semiconductormultilayer structure portion 4 can be reduced, whereby current collapse can be suppressed. - While the embodiment of the present invention has been described, the present invention may be embodied in other ways.
- For example, the two-dimensional electron gas 14 may be formed on an i-type GaN layer containing no impurity, in place of the n−-type GaN layer 5.
- The nitride semiconductor
multilayer structure portion 4 may not have the GaN/AlGaN interface, so far as the same includes two types of group III nitride semiconductor layers at least having different lattice constants with an interface forming the two-dimensional electron gas 14. The nitride semiconductormultilayer structure portion 4 may have the other layers of group III nitride semiconductor on two types of group III nitride semiconductor layers at least having different lattice constants with an interface. - The source electrode 11 may have another structure, so far as the same is electrically connected with the two-dimensional electron gas 14. When the nitride semiconductor
multilayer structure portion 4 includes group III nitride semiconductor layers other than the n-type GaN layer 5 and the n+-type AlGaN layer 6, for example, thesource electrode 11 may be formed on either one of the upper walls (upper surfaces) of the group III nitride semiconductor layers parallel to theprincipal plane 1 a of the n+-type GaN substrate 1. - The
gate electrode 10 may be formed through a gate insulating film made of SiN or the like. Thus, the CAVET has the so-called MIS (Metal Insulator Semiconductor) structure. When the CAVET has the MIS structure, surface charge (interface charge) around the interface between the nitride semiconductormultilayer structure portion 4 and SiN can be suppressed, whereby current collapse as well as generation of a leakage current can be suppressed. - The n+-
type GaN substrate 1 may be replaced with a substrate such as an InN (nitride indium) substrate, for example, consisting of a conductive group III nitride semiconductor. - The −c-axis side inclined
surface 9 can be defined by a −c-plane by employing an n+-type GaN substrate having a principal plane defined by a semipolar plane and growing a group III nitride semiconductor from this principal plane. When the −c-axis side inclinedsurface 9 is defined by a −c-plane, the electron density of the part of the two-dimensional electron gas 14 along the −c-axis side inclinedsurface 9 can be more increased, whereby a CAVET having excellent channel mobility can be implemented. - In the n+-type AlGaN layer 6, the Al composition may be uniform, or portions having different Al compositions may be distributed.
- While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit ad scope of the present invention are to be limited only by the appended claims.
- This application corresponds to Japanese Patent Application No. 2007-208389 filed in the Japanese Patent Office on Aug. 9, 2007, the disclosure of which is incorporated herein by reference in its entirety.
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US12/222,462 Active 2029-12-07 US8134180B2 (en) | 2007-08-09 | 2008-08-08 | Nitride semiconductor device with a vertical channel and method for producing the nitride semiconductor device |
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US20090321854A1 (en) * | 2006-08-24 | 2009-12-31 | Hiroaki Ohta | Mis field effect transistor and method for manufacturing the same |
US20100078688A1 (en) * | 2007-01-26 | 2010-04-01 | Rohm Co., Ltd | Nitride semiconductor device, nitride semiconductor package, and method for manufacturing nitride semiconductor device |
US20100279493A1 (en) * | 2009-04-30 | 2010-11-04 | Kishore Kamath | Doping of semiconductor layer for improved efficiency of semiconductor structures |
US20100314695A1 (en) * | 2009-06-10 | 2010-12-16 | International Rectifier Corporation | Self-aligned vertical group III-V transistor and method for fabricated same |
EP2549528B1 (en) * | 2010-03-19 | 2018-12-19 | Fujitsu Limited | Compound semiconductor device and method for fabricating the same |
US8969912B2 (en) | 2011-08-04 | 2015-03-03 | Avogy, Inc. | Method and system for a GaN vertical JFET utilizing a regrown channel |
WO2013020061A1 (en) * | 2011-08-04 | 2013-02-07 | Avogy, Inc. | Method and system for a gan vertical jfet utilizing a regrown gate |
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CN103035707A (en) * | 2013-01-04 | 2013-04-10 | 电子科技大学 | Super-junction vertical gallium nitride based nitride heterojunction field effect transistor |
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US10325997B2 (en) | 2013-07-15 | 2019-06-18 | Hrl Laboratories, Llc | Vertical III-nitride semiconductor device with a vertically formed two dimensional electron gas |
US20150187599A1 (en) * | 2013-12-30 | 2015-07-02 | Electronics And Telecommunications Research Institute | Methods of manufacturing nitride semiconductor devices |
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US9799726B1 (en) | 2015-06-18 | 2017-10-24 | Hrl Laboratories, Llc | Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas |
US9601610B1 (en) | 2015-06-18 | 2017-03-21 | Hrl Laboratories, Llc | Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas |
US10418475B2 (en) * | 2016-11-28 | 2019-09-17 | Arizona Board Of Regents On Behalf Of Arizona State University | Diamond based current aperture vertical transistor and methods of making and using the same |
CN107154435A (en) * | 2017-03-29 | 2017-09-12 | 西安电子科技大学 | Grading current barrier layer vertical-type power device |
CN111354777A (en) * | 2018-12-24 | 2020-06-30 | 东南大学 | Heterojunction semiconductor device with low on-resistance |
TWI768222B (en) * | 2019-07-17 | 2022-06-21 | 世界先進積體電路股份有限公司 | Semiconductor device and manufacturing method of the same |
CN112310189A (en) * | 2019-07-26 | 2021-02-02 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
US11251264B2 (en) | 2019-10-08 | 2022-02-15 | Vanguard International Semiconductor Corporation | Semiconductor device and manufacturing method of the same |
US20230078017A1 (en) * | 2021-09-16 | 2023-03-16 | Wolfspeed, Inc. | Semiconductor device incorporating a substrate recess |
CN114520262A (en) * | 2022-02-17 | 2022-05-20 | 电子科技大学 | Enhanced MIS-GaN device |
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US8134180B2 (en) | 2012-03-13 |
JP2009044006A (en) | 2009-02-26 |
JP5208463B2 (en) | 2013-06-12 |
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