US20070079167A1 - Clock domain crossing - Google Patents
Clock domain crossing Download PDFInfo
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- US20070079167A1 US20070079167A1 US11/241,581 US24158105A US2007079167A1 US 20070079167 A1 US20070079167 A1 US 20070079167A1 US 24158105 A US24158105 A US 24158105A US 2007079167 A1 US2007079167 A1 US 2007079167A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
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- FIG. 1 shows an example of a known device 10 having logic circuitry 12 which is synchronized by a clock signal A.
- the device 10 may also have additional logic circuitry 14 which is synchronized by a clock signal B which may be at a different frequency than that of clock signal A.
- the logic circuitry 12 , 14 can be said to operate in different clock domains, here, clock A domain and clock B domain, respectively.
- a device such as device 10 may have separate clock domains for a variety reasons. For example, if the device 10 is part of a portable, battery operated device, the clock signal A may have a frequency substantially lower than that of clock signal B. Hence, logic circuitry 12 may, in some applications, be operated at a reduced power level as compared to logic circuitry 14 , to extend effective battery time.
- FIGS. 2 a and 2 b are timing diagrams illustrating a sequence of data words, Word 0 , Word 1 , . . . Wordn loaded into the register 16 .
- the register 16 is in the clock A domain, the register 16 is clocked by the clock signal A.
- each data word is available for a full period of clock signal A as shown in FIGS. 2 a , 2 b.
- a data word provided by the register 16 of the clock A domain may be loaded by a register 18 of the clock B domain.
- the register 18 is in the clock B domain, the register 18 is clocked by the clock signal B.
- the clock signal B has exactly twice the frequency of clock signal A.
- the period of the clock signal A is an integral multiple of (here two times) the period of the clock signal B. Accordingly, if the register 18 is triggered to load data from the register 16 on the leading edge 20 , for example, of the clock signal B, a data word may be loaded from the register 16 on the leading edge of each clock signal A, as indicated by dashed lines 22 in FIG. 2 a .
- a data word may be loaded from the register 16 on the trailing edge of each clock signal A as indicated by dashed lines 26 in FIG. 2 a.
- FIG. 2 b shows another example in which the period of the clock signal A is not an integral multiple of the period of the clock signal B.
- the period of the clock signal A is 5/3 that of the clock signal B.
- the cycle repeats such that at dashed line 30 n, the point within the clock signal A at which the data word is loaded into the register 18 is the same as that of the dashed line 30 a.
- the cycle is fifteen times the period of the clock B.
- FIG. 1 is a prior art example of a clock domain crossing circuit.
- FIGS. 2 a and 2 b are timing diagrams illustrating operation of a prior art clock domain crossing circuit at various frequencies.
- FIG. 3 is a schematic diagram illustrating one environment which may utilize a clock domain crossing circuit in accordance with one embodiment of the description provided herein.
- FIG. 4 illustrates one example of operations of a clock domain crossing circuit in accordance with one embodiment of the description provided herein.
- FIG. 5 is a schematic diagram of a clock domain crossing circuit in accordance with one embodiment of the description provided herein.
- FIG. 6 is a more detailed schematic diagram of a portion of the clock domain crossing circuit of FIG. 5 .
- FIG. 7 is a timing diagram illustrating operation of one embodiment of the parallel to serial converter circuit of FIG. 6 .
- FIG. 8 is a chart illustrating operation of one embodiment of the parallel to serial converter circuit of FIG. 6 .
- FIG. 3 illustrates one example of a computing environment which may be used with the described embodiments.
- a computer 102 includes a processor 104 (such as one or more central processing units (CPU)), a basic input/output system (BIOS) 106 including code executed by the processor 104 to initialize and control various computer 102 components (e.g., the keyboard, display screen, disk drives, serial communications, etc.) during a boot sequence.
- the computer 102 includes a memory 108 , comprising one or more volatile memory devices, such as volatile random access memory (RAM), in which an operating system 110 and one or more drivers 112 , such as a device driver interfacing with an attached device 114 , are loaded into the memory 108 implementing a runtime environment.
- the memory 8 may further include nonvolatile memory (e.g., a flash memory, Electronically Erasable Programmable Memory (EEPROM), optical disk drives, magnetic disk drives etc.)
- the device 114 may comprise any type of Input/Output (I/O) device internal or external to a housing of the computer 102 , such as a hard disk drive, or a video chipset, which may be integrated on the computer 102 motherboard or on an expansion card inserted in an expansion slot on the computer 102 motherboard.
- the BIOS 106 may be implemented in firmware in a non-volatile memory device on the computer 102 motherboard, such as a Flash memory, Read Only Memory (ROM), Programmable ROM (PROM), etc.
- the BIOS 106 code indicates the sequence of the boot operations.
- the operating system 110 may comprise a suitable operating system, such as a Microsoft® Windows® operating system, LinuxTM, Apple® Macintosh®, etc.
- the computer 102 may comprise any computing device known in the art, such as a mainframe, server, personal computer, workstation, laptop, handheld computer, telephony device, network appliance, virtualization device, storage controller, network controller, etc. Any suitable CPU or processor 104 and operating system may be used.
- one or more of the devices of a system may include a clock domain crossing circuit 120 to facilitate transferring data from one clock domain to another.
- the memory 108 may include a clock domain crossing circuit 120 within the memory 108 to facilitate transferring data from one clock domain to another clock domain within the memory 108 .
- the clock domain crossing circuit 120 may be implemented on a dynamic random access memory (DRAM) monolithic integrated circuit chip, for example.
- the processor 104 may similarly have a clock domain crossing circuit 120 to facilitate the transfer of data from one clock domain of the processor 104 to another clock domain within the processor 104 .
- the clock domain crossing circuit 120 of the processor 104 may be implemented on a microprocessor monolithic integrated circuit chip, for example.
- the device 114 may have a clock domain crossing circuit 120 to facilitate the transfer of data from one clock domain of the device 114 to another clock domain within the device 114 .
- the clock domain crossing circuit 120 of the device 114 may be implemented on an integrated circuit chip, for example. It is appreciated that a system may have as few as one and as many as several such clock domain crossing circuits.
- the clock domain crossing circuit 120 may be implemented on a single monolithic integrated circuit chip, or may span a plurality of monolithic integrated circuit chips.
- FIG. 4 illustrates one example of operations to effectuate a transfer of data from one clock domain to another, in accordance with one aspect of the description provided herein.
- bits of data to be transferred are shifted (block 150 , FIG. 4 ) in the first clock domain.
- FIG. 5 shows an example of a clock domain crossing circuit 120 which shifts bits of data to be transferred to another clock domain.
- shifted bits of data to be transferred may be sampled (block 152 , FIG. 4 ) in a second clock domain at a fixed time within each clock signal of the first clock domain.
- FIGS. 5-8 show one example in which shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain.
- a stream of sampled bits may be output (block 154 , FIG. 4 )) in the second clock domain.
- FIGS. 5-8 show one example in which a stream of sampled bits may be output in a second clock domain.
- FIG. 5 data to be transferred from a first clock domain, designated clock A domain in this example, to a second clock domain, designated clock B domain, in this example, is provided by a logic circuit 202 which is clocked by clock A of the clock A domain. Bits of data to be transferred are shifted by a shifter circuit 204 and stored in a register 206 .
- FIG. 6 shows an example of a register 206 which includes 12 flip-flops having 12 outputs, R 0 , R 1 , . . . R 11 , respectively. It is appreciated that the register 206 may be formed of a variety of temporary storage devices and may include more or fewer bit positions, depending upon the particular application.
- each word of data to be transferred includes 9 bits, bits 0 , 1 , 2 . . . 8 . These bits are shifted and loaded, together with three don't care bits (each designated “X”) in the flip-flops of the register 206 .
- the outputs of the 12 flip-flops of the register 206 are designed R 0 , R 1 , R 2 . . . R 11 .
- Table 1 below indicates one example in which bits of a data word to be transferred may be shifted by the shifter 204 and loaded into the register 206 . It is appreciated that the manner in which transfer bits are shifted may vary, depending upon the particular application.
- a new word to be transferred is presented each cycle of clock A of the clock A domain.
- Table 1 four successive clock A cycles are designated clock A cycle 0 , clock A cycle 1 , clock A cycle 2 and clock A cycle 3 .
- the shifter 204 shifts bit 7 of the transfer word of clock A cycle 0 and loads it in the R 11 output of the register 206 .
- the shifter 204 shifts bit 3 of the transfer word of clock A cycle 0 and loads it in the R 10 output of the register 206 and so on as indicated in Table 1.
- Don't cares (designated “X”) are loaded in the R 9 , R 7 and R 5 outputs for the transfer word of the clock A cycle 0 .
- the shifting function is performed by a barrel shifter 210 ( FIG. 6 ) of the shifter circuit 204 ( FIG. 5 ). It is appreciated that a variety of techniques and devices may be used to perform the bit shifting function. These include dedicated hardwired circuits, firmware, software, general purpose processors, ASICs, etc. Shifting techniques other than barrel shifting may be utilized as well, depending upon the particular application. Furthermore, the data bit shifting indicated by Table 1 provides but one example of suitable bit shifting in accordance with the present description. It is appreciated that other bit shifting schemes may be utilized, depending upon the particular application.
- bits of data to be transferred may be sampled (block 152 , FIG. 4 ) in a second clock domain at a fixed time within each clock signal of the first clock domain.
- FIG. 7 shows one example of sampling bits of data to be transferred at a fixed time within each clock signal of the first clock domain, that is, clock domain A, in this example.
- bits are sampled at three fixed times within each cycle of clock A, as indicated by three vertical lines 214 a, 214 b, 214 c.
- the bits of word 0 are sampled at the same three times 214 a, 214 b, 214 c within clock cycle 0 that bits are sampled from word 1 during clock A cycle 1 and so on.
- the clock signal A has a period of 9 unit intervals (UI) and the clock signal B has a period of 4 unit intervals.
- the period of the clock A is 9/4 times that of the period of the clock B and the,period of the clock B is 4/9 times that of the clock A.
- the clock domain crossing features described herein are applicable to a variety of different clocks including those in which neither period is an integral multiple of the other period such as those shown in FIG. 7 , for example.
- the relative lengths of the clock signals may vary, depending upon the particular application.
- FIG. 5 shows one example of a circuit for sampling bits of data in the second clock domain of clock B at a fixed time within each clock signal of the first clock domain of clock A.
- the sampling circuit includes a parallel to serial converter 220 which is clocked by clock B of the clock B domain.
- the bits of data sampled from the register 206 are stored in a register 222 .
- FIG. 6 shows an example of a register 222 which includes 12 flip-flops designated A 0 , A 1 , A 2 , B 0 , B 1 , B 2 , C 0 , C 1 , C 2 , D 0 , D 1 , D 2 , respectively.
- the register 222 may be formed of a variety of temporary storage devices and may include more or fewer bit positions, depending upon the particular application.
- Table 2 below indicates one example of the manner in which data bits of the data words being transferred may be sampled and stored in the register 222 .
- TABLE 2 Data bit mapping to converter register in Clock B Domain Bank D Bank C Bank B Bank A Clock A cycle: D0 D1 D2 C0 C1 C2 B0 B1 B2 A0 A1 A2 0 7 3 X 6 X 2 X 5 1 8 4 0 1 6 X 2 X 5 1 8 4 0 7 3 X 2 X 5 1 8 4 0 7 3 X 6 X 2 3 8 4 0 7 3 X 6 X 2 X 5 1
- the flip-flops designated A 0 , A 1 , A 2 , B 0 , B 1 , B 2 , C 0 , C 1 , C 2 , D 0 , D 1 , D 2 , of the register 222 are logically arranged in a four by three array of four banks A, B, C and D, each of which having three flip-flops in three columns, col 1 , col 2 , col 3 .
- Bank A has flip-flops A 0 , A 1 , A 2 ,
- Bank B has flip-flops B 0 , B 1 , B 2 , and so on.
- a new word to be transferred is presented each cycle of clock A of the clock A domain.
- four successive clock A cycles are designated clock A cycle 0 , clock A cycle 1 , clock A cycle 2 and clock A cycle 3 .
- the shifter 204 shifts bit 7 of the transfer word of clock A cycle 0 and loads it in the R 11 output of the register 206 .
- the flip-flop D 0 of the register 222 has an input coupled to the R 11 output of the register 206 . Accordingly, as shown in Table 2, the flip-flop D 0 of the Bank D loads the bit 7 of the transfer word of clock A cycle 0 .
- the parallel to serial converter 220 includes an input multiplexer 224 having an input coupled to the R 10 output of the register 206 and an output coupled to the input of the flip-flop D 1 of the Bank D.
- the flip-flop D 1 of the Bank D loads bit 3 of the transfer word of clock A cycle 0 as indicated in Table 2.
- the remaining flip-flops of the register 222 are coupled to corresponding outputs of the register 206 and load shifted bits as set forth in the Tables 1 and 2.
- FIG. 7 shows one example of outputting a stream 250 of sampled bits in the clock B domain.
- the stream 250 is outputted by the register 222 of the parallel to serial converter 220 .
- the stream 250 comprises bits 0 , 1 , . . . 8 of sampled word 0 , bits 0 , 1 , . . . 8 of sampled word 1 , and so on. It is appreciated that the order of the bits, and the number of bits may vary, depending upon the particular application.
- the parallel to serial converter 220 samples bits of data in the second clock domain of clock B at a fixed time within each clock signal of the first clock domain of clock A. As explained in greater detail below, to output the stream 250 of bits, some bits may be output by the converter 220 after being loaded by the register 222 . Other bits are first shifted within the register 222 before being outputted by the register 222 .
- the input of the flip-flop D 1 of the Bank D is coupled to an input multiplexer 224 having an input coupled to the R 10 output of the register 206 .
- the input multiplexer 224 has another input coupled to the output of the flip-flop D 0 as shown in FIG. 6 .
- the R 10 output of the register 206 can be loaded into the flip-flop D 1
- the output of the flip-flop D 0 may be shifted into the flip-flop D 1 , depending upon the selection of the multiplexer 224 .
- Bits may be loaded into or shifted into the remaining flip-flops of the register 222 using a multiplexer 224 as shown in FIG. 6 .
- FIG. 8 is a chart illustrating one example of a timing sequence by which bits of a word may be sampled and selectively shifted to produce the stream 250 . It is appreciated that other timing sequences may be utilized, depending upon the particular application.
- the four by three array of flip-flops of the register 222 are represented by a four by three array of boxes 260 a having four rows of boxes labeled Bank A, Bank B, Bank C, Bank D, in three columns of boxes labeled col 0 , col 1 , col 2 in the same manner as the flip-flops A 0 , A 1 . . . D 2 of FIG. 6 .
- the flip-flop D 1 for example, is represented in the array 260 a of FIG. 8 by the box in the row labeled Bank D and in the column labeled col 1 .
- the flip-flops A 0 , A 1 , A 2 , B 0 , B 1 , B 2 , C 0 , C 1 , C 2 , D 0 , D 1 , D 2 , of the register 222 are clocked by four phases of the clock B, designated clock B 0°, clock B 90°, clock B 180°clock B 270°which are depicted in FIG. 7 .
- the flip-flop D 0 is clocked by the clock B 90°
- the flip-flop D 1 is clocked by the clock B 0°
- FIGS. 6 and 7 the flip-flops A 0 , A 1 , A 2 , B 0 , B 1 , B 2 , C 0 , C 1 , C 2 , D 0 , D 1 , D 2 , of the register 222 are clocked by four phases of the clock B, designated clock B 0°, clock B 90°, clock B 180°clock B 270°which are depicted in FIG
- the four by three array 260 a of boxes of the chart of FIG. 8 illustrates the loading of bits during the clock B 0°.
- the flip-flop C 0 (Bank C, col 0 ) loads the bit 6 , which is bit 6 of word 0 as indicated in FIG. 7 .
- the loading of bit 6 by flip-flop C 0 is indicated by the box in row BankC, column col 0 in array 260 a of FIG. 8 .
- flip-flops D 1 and A 2 load bits 3 , 0 , respectively during clock A cycle 0 as indicated in Table 2 and FIG. 8 .
- the chart of FIG. 8 comprises a plurality of arrays 260 a, 260 b . . . 260 i similar to the array 260 a.
- the next four by three array 260 b of boxes of the chart of FIG. 8 illustrates the loading of bits during the clock B 90°.
- the flip-flops D 0 , A 1 , B 2 load the bits 7 , 4 , 1 , respectively of word 0 .
- the next four by three array 260 c of boxes of the chart of FIG. 8 illustrates the loading of bits during the clock B 180°.
- the flip-flops A 0 , B 1 , C 2 load the bits 8 , 5 , 2 , respectively, of word 0 .
- outputs of the column col 2 flip-flops that is flip-flops A 2 , B 2 , C 2 , D 2 , may be selected for output to the bit stream 250 .
- bits 0 , 1 , 2 , respectively, of word 0 are available for output on outputs outA, outB, outC ( FIG. 6 ) of the flip-flops A 2 , B 2 , C 2 , respectively.
- the next four by three array 260 d of boxes of the chart of FIG. 8 illustrates the shifting of bits during the clock B 270°.
- the bits 6 , 3 loaded by flip-flops C 0 , D 1 , respectively are shifted to flip-flops C 1 , D 2 , respectively.
- the bit 3 of word 0 is available for output on output outD of flip-flop D 2 .
- the flip-flop B 0 loads a don't care (as indicated by the “X”) in Table 2 and FIGS. 7, 8 , during the clock B 270°.
- the next four by three array 260 e of boxes of the chart of FIG. 8 illustrates the shifting of bits during the clock B 0°.
- the bits 7 , 4 loaded by flip-flops D 0 , A 1 , respectively are shifted to flip-flops D 1 , A 2 , respectively.
- the bit 4 of word 0 is available for output on output outA of flip-flop A 2 .
- the flip-flop C 0 loads a don't care (as indicated by the “X”) in Table 2 and FIGS. 7, 8 , during the clock B 0°.
- the flip-flops D 1 , A 2 loaded bits of word 0 .
- the flip-flops D 1 , A 2 received shifted bits of word 0 .
- the multiplexers 224 coupled to the inputs of the flip-flops D 1 , A 2 are controlled in the illustrated embodiment by a multiplexer select signal multiplexselect 0 which is depicted in FIG. 7 .
- the multiplexer select signal multiplexerselect 0 controls the input multiplexer 224 of the flip-flops which are clocked by the clock signal clock B 0°.
- the multiplexer select signal multiplexerselect 90 controls the input multiplexers 224 of the flip-flops which are clocked by the clock signal clock B 90°.
- the multiplexer select signal multiplexerselect 180 controls the input multiplexers 224 of the flip-flops which are clocked by the clock signal clock B 180°.
- the multiplexer select signal multiplexerselect 270 controls the input multiplexers 224 of the flip-flops which are clocked by the clock signal clock B 270°.
- the flip flops of the columns col 1 , col 2 shift bits of word 0 when clocked by the associated clock clock B 0°, clock B 90°, clock B 180°, or clock B 270°, and the flip-flops of the column col 0 load don't cares.
- outputs of the column col 2 flip-flops A 2 , B 2 , C 2 , D 2 may be selected to output the remaining bits 4 , 5 , . . . 8 for output to the bit stream 250 as shown in FIG. 7 .
- the four by three array 272 a of boxes of the chart of FIG. 8 illustrates the loading of bits during the clock B 90° and clock A cycle 1 .
- the four by three array 272 b of boxes of the chart of FIG. 8 illustrates the loading of bits during the clock B 180°and clock A cycle 1 .
- the four by three array 272 c of boxes of the chart of FIG. 8 illustrates the loading of bits during the clock B 270° and clock A cycle 1 .
- the remaining portion of the chart of FIG. 8 for the clock A cycle 1 , cycle 2 , cycle 3 may be readily determined by reference to Tables 1, 2 and FIGS. 6, 7 .
- the stream 250 sequence of data words, Word 0 , Word 1 , . . . Wordn, which is clocked by clock B of the Clock B Domain, may be utilized and processed by other logic of the Clock B Domain as represented by the logic circuitry 280 which is also clocked by the clock B. Circuitry similar to the clock domain crossing circuit 120 may be employed to transfer data words from the Clock B Domain over to the Clock A Domain.
- an embodiment means “one or more (but not all) embodiments of the present invention(s)” unless expressly specified otherwise.
- the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise.
- the enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.
- the terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise.
- Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise.
- devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.
- the described operations may be implemented as a method, apparatus or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof.
- article of manufacture refers to code or logic implemented in a tangible medium, where such tangible medium may comprise hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.) or a computer readable medium, such as magnetic storage medium (e.g., hard disk drives, floppy disks,, tape, etc.), optical storage (CD-ROMs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, firmware, programmable logic, etc.).
- hardware logic e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.
- a computer readable medium such as magnetic storage medium (e.g., hard disk drives, floppy disk
- Code in the computer readable medium is accessed and executed by a processor.
- the tangible medium in which the code or logic is encoded may also comprise transmission signals propagating through space or a transmission media, such as an optical fiber, copper wire, etc.
- the transmission signal in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc.
- the transmission signal in which the code or logic is encoded is capable of being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a computer readable medium at the receiving and transmitting stations or devices.
- the “article of manufacture” may comprise a combination of hardware and software components in which the code is embodied, processed, and executed. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope of the present description, and that the article of manufacture may comprise any suitable information bearing medium.
- the embodiments may be included in a computer system including nonvolatile memory and a storage controller, such as a SCSI, Integrated Drive Electronics (IDE), Redundant Array of Independent Disk (RAID), etc., controller, that manages access to a non-volatile storage device, such as a magnetic disk drive, tape media, optical disk, etc.
- a storage controller such as a SCSI, Integrated Drive Electronics (IDE), Redundant Array of Independent Disk (RAID), etc.
- RAID Redundant Array of Independent Disk
- controller that manages access to a non-volatile storage device, such as a magnetic disk drive, tape media, optical disk, etc.
- embodiments may be included in a system that does not include nonvolatile memory or a storage controller, such as certain hubs and switches.
- the embodiments may be implemented in a computer system including a video controller to render information to display on a monitor electrically coupled to the computer system including the host software driver and network controller, such as a computer system comprising a desktop, workstation, server, mainframe, laptop, handheld computer, telephone, etc.
- the features described herein may be implemented in a computing device that does not include a video controller, such as a switch, router, etc.
- the devices 114 of the architecture of the system 102 may include a network controller to enable communication with a network, such as an Ethernet, a Fibre Channel Arbitrated Loop, etc. Further, the architecture may, in certain embodiments, include a video controller to render information on a display monitor, where the video controller may be implemented on a video card or integrated on integrated circuit components mounted on the motherboard.
- An input device may be used to provide user input to the processor 104 , and may include a keyboard, mouse, pen-stylus, microphone, touch sensitive display screen, or any other suitable activation or input mechanism.
- An output device may be capable of rendering information transmitted from the processor 104 , or other component, such as a display monitor, printer, storage, etc.
- the embodiments of the present description may be implemented on an expansion card such as a network card, such as a Peripheral Component Interconnect (PCI) card or some other card, or on integrated circuit components mounted on the motherboard.
- a network card such as a Peripheral Component Interconnect (PCI) card or some other card, or on integrated circuit components mounted on the motherboard.
- PCI Peripheral Component Interconnect
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Abstract
Description
- Digital circuits such as microprocessors, memory circuits, busses and other devices are frequently synchronous circuits in which operations may be synchronized by one or more clock signals. A clock signal is typically a periodic signal having a particular frequency.
FIG. 1 shows an example of a knowndevice 10 havinglogic circuitry 12 which is synchronized by a clock signal A. Thedevice 10 may also haveadditional logic circuitry 14 which is synchronized by a clock signal B which may be at a different frequency than that of clock signal A. Thus, thelogic circuitry - A device such as
device 10 may have separate clock domains for a variety reasons. For example, if thedevice 10 is part of a portable, battery operated device, the clock signal A may have a frequency substantially lower than that of clock signal B. Hence,logic circuitry 12 may, in some applications, be operated at a reduced power level as compared tologic circuitry 14, to extend effective battery time. - The circuitry of the various clock domains of a device often do not operate completely independently of the operations of the other clock domains. Thus, data may be transferred from one clock domain to another clock domain. The
device 10 has aregister 16 which may be loaded with data for transfer to the clock B domain.FIGS. 2 a and 2 b are timing diagrams illustrating a sequence of data words, Word0, Word1, . . . Wordn loaded into theregister 16. In that theregister 16 is in the clock A domain, theregister 16 is clocked by the clock signal A. In this example, each data word is available for a full period of clock signal A as shown inFIGS. 2 a, 2 b. - A data word provided by the
register 16 of the clock A domain may be loaded by aregister 18 of the clock B domain. In that theregister 18 is in the clock B domain, theregister 18 is clocked by the clock signal B. In the example ofFIG. 2 a, the clock signal B has exactly twice the frequency of clock signal A. Thus, the period of the clock signal A is an integral multiple of (here two times) the period of the clock signal B. Accordingly, if theregister 18 is triggered to load data from theregister 16 on the leadingedge 20, for example, of the clock signal B, a data word may be loaded from theregister 16 on the leading edge of each clock signal A, as indicated bydashed lines 22 inFIG. 2 a. Alternatively, if theregister 18 is triggered to load data from theregister 16 on the leadingedge 24, for example, of the clock signal B, a data word may be loaded from theregister 16 on the trailing edge of each clock signal A as indicated bydashed lines 26 inFIG. 2 a. -
FIG. 2 b shows another example in which the period of the clock signal A is not an integral multiple of the period of the clock signal B. In this example, the period of the clock signal A is 5/3 that of the clock signal B. If theregister 18 is triggered to load data from theregister 16 on theleading edges register 18, shifts from pulse to pulse as indicated by the series ofdashed lines line 30 n, the point within the clock signal A at which the data word is loaded into theregister 18 is the same as that of thedashed line 30 a. In this example, the cycle is fifteen times the period of the clock B. -
FIG. 1 is a prior art example of a clock domain crossing circuit. -
FIGS. 2 a and 2 b are timing diagrams illustrating operation of a prior art clock domain crossing circuit at various frequencies. -
FIG. 3 is a schematic diagram illustrating one environment which may utilize a clock domain crossing circuit in accordance with one embodiment of the description provided herein. -
FIG. 4 illustrates one example of operations of a clock domain crossing circuit in accordance with one embodiment of the description provided herein. -
FIG. 5 is a schematic diagram of a clock domain crossing circuit in accordance with one embodiment of the description provided herein. -
FIG. 6 is a more detailed schematic diagram of a portion of the clock domain crossing circuit ofFIG. 5 . -
FIG. 7 is a timing diagram illustrating operation of one embodiment of the parallel to serial converter circuit ofFIG. 6 . -
FIG. 8 is a chart illustrating operation of one embodiment of the parallel to serial converter circuit ofFIG. 6 . - In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments. It is understood that other embodiments may be utilized and structural and operational changes may be made without departing from the scope of the descriptions provided.
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FIG. 3 illustrates one example of a computing environment which may be used with the described embodiments. Acomputer 102 includes a processor 104 (such as one or more central processing units (CPU)), a basic input/output system (BIOS) 106 including code executed by theprocessor 104 to initialize and controlvarious computer 102 components (e.g., the keyboard, display screen, disk drives, serial communications, etc.) during a boot sequence. Thecomputer 102 includes amemory 108, comprising one or more volatile memory devices, such as volatile random access memory (RAM), in which anoperating system 110 and one ormore drivers 112, such as a device driver interfacing with an attacheddevice 114, are loaded into thememory 108 implementing a runtime environment. In some applications, thememory 8 may further include nonvolatile memory (e.g., a flash memory, Electronically Erasable Programmable Memory (EEPROM), optical disk drives, magnetic disk drives etc.) - The
device 114 may comprise any type of Input/Output (I/O) device internal or external to a housing of thecomputer 102, such as a hard disk drive, or a video chipset, which may be integrated on thecomputer 102 motherboard or on an expansion card inserted in an expansion slot on thecomputer 102 motherboard. TheBIOS 106 may be implemented in firmware in a non-volatile memory device on thecomputer 102 motherboard, such as a Flash memory, Read Only Memory (ROM), Programmable ROM (PROM), etc. TheBIOS 106 code indicates the sequence of the boot operations. Theoperating system 110 may comprise a suitable operating system, such as a Microsoft® Windows® operating system, Linux™, Apple® Macintosh®, etc. (Microsoft and Windows are registered trademarks of Microsoft Corporation, Apple and Macintosh are registered trademarks of Apple Computer, Inc., and Linux is a trademark of Linus Torvalds). Thecomputer 102 may comprise any computing device known in the art, such as a mainframe, server, personal computer, workstation, laptop, handheld computer, telephony device, network appliance, virtualization device, storage controller, network controller, etc. Any suitable CPU orprocessor 104 and operating system may be used. - In accordance with one aspect of the description provided herein, one or more of the devices of a system such as the
computer 102 may include a clockdomain crossing circuit 120 to facilitate transferring data from one clock domain to another. For example, thememory 108 may include a clockdomain crossing circuit 120 within thememory 108 to facilitate transferring data from one clock domain to another clock domain within thememory 108. The clockdomain crossing circuit 120 may be implemented on a dynamic random access memory (DRAM) monolithic integrated circuit chip, for example. Theprocessor 104 may similarly have a clockdomain crossing circuit 120 to facilitate the transfer of data from one clock domain of theprocessor 104 to another clock domain within theprocessor 104. The clockdomain crossing circuit 120 of theprocessor 104 may be implemented on a microprocessor monolithic integrated circuit chip, for example. Similarly, thedevice 114 may have a clockdomain crossing circuit 120 to facilitate the transfer of data from one clock domain of thedevice 114 to another clock domain within thedevice 114. The clockdomain crossing circuit 120 of thedevice 114 may be implemented on an integrated circuit chip, for example. It is appreciated that a system may have as few as one and as many as several such clock domain crossing circuits. The clockdomain crossing circuit 120 may be implemented on a single monolithic integrated circuit chip, or may span a plurality of monolithic integrated circuit chips. -
FIG. 4 illustrates one example of operations to effectuate a transfer of data from one clock domain to another, in accordance with one aspect of the description provided herein. In one operation, bits of data to be transferred are shifted (block 150,FIG. 4 ) in the first clock domain.FIG. 5 shows an example of a clockdomain crossing circuit 120 which shifts bits of data to be transferred to another clock domain. - In another operation, shifted bits of data to be transferred may be sampled (
block 152,FIG. 4 ) in a second clock domain at a fixed time within each clock signal of the first clock domain.FIGS. 5-8 show one example in which shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. - In another operation, a stream of sampled bits may be output (
block 154,FIG. 4 )) in the second clock domain.FIGS. 5-8 show one example in which a stream of sampled bits may be output in a second clock domain. - Referring to
FIG. 5 , data to be transferred from a first clock domain, designated clock A domain in this example, to a second clock domain, designated clock B domain, in this example, is provided by alogic circuit 202 which is clocked by clock A of the clock A domain. Bits of data to be transferred are shifted by ashifter circuit 204 and stored in aregister 206.FIG. 6 shows an example of aregister 206 which includes 12 flip-flops having 12 outputs, R0, R1, . . . R11, respectively. It is appreciated that theregister 206 may be formed of a variety of temporary storage devices and may include more or fewer bit positions, depending upon the particular application. - In this embodiment, each word of data to be transferred includes 9 bits,
bits register 206. The outputs of the 12 flip-flops of theregister 206 are designed R0, R1, R2 . . . R11. Table 1 below indicates one example in which bits of a data word to be transferred may be shifted by theshifter 204 and loaded into theregister 206. It is appreciated that the manner in which transfer bits are shifted may vary, depending upon the particular application.TABLE 1 Data bit shifting in Clock A Domain Clock A Shifter Register Outputs: cycle: R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Clock A 7 3 X 6 X 2 X 5 1 8 4 0 Cycle 0Clock A 6 X 2 X 5 1 8 4 0 7 3 X Cycle 1 Clock A X 5 1 8 4 0 7 3 X 6 X 2 Cycle 2Clock A 8 4 0 7 3 X 6 X 2 X 5 1 Cycle 3 - In this example, a new word to be transferred is presented each cycle of clock A of the clock A domain. In Table 1, four successive clock A cycles are designated
clock A cycle 0,clock A cycle 1,clock A cycle 2 andclock A cycle 3. Thus, as shown in Table 1 below, theshifter 204 shifts bit 7 of the transfer word ofclock A cycle 0 and loads it in the R11 output of theregister 206. Theshifter 204 shifts bit 3 of the transfer word ofclock A cycle 0 and loads it in the R10 output of theregister 206 and so on as indicated in Table 1. Don't cares (designated “X”) are loaded in the R9, R7 and R5 outputs for the transfer word of theclock A cycle 0. - In the illustrated embodiment, the shifting function is performed by a barrel shifter 210 (
FIG. 6 ) of the shifter circuit 204 (FIG. 5 ). It is appreciated that a variety of techniques and devices may be used to perform the bit shifting function. These include dedicated hardwired circuits, firmware, software, general purpose processors, ASICs, etc. Shifting techniques other than barrel shifting may be utilized as well, depending upon the particular application. Furthermore, the data bit shifting indicated by Table 1 provides but one example of suitable bit shifting in accordance with the present description. It is appreciated that other bit shifting schemes may be utilized, depending upon the particular application. - As previously mentioned, bits of data to be transferred may be sampled (block 152,
FIG. 4 ) in a second clock domain at a fixed time within each clock signal of the first clock domain.FIG. 7 shows one example of sampling bits of data to be transferred at a fixed time within each clock signal of the first clock domain, that is, clock domain A, in this example. As shown inFIG. 7 , bits are sampled at three fixed times within each cycle of clock A, as indicated by threevertical lines clock A cycle 0, the bits ofword 0 are sampled at the same threetimes clock cycle 0 that bits are sampled fromword 1 duringclock A cycle 1 and so on. - In this example, the clock signal A has a period of 9 unit intervals (UI) and the clock signal B has a period of 4 unit intervals. Thus, the period of the clock A is 9/4 times that of the period of the clock B and the,period of the clock B is 4/9 times that of the clock A. It is believed that the clock domain crossing features described herein are applicable to a variety of different clocks including those in which neither period is an integral multiple of the other period such as those shown in
FIG. 7 , for example. Thus, it is appreciated that the relative lengths of the clock signals may vary, depending upon the particular application. -
FIG. 5 shows one example of a circuit for sampling bits of data in the second clock domain of clock B at a fixed time within each clock signal of the first clock domain of clock A. In this embodiment, the sampling circuit includes a parallel toserial converter 220 which is clocked by clock B of the clock B domain. The bits of data sampled from theregister 206 are stored in aregister 222.FIG. 6 shows an example of aregister 222 which includes 12 flip-flops designated A0, A1, A2, B0, B1, B2, C0, C1, C2, D0, D1, D2, respectively. It is appreciated that theregister 222 may be formed of a variety of temporary storage devices and may include more or fewer bit positions, depending upon the particular application. - Table 2 below indicates one example of the manner in which data bits of the data words being transferred may be sampled and stored in the
register 222.TABLE 2 Data bit mapping to converter register in Clock B Domain Bank D Bank C Bank B Bank A Clock A cycle: D0 D1 D2 C0 C1 C2 B0 B1 B2 A0 A1 A2 0 7 3 X 6 X 2 X 5 1 8 4 0 1 6 X 2 X 5 1 8 4 0 7 3 X 2 X 5 1 8 4 0 7 3 X 6 X 2 3 8 4 0 7 3 X 6 X 2 X 5 1 - In the illustrated embodiment, the flip-flops designated A0, A1, A2, B0, B1, B2, C0, C1, C2, D0, D1, D2, of the
register 222 are logically arranged in a four by three array of four banks A, B, C and D, each of which having three flip-flops in three columns, col1, col2, col3. Thus, as shown inFIG. 6 and Table 2, Bank A has flip-flops A0, A1, A2,, Bank B has flip-flops B0, B1, B2, and so on. - As previously mentioned, in this example, a new word to be transferred is presented each cycle of clock A of the clock A domain. Thus, in both Table 1 and Table 2, four successive clock A cycles are designated
clock A cycle 0,clock A cycle 1,clock A cycle 2 andclock A cycle 3. As previously mentioned and shown in Table 1 above, theshifter 204 shifts bit 7 of the transfer word ofclock A cycle 0 and loads it in the R11 output of theregister 206. As shown inFIG. 6 , the flip-flop D0 of theregister 222 has an input coupled to the R11 output of theregister 206. Accordingly, as shown in Table 2, the flip-flop D0 of the Bank D loads thebit 7 of the transfer word ofclock A cycle 0. The parallel toserial converter 220 includes aninput multiplexer 224 having an input coupled to the R10 output of theregister 206 and an output coupled to the input of the flip-flop D1 of the Bank D. The flip-flop D1 of the Bank D loads bit 3 of the transfer word ofclock A cycle 0 as indicated in Table 2. The remaining flip-flops of theregister 222 are coupled to corresponding outputs of theregister 206 and load shifted bits as set forth in the Tables 1 and 2. - As previously mentioned, a stream of sampled bits is outputted (block 154.
FIG. 4 ) in the second clock domain.FIG. 7 shows one example of outputting astream 250 of sampled bits in the clock B domain. Thestream 250 is outputted by theregister 222 of the parallel toserial converter 220. Thestream 250 comprisesbits word 0,bits word 1, and so on. It is appreciated that the order of the bits, and the number of bits may vary, depending upon the particular application. - In this embodiment, the parallel to
serial converter 220 samples bits of data in the second clock domain of clock B at a fixed time within each clock signal of the first clock domain of clock A. As explained in greater detail below, to output thestream 250 of bits, some bits may be output by theconverter 220 after being loaded by theregister 222. Other bits are first shifted within theregister 222 before being outputted by theregister 222. - As previously mentioned, the input of the flip-flop D1 of the Bank D is coupled to an
input multiplexer 224 having an input coupled to the R10 output of theregister 206. Theinput multiplexer 224 has another input coupled to the output of the flip-flop D0 as shown inFIG. 6 . Thus, either the R10 output of theregister 206 can be loaded into the flip-flop D1, or the output of the flip-flop D0 may be shifted into the flip-flop D1, depending upon the selection of themultiplexer 224. Bits may be loaded into or shifted into the remaining flip-flops of theregister 222 using amultiplexer 224 as shown inFIG. 6 . -
FIG. 8 is a chart illustrating one example of a timing sequence by which bits of a word may be sampled and selectively shifted to produce thestream 250. It is appreciated that other timing sequences may be utilized, depending upon the particular application. In the chart ofFIG. 8 , the four by three array of flip-flops of theregister 222 are represented by a four by three array ofboxes 260 a having four rows of boxes labeled Bank A, Bank B, Bank C, Bank D, in three columns of boxes labeled col0, col1, col2 in the same manner as the flip-flops A0, A1 . . . D2 ofFIG. 6 . Thus, the flip-flop D1, for example, is represented in thearray 260 a ofFIG. 8 by the box in the row labeled Bank D and in the column labeled col1. - In the illustrated embodiment, and as shown in
FIG. 6 , the flip-flops A0, A1, A2, B0, B1, B2, C0, C1, C2, D0, D1, D2, of theregister 222 are clocked by four phases of the clock B, designatedclock B 0°, clock B 90°, clock B 180°clock B 270°which are depicted inFIG. 7 . Thus, for example, the flip-flop D0 is clocked by the clock B 90°, the flip-flop D1 is clocked by theclock B 0°, and so on as shown inFIGS. 6 and 7 . - The four by three
array 260 a of boxes of the chart ofFIG. 8 illustrates the loading of bits during theclock B 0°. As indicated in Table 2, duringclock A cycle 0, the flip-flop C0 (Bank C, col0) loads thebit 6, which isbit 6 of word0 as indicated inFIG. 7 . The loading ofbit 6 by flip-flop C0 is indicated by the box in row BankC, column col0 inarray 260 a ofFIG. 8 . In addition, flip-flops D1 andA2 load bits clock A cycle 0 as indicated in Table 2 andFIG. 8 . - The chart of
FIG. 8 comprises a plurality ofarrays 260 a, 260 b . . . 260 i similar to thearray 260 a. Thearrays 260 a, 260 b . . . 260 i when read in time sequential order corresponding to the timing diagram ofFIG. 7 , are read left to right, top to bottom. The next four by three array 260 b of boxes of the chart ofFIG. 8 illustrates the loading of bits during the clock B 90°. As indicated in Table 2 andFIGS. 7, 8 , duringclock A cycle 0, the flip-flops D0, A1, B2 load thebits word 0. The next four by threearray 260 c of boxes of the chart ofFIG. 8 illustrates the loading of bits during the clock B 180°. As indicated in Table 2 andFIGS. 7, 8 , duringclock A cycle 0, the flip-flops A0, B1, C2 load thebits word 0. - At this point, all 9
bits word 0 have been loaded into flip-flops of theregister 222. In the illustrated embodiment, outputs of the column col2 flip-flops, that is flip-flops A2, B2, C2, D2, may be selected for output to thebit stream 250. In this example, after being loaded by the flip-flops A2, B2, C2,bits word 0 are available for output on outputs outA, outB, outC (FIG. 6 ) of the flip-flops A2, B2, C2, respectively. - The next four by three
array 260 d of boxes of the chart ofFIG. 8 illustrates the shifting of bits during the clock B 270°. As indicated inFIGS. 7, 8 , duringclock A cycle 0, thebits bit 3 ofword 0 is available for output on output outD of flip-flop D2. The flip-flop B0 loads a don't care (as indicated by the “X”) in Table 2 andFIGS. 7, 8 , during the clock B 270°. - The next four by three
array 260 e of boxes of the chart ofFIG. 8 illustrates the shifting of bits during theclock B 0°. As indicated inFIGS. 7, 8 , duringclock A cycle 0, thebits bit 4 ofword 0 is available for output on output outA of flip-flop A2. The flip-flop C0 loads a don't care (as indicated by the “X”) in Table 2 andFIGS. 7, 8 , during theclock B 0°. - It is noted that in the
clock B 0°, as represented by the four by threearray 260 a of boxes of the chart ofFIG. 8 , the flip-flops D1, A2 loaded bits ofword 0. In thenext clock B 0°, as represented by the four by threearray 260 e of boxes of the chart ofFIG. 8 , the flip-flops D1, A2 received shifted bits ofword 0. Themultiplexers 224 coupled to the inputs of the flip-flops D1, A2 are controlled in the illustrated embodiment by a multiplexer select signal multiplexselect0 which is depicted inFIG. 7 . The multiplexer select signal multiplexerselect0 controls theinput multiplexer 224 of the flip-flops which are clocked by the clocksignal clock B 0°. Similarly, the multiplexer select signal multiplexerselect90 controls theinput multiplexers 224 of the flip-flops which are clocked by the clock signal clock B 90°. The multiplexer select signal multiplexerselect180 controls theinput multiplexers 224 of the flip-flops which are clocked by the clock signal clock B 180°. The multiplexer select signal multiplexerselect270 controls theinput multiplexers 224 of the flip-flops which are clocked by the clock signal clock B 270°. - In the remaining four by three
array clock clock B 0°, clock B 90°, clock B 180°, or clock B 270°, and the flip-flops of the column col0 load don't cares. In the illustrated embodiment, outputs of the column col2 flip-flops A2, B2, C2, D2 may be selected to output the remainingbits bit stream 250 as shown inFIG. 7 . - The above described cycle of operations is repeated for each
successive word 1,word 2,word 3 . . . provided in each successiveclock A cycle 1,cycle 2,cycle 3 . . . , respectively. Thus, for example, the four by threearray 272 a of boxes of the chart ofFIG. 8 illustrates the loading of bits during the clock B 90° andclock A cycle 1. The four by threearray 272 b of boxes of the chart ofFIG. 8 illustrates the loading of bits during the clock B 180°andclock A cycle 1. The four by threearray 272 c of boxes of the chart ofFIG. 8 illustrates the loading of bits during the clock B 270° andclock A cycle 1. The remaining portion of the chart ofFIG. 8 for theclock A cycle 1,cycle 2,cycle 3 may be readily determined by reference to Tables 1, 2 andFIGS. 6, 7 . - The
stream 250 sequence of data words, Word0, Word1, . . . Wordn, which is clocked by clock B of the Clock B Domain, may be utilized and processed by other logic of the Clock B Domain as represented by thelogic circuitry 280 which is also clocked by the clock B. Circuitry similar to the clockdomain crossing circuit 120 may be employed to transfer data words from the Clock B Domain over to the Clock A Domain. - The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the present invention(s)” unless expressly specified otherwise. The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise.
- Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.
- A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention. Further, although process operations, method operations, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of operations that may be described does not necessarily indicate a requirement that the operations be performed in that order. The operations of processes described herein may be performed in any order practical. Further, some operations may be performed simultaneously.
- When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the present invention need not include the device itself.
- The described operations may be implemented as a method, apparatus or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The term “article of manufacture” as used herein refers to code or logic implemented in a tangible medium, where such tangible medium may comprise hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.) or a computer readable medium, such as magnetic storage medium (e.g., hard disk drives, floppy disks,, tape, etc.), optical storage (CD-ROMs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, firmware, programmable logic, etc.). Code in the computer readable medium is accessed and executed by a processor. The tangible medium in which the code or logic is encoded may also comprise transmission signals propagating through space or a transmission media, such as an optical fiber, copper wire, etc. The transmission signal in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The transmission signal in which the code or logic is encoded is capable of being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a computer readable medium at the receiving and transmitting stations or devices. Additionally, the “article of manufacture” may comprise a combination of hardware and software components in which the code is embodied, processed, and executed. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope of the present description, and that the article of manufacture may comprise any suitable information bearing medium.
- In certain implementations, the embodiments may be included in a computer system including nonvolatile memory and a storage controller, such as a SCSI, Integrated Drive Electronics (IDE), Redundant Array of Independent Disk (RAID), etc., controller, that manages access to a non-volatile storage device, such as a magnetic disk drive, tape media, optical disk, etc. In alternative implementations, embodiments may be included in a system that does not include nonvolatile memory or a storage controller, such as certain hubs and switches.
- In certain implementations, the embodiments may be implemented in a computer system including a video controller to render information to display on a monitor electrically coupled to the computer system including the host software driver and network controller, such as a computer system comprising a desktop, workstation, server, mainframe, laptop, handheld computer, telephone, etc. Alternatively, the features described herein may be implemented in a computing device that does not include a video controller, such as a switch, router, etc.
- The
devices 114 of the architecture of thesystem 102 may include a network controller to enable communication with a network, such as an Ethernet, a Fibre Channel Arbitrated Loop, etc. Further, the architecture may, in certain embodiments, include a video controller to render information on a display monitor, where the video controller may be implemented on a video card or integrated on integrated circuit components mounted on the motherboard. - An input device may be used to provide user input to the
processor 104, and may include a keyboard, mouse, pen-stylus, microphone, touch sensitive display screen, or any other suitable activation or input mechanism. An output device may be capable of rendering information transmitted from theprocessor 104, or other component, such as a display monitor, printer, storage, etc. - The embodiments of the present description may be implemented on an expansion card such as a network card, such as a Peripheral Component Interconnect (PCI) card or some other card, or on integrated circuit components mounted on the motherboard.
- The foregoing description of various embodiments has been presented for the purposes of illustration. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.
Claims (29)
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060023819A1 (en) * | 2004-07-29 | 2006-02-02 | Adkisson Richard W | Clock synchronizer |
US20070257877A1 (en) * | 2006-04-13 | 2007-11-08 | Etron Technology, Inc. | Method and circuit for transferring data stream across multiple clock domains |
US20130329553A1 (en) * | 2012-06-06 | 2013-12-12 | Mosys, Inc. | Traffic metering and shaping for network packets |
US10204201B1 (en) * | 2016-06-30 | 2019-02-12 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques |
US11351834B2 (en) | 2013-05-31 | 2022-06-07 | Fox Factory, Inc. | Methods and apparatus for adjusting a spring pre-load |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7725502B1 (en) * | 2005-06-15 | 2010-05-25 | Google Inc. | Time-multiplexing documents based on preferences or relatedness |
US7716510B2 (en) | 2006-12-19 | 2010-05-11 | Micron Technology, Inc. | Timing synchronization circuit with loop counter |
US7656745B2 (en) | 2007-03-15 | 2010-02-02 | Micron Technology, Inc. | Circuit, system and method for controlling read latency |
US8176352B2 (en) * | 2008-04-16 | 2012-05-08 | Adavanced Micro Devices, Inc. | Clock domain data transfer device and methods thereof |
US7969813B2 (en) | 2009-04-01 | 2011-06-28 | Micron Technology, Inc. | Write command and write data timing circuit and methods for timing the same |
US8584067B2 (en) | 2010-11-02 | 2013-11-12 | Advanced Micro Devices, Inc. | Clock domain crossing buffer |
US8984320B2 (en) | 2011-03-29 | 2015-03-17 | Micron Technology, Inc. | Command paths, apparatuses and methods for providing a command to a data block |
US8509011B2 (en) | 2011-04-25 | 2013-08-13 | Micron Technology, Inc. | Command paths, apparatuses, memories, and methods for providing internal commands to a data path |
US8552776B2 (en) | 2012-02-01 | 2013-10-08 | Micron Technology, Inc. | Apparatuses and methods for altering a forward path delay of a signal path |
US9166579B2 (en) | 2012-06-01 | 2015-10-20 | Micron Technology, Inc. | Methods and apparatuses for shifting data signals to match command signal delay |
US9054675B2 (en) | 2012-06-22 | 2015-06-09 | Micron Technology, Inc. | Apparatuses and methods for adjusting a minimum forward path delay of a signal path |
US9329623B2 (en) | 2012-08-22 | 2016-05-03 | Micron Technology, Inc. | Apparatuses, integrated circuits, and methods for synchronizing data signals with a command signal |
US8913448B2 (en) | 2012-10-25 | 2014-12-16 | Micron Technology, Inc. | Apparatuses and methods for capturing data in a memory |
US9734097B2 (en) | 2013-03-15 | 2017-08-15 | Micron Technology, Inc. | Apparatuses and methods for variable latency memory operations |
US9727493B2 (en) | 2013-08-14 | 2017-08-08 | Micron Technology, Inc. | Apparatuses and methods for providing data to a configurable storage area |
US9183904B2 (en) | 2014-02-07 | 2015-11-10 | Micron Technology, Inc. | Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path |
US9508417B2 (en) | 2014-02-20 | 2016-11-29 | Micron Technology, Inc. | Methods and apparatuses for controlling timing paths and latency based on a loop delay |
US9530473B2 (en) | 2014-05-22 | 2016-12-27 | Micron Technology, Inc. | Apparatuses and methods for timing provision of a command to input circuitry |
US9531363B2 (en) | 2015-04-28 | 2016-12-27 | Micron Technology, Inc. | Methods and apparatuses including command latency control circuit |
US9813067B2 (en) | 2015-06-10 | 2017-11-07 | Micron Technology, Inc. | Clock signal and supply voltage variation tracking |
US9865317B2 (en) | 2016-04-26 | 2018-01-09 | Micron Technology, Inc. | Methods and apparatuses including command delay adjustment circuit |
US9601170B1 (en) | 2016-04-26 | 2017-03-21 | Micron Technology, Inc. | Apparatuses and methods for adjusting a delay of a command signal path |
US9997220B2 (en) | 2016-08-22 | 2018-06-12 | Micron Technology, Inc. | Apparatuses and methods for adjusting delay of command signal path |
US10224938B2 (en) | 2017-07-26 | 2019-03-05 | Micron Technology, Inc. | Apparatuses and methods for indirectly detecting phase variations |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5915107A (en) * | 1997-09-26 | 1999-06-22 | Advanced Micro Devices, Inc. | Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other |
US6009107A (en) * | 1995-01-11 | 1999-12-28 | Telefonaktiebolaget Lm Ericsson | Data transmission system |
US6049887A (en) * | 1997-12-04 | 2000-04-11 | Intel Corporation | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio |
US6311285B1 (en) * | 1999-04-27 | 2001-10-30 | Intel Corporation | Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency |
-
2005
- 2005-09-30 US US11/241,581 patent/US7451338B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6009107A (en) * | 1995-01-11 | 1999-12-28 | Telefonaktiebolaget Lm Ericsson | Data transmission system |
US5915107A (en) * | 1997-09-26 | 1999-06-22 | Advanced Micro Devices, Inc. | Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other |
US6049887A (en) * | 1997-12-04 | 2000-04-11 | Intel Corporation | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio |
US6311285B1 (en) * | 1999-04-27 | 2001-10-30 | Intel Corporation | Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency |
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US20060023819A1 (en) * | 2004-07-29 | 2006-02-02 | Adkisson Richard W | Clock synchronizer |
US20070257877A1 (en) * | 2006-04-13 | 2007-11-08 | Etron Technology, Inc. | Method and circuit for transferring data stream across multiple clock domains |
US7860202B2 (en) * | 2006-04-13 | 2010-12-28 | Etron Technology, Inc. | Method and circuit for transferring data stream across multiple clock domains |
US20130329553A1 (en) * | 2012-06-06 | 2013-12-12 | Mosys, Inc. | Traffic metering and shaping for network packets |
US9667546B2 (en) | 2012-06-06 | 2017-05-30 | Mosys, Inc. | Programmable partitionable counter |
US11351834B2 (en) | 2013-05-31 | 2022-06-07 | Fox Factory, Inc. | Methods and apparatus for adjusting a spring pre-load |
US10204201B1 (en) * | 2016-06-30 | 2019-02-12 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques |
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