CN112737571A - Clock circuit and clock circuit generating method, device, equipment and medium - Google Patents

Clock circuit and clock circuit generating method, device, equipment and medium Download PDF

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Publication number
CN112737571A
CN112737571A CN202011615548.9A CN202011615548A CN112737571A CN 112737571 A CN112737571 A CN 112737571A CN 202011615548 A CN202011615548 A CN 202011615548A CN 112737571 A CN112737571 A CN 112737571A
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China
Prior art keywords
clock
module
frequency division
delay
frequency
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CN202011615548.9A
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Chinese (zh)
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杨申
臧凤仙
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Shanghai Jinzhuo Technology Co Ltd
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Shanghai Jinzhuo Technology Co Ltd
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Priority to CN202011615548.9A priority Critical patent/CN112737571A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1803—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the counter or frequency divider being connected to a cycle or pulse swallowing circuit

Abstract

The embodiment of the invention discloses a clock circuit and a clock circuit generating method, a clock circuit generating device, clock circuit generating equipment and a clock circuit generating medium. The clock circuit comprises a clock creating module, a clock frequency dividing module and a clock delay module; the clock creating module is used for generating a source clock signal with preset frequency; the clock frequency division module is used for carrying out even frequency division of preset multiples on the source clock signal to generate a frequency division clock signal; and the clock delay module is used for generating a preset number of phase delay signals according to the source clock signal and the frequency division clock signal and outputting the phase delay signals to the clock circuit external module. The embodiment of the invention solves the problem that the method for timing by adopting a single-path high-frequency clock signal has high requirement on the performance of hardware, avoids introducing DLL into the circuit and ensures the low power consumption performance and high integration of ASIC.

Description

Clock circuit and clock circuit generating method, device, equipment and medium
Technical Field
The embodiments of the present invention relate to the field of application integrated circuit technologies, and in particular, to a clock circuit and a method, an apparatus, a device, and a medium for generating a clock circuit.
Background
The method comprises the steps of timing an event length by adopting a low-frequency clock signal, sampling both rising edges and falling edges of the clock signal, wherein the minimum time interval which can be distinguished is a half period of the clock signal, namely the highest timing precision is limited by the frequency of the clock signal.
In order to improve the timing accuracy, in the prior art, a Delay Locked Loop (DLL) is usually used to perform different phase delays on a low-frequency clock signal to generate a plurality of clocks with different phases, each path has an equal smaller time interval, and the timing accuracy can reach the smaller time interval when the plurality of signals are sampled simultaneously.
However, when the method in the prior art is implemented in an application integrated circuit (ASIC), the added DLL will increase extra power consumption and area, and destroy the low power consumption performance and high integration of the ASIC.
Disclosure of Invention
The embodiment of the invention provides a clock circuit and a clock circuit generating method, a clock circuit generating device and a clock circuit generating medium, which solve the problem that a method for timing by adopting a single-path high-frequency clock signal has high requirement on hardware performance, avoid introducing DLL into a circuit and ensure the low power consumption performance and high integration degree of an ASIC.
In a first aspect, an embodiment of the present invention provides a clock circuit, including a clock creating module, a clock dividing module, and a clock delaying module;
the clock creating module is used for generating a source clock signal with a preset frequency and outputting the source clock signal to the clock frequency dividing module and the clock delay module;
the clock frequency division module is used for performing even frequency division of preset multiple on the source clock signal output by the clock creation module to generate a frequency division clock signal, and outputting the frequency division clock signal to a clock circuit external module and the clock delay module at the same time;
the clock delay module is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and output the phase delay signals to the clock circuit external module;
the frequency division clock signal and the phase delay signal form a low-frequency clock signal group, and every two adjacent paths of signals in the low-frequency clock signal group have the same preset phase difference and have fixed phase relation.
In a second aspect, an embodiment of the present invention further provides a clock circuit generation method, including:
receiving hardware design information and constraint information aiming at a clock circuit, wherein the hardware design information comprises a clock creation instruction, a clock frequency division instruction and a clock delay instruction;
adding a clock creating module in a basic circuit according to the clock creating instruction, wherein the clock creating module is used for generating a source clock signal with a preset frequency and outputting the source clock signal to the clock frequency dividing module and the clock delay module;
adding a clock frequency division module in the basic circuit according to the clock frequency division instruction, wherein the clock frequency division module is used for carrying out even frequency division of preset multiple on the source clock signal output by the clock creation module to generate a frequency division clock signal, and outputting the frequency division clock signal to a clock circuit external module and the clock delay module simultaneously;
adding a clock delay module in the basic circuit according to the clock delay instruction, wherein the clock delay module is used for generating phase delay signals with a preset number according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and outputting the phase delay signals to the clock circuit external module;
and determining the connection relation among the clock creating module, the clock frequency dividing module and the clock delay module in the basic circuit according to the constraint information to generate a clock circuit.
In a third aspect, an embodiment of the present invention further provides a clock circuit generation apparatus, including:
the information receiving module is used for receiving hardware design information and constraint information aiming at a clock circuit, wherein the hardware design information comprises a clock creation instruction, a clock frequency division instruction and a clock delay instruction;
a clock creating module adding module, configured to add a clock creating module in a basic circuit according to the clock creating instruction, where the clock creating module is configured to generate a source clock signal with a preset frequency and output the source clock signal to the clock frequency dividing module and the clock delay module;
a clock frequency division module adding module, configured to add a clock frequency division module in the basic circuit according to the clock frequency division instruction, where the clock frequency division module is configured to perform even frequency division of a preset multiple on the source clock signal output by the clock creating module, generate a frequency division clock signal, and output the frequency division clock signal to a clock circuit external module and the clock delay module at the same time;
a clock delay module adding module, configured to add a clock delay module to the basic circuit according to the clock delay instruction, where the clock delay module is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creating module and the frequency division clock signal output by the clock frequency division module, and output the phase delay signals to the clock circuit external module;
and the clock circuit generating module is used for determining the connection relation among the clock creating module, the clock frequency dividing module and the clock delay module in the basic circuit according to the constraint information to generate a clock circuit.
In a fourth aspect, an embodiment of the present invention further provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the clock circuit generation method according to the embodiment of the present invention is implemented.
In a fifth aspect, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the clock circuit generation method according to the embodiment of the present invention.
According to the technical scheme of the embodiment of the invention, based on one path of clock signal, a group of low-frequency clock signals with only phase difference between each path of signal, fixed phase relation and equal phase difference between every two adjacent paths are obtained through a signal frequency division and delay technology, and when a high-precision meter adopting a multi-path low-speed clock can be realized by sampling according to the group of low-frequency clock signals, the problem that the requirement on hardware performance is too high by adopting a single-path high-frequency clock signal for timing is solved, and meanwhile, DLL (delay locked loop) is prevented from being introduced into a circuit, so that the low power consumption performance and high integration degree of an ASIC (application specific integrated circuit) are.
Drawings
Fig. 1A is a block diagram of a clock circuit according to an embodiment of the present invention.
Fig. 1B is a schematic diagram of a clock signal phase according to an embodiment of the present invention.
Fig. 2A is a schematic structural diagram of a clock circuit according to a second embodiment of the present invention.
Fig. 2B is a schematic structural diagram of another clock circuit according to a second embodiment of the present invention.
Fig. 3 is a flowchart of a clock circuit generating method according to a third embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a clock circuit generating device according to a fourth embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a computer device according to a fifth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1A is a block diagram of a clock circuit according to an embodiment of the present invention. As shown in fig. 1A, the apparatus of the embodiment of the present invention includes: a clock creation module 110, a clock division module 120, and a clock delay module 130.
The clock creating module 110 is configured to generate a source clock signal with a preset frequency, and output the source clock signal to the clock dividing module 120 and the clock delaying module 130.
Specifically, the source clock signal may be a high-frequency clock signal with a preset frequency. The predetermined frequency may be determined based on a minimum time interval resolvable to be reached by the clock.
Alternatively, in an ASIC, the clock creation module 110 may be a Phase Locked Loop (PLL).
Optionally, the period of the source clock signal is equal to the target sampling time precision.
Specifically, the target sampling time precision may be the precision that the clock needs to achieve, i.e. the resolvable minimum time interval, which may be 1ns, for example. The period of the source clock signal is equal to the target sampling time precision, and the preset frequency of the source clock signal can be calculated according to the target sampling time precision. Illustratively, for a target sampling time accuracy of 1ns, a source clock signal with a period of 1ns and a frequency of 1GHz needs to be created.
The clock dividing module 120 is configured to divide the source clock signal output by the clock creating module 110 by an even number of a preset multiple to generate the divided clock signal, and output the divided clock signal to the clock circuit external module and the clock delay module 130 at the same time.
Specifically, the source clock signal is divided by an even number to obtain a divided clock signal with a duty ratio of 50%. The even-number frequency division can reduce the frequency of the source clock signal by multiples to obtain a frequency-divided clock signal with lower frequency, and the multiple relation between the frequency of the obtained frequency-divided clock signal and the frequency of the source clock signal is matched with the frequency-divided multiples of the even-number frequency division. Illustratively, a source clock signal with a frequency of 1GHz is divided by eight to obtain a divided clock signal with a frequency of 125MHz, the period of which is 8ns, and the timing precision when sampling is performed according to the rising edge and the falling edge of which can only reach 4 ns.
Alternatively, in an ASIC, the clock divider module 120 may be a frequency divider. During ASIC design, a counter is designed by adopting a hardware description language, and output signal inversion is set according to the counting times of the counter on the rising edge or the falling edge of a source clock signal to realize even frequency division of different frequency division multiples.
The clock delay module 130 is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creation module 110 and the frequency division clock signal output by the clock frequency division module 120, and output the phase delay signals to the clock circuit external module.
Specifically, the waveform of the phase delay signal is completely consistent with the waveform of the frequency division clock signal, only a phase difference exists, and the phase relationship between each path of signal is fixed. And the phase difference between two adjacent paths of signals in the frequency division clock signal and the phase delay signal obtained according to the source clock signal is equal, and the time interval between the starting points of the periods is equal to the period of the source clock signal. And if the frequency division multiples are different, the obtained multiple relation between the period of the frequency division clock signal and the period of the source clock signal is different.
Optionally, the number of signals in the low-frequency clock signal group is one half of a preset multiple of the even-numbered frequency division; the predetermined phase difference is equal to 180 ° divided by the number of signals in the set of low frequency clock signals. Illustratively, as shown in fig. 1B, a source clock signal with a frequency of 1GHz is divided by eight to obtain a divided clock signal Clk _125M _0 with a frequency of 125MHz, and delayed according to the source clock signal to obtain three phase delayed signals Clk _125M _45, Clk _125M _90, and Clk _125M _135 with phase differences of 45 °, 90 °, and 135 ° respectively, and the phase relationships are fixed, so that timing with a precision of 1ns can be realized when sampling is performed according to rising edges and falling edges of the divided clock signal and the phase delayed signals.
Optionally, in the ASIC, the clock delay module 130 may include a D flip-flop. When a hardware description language is adopted for circuit design, a D trigger definition instruction can be adopted for realizing time delay, and a relevant register is instantiated in a Register Transfer Level (RTL) so as to keep a circuit structure, so that the phase relation between a frequency division clock signal and a phase delay signal is determined, and unnecessary logic optimization of a back-end tool is avoided.
Optionally, the frequency-divided clock signal and the phase-delayed signal form a low-frequency clock signal group, and each two adjacent signals in the low-frequency clock signal group have the same preset phase difference and have a fixed phase relationship.
Specifically, the clock circuit external module may use the low-frequency clock signal group as a clock, and may perform simultaneous sampling according to rising edges and falling edges of the frequency-divided clock signal and the phase delay signal, so as to achieve the timing of the target clock precision. When ASIC back end is restrained, a clock group is established to restrain the frequency division clock signal and the phase delay signal, the frequency division clock signal and the phase delay signal are set as synchronous clocks, and a back end tool can ensure that the phase deviation is controlled within a set range; and setting the source clock signal and the clock group as asynchronous clocks.
The embodiment of the invention provides a clock circuit, based on one path of clock signals, a group of low-frequency clock signals with only phase difference between each path of signals, fixed phase relation and equal phase difference between every two adjacent paths are obtained through a signal frequency division and delay technology, and when a high-precision meter adopting a multi-path low-speed clock is realized by sampling according to the group of low-frequency clock signals, the problem that the requirement on hardware performance is too high by adopting a single-path high-frequency clock signal for timing is solved, meanwhile, DLL is prevented from being introduced into the circuit, and the low power consumption performance and high integration degree of an ASIC are ensured.
Example two
Fig. 2A is a schematic structural diagram of a clock circuit according to a second embodiment of the present invention. As shown in fig. 2A, on the basis of the above embodiment, the embodiment of the present invention embodies the structures of a clock creating module, a clock dividing module, and a clock delaying module, and includes: the clock creation module is embodied as a phase-locked loop 111 of a preset frequency, the clock division module is embodied as a frequency divider 121 of a preset multiple, and the clock delay module is embodied as a preset number of D flip-flops 131.
The pll 111 is configured to create a source clock signal, and the preset frequency of the pll 111 may be the preset frequency of the source clock signal output by the pll 111. Specifically, the phase-locked loop 111 is a closed-loop feedback control circuit, and controls the frequency and phase of an internal oscillation signal of the loop by using an externally input reference signal, so that the output signal and the reference signal can keep a fixed phase relationship, and the phase-locked loop can perform the functions of frequency multiplication on an external clock signal with a lower frequency and outputting a clock signal with a fixed multiple frequency in the circuit.
The frequency divider 121 is configured to divide the source clock signal by an even number to obtain a divided clock signal, and the preset multiple of the frequency divider 121 may be a division multiple of the source clock signal by the even number.
For example, the frequency divider 121 may count rising edges of the source clock signal, and the output signal of the frequency divider 121 is inverted once every time four rising edges are counted, so as to divide the source clock signal by eight, where the output signal of the frequency divider 121 is the divided clock signal.
Each D flip-flop 131 is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and each D flip-flop 131 generates a path of phase delay signal.
Specifically, the D flip-flop 131 includes a clock terminal, an input terminal, and an output terminal, where the clock terminal is configured to receive a source clock signal, the input terminal is configured to receive a frequency division clock signal or a phase delay signal, and the output terminal is configured to output a phase delay signal generated by delaying a signal received by the input terminal according to the source clock signal. The D flip-flop 131 may sample the signal received by the input terminal thereof when detecting the rising edge of the signal received by the clock terminal thereof, output the sampled data from the output terminal and maintain for one cycle until detecting the rising edge of the signal received by the clock terminal again, and repeat the above steps.
Optionally, the clock delay module 130 includes: a first stage D flip-flop 131, a predetermined number of intermediate stage D flip-flops 131, and a last stage D flip-flop 131.
The first-stage D flip-flop 131 is configured to receive the source clock signal and the frequency-divided clock signal, perform phase delay on the frequency-divided clock signal according to the source clock signal, generate a path of phase delay signal with a phase delayed by a preset phase difference from the frequency-divided clock signal, and output the phase delay signal to the outside of the clock circuit and the next-stage D flip-flop 131 at the same time.
Each of the intermediate D flip-flops 131 is configured to receive the source clock signal and the phase delay signal output by the previous D flip-flop 131, perform phase delay on the phase delay signal according to the source clock signal, generate a path of phase delay signal with a phase delay that is a preset phase difference from the phase delay signal output by the previous D flip-flop 131, and output the phase delay signal to the outside of the clock circuit and the next D flip-flop 131 at the same time.
The final D flip-flop 131 is configured to receive the source clock signal and the phase delay signal output by the previous D flip-flop 131, perform phase delay on the phase delay signal according to the source clock signal, generate a path of phase delay signal with a phase delay that is a preset phase difference from the phase delay signal output by the previous D flip-flop 131, and output the phase delay signal to the outside of the clock circuit.
The embodiment of the invention provides a clock circuit, based on a path of clock signal, a group of low-frequency clock signals with only phase difference between each path of signals, fixed phase relation and equal phase difference between every two adjacent paths are obtained through a signal frequency division and delay technology, and when a high-precision meter adopting a multi-path low-speed clock is realized by sampling according to the group of low-frequency clock signals, the problem that the requirement on hardware performance is too high by adopting a method for timing by adopting a single-path high-frequency clock signal is solved, and meanwhile, a DLL (delay locked loop) is prevented from being introduced into the circuit, so that the low power consumption performance and high integration degree of an ASIC (application specific integrated circuit) are ensured; the clock circuit is simple in logic and design, and can realize that each path can be checked through a constraint tool without unnecessary logic optimization of a back-end tool.
The embodiment of the invention also provides a specific implementation mode. Fig. 2B is a schematic structural diagram of a clock circuit in the embodiment. As shown in fig. 2B, the clock circuit according to the embodiment of the present invention includes a clock creating module, a clock dividing module and a clock delaying module, wherein the clock creating module includes a phase-locked loop 211 with a preset frequency of 1GHz, the clock dividing module includes a frequency divider 221 with a preset multiple of eight frequency divisions, and the clock delaying module includes three D flip-flops D1、D2And D3。
The phase-locked loop 211 creates a source clock signal Clk _1GHz with a frequency of 1GHz, and outputs the source clock signal Clk _1GHz to the input terminal of the frequency divider 221 and the D flip-flop D1、D2And D3The clock terminal of (1).
Divider 221 is a divide-by-eight divider. After receiving the source clock signal Clk _1GHz, the frequency divider 221 divides the source clock signal Clk _1GHz by eight to obtain a frequency-divided clock signal Clk _125M _0 with a frequency of 125MHz, and outputs the frequency-divided clock signal Clk _125M _0 to the D flip-flop D1And input Clk0 of a module external to the clock circuit.
D flip-flop D1The input end receives the frequency-dividing clock signal Clk _125M _0, the clock end receives the source clock signal Clk _1GHz, the phase delay is carried out on the frequency-dividing clock signal Clk _125M _0, the phase difference is 45 degrees, the phase delay signal Clk _125M _45 is output, and the phase delay signal Clk _125M _45 is output to the D trigger D2And input Clk1 of a module external to the clock circuit.
D flip-flop D2Having an input receiving a phase delayed signal Clk _125M _45 and a clock receiving a sourceAfter the clock signal Clk _1GHz, the phase delay signal Clk _125M _45 is subjected to phase delay, the phase difference is 45 degrees, the phase delay signal Clk _125M _90 is output, and the phase delay signal Clk _125M _90 is output to a D trigger D3And input Clk2 of a module external to the clock circuit.
D flip-flop D3The input terminal of the clock circuit receives the phase delay signal Clk _125M _90, the clock terminal receives the source clock signal Clk _1GHz, then the phase delay is performed on the phase delay signal Clk _125M _90, the phase difference is 45 degrees, the phase delay signal Clk _125M _135 is output, and the phase delay signal Clk _125M _135 is output to the input terminal Clk2 of the external module of the clock circuit.
The divided clock signals Clk _125M _0, the phase delay signals Clk _125M _45, Clk _125M _90 and Clk _125M _135 are respectively output to the inputs Clk0, Clk1, Clk2 and Clk3 of the external module of the clock circuit, and are a set of synchronous clocks with a phase difference of 45 ° and a fixed phase relationship.
The clock circuit external module counts time according to the frequency division clock signal Clk _125M _0, the phase delay signals Clk _125M _45, Clk _125M _90 and Clk _125M _135, performs first sampling when detecting a first rising edge of Clk _125M _0, performs second sampling when detecting a first rising edge of Clk _125M _45, performs third sampling when detecting a first rising edge of Clk _125M _90, performs fourth sampling when detecting a first rising edge of Clk _125M _135, performs fifth sampling when detecting a first falling edge of Clk _125M _0, performs sixth sampling when detecting a first falling edge of Clk _125M _45, performs seventh sampling when detecting a first falling edge of Clk _125M _90, and performs eighth sampling when detecting a first falling edge of Clk _125M _ 135; and then, when the rising edge of the Clk _125M _0 is detected again, carrying out ninth sampling, namely entering the second period of the Clk _125M _0, and continuing to carry out detection and sampling according to the above mode, wherein the time interval between every two samplings is 1ns, so that the timing with the target clock precision of 1ns is realized.
The above specific embodiment provides a clock circuit, based on a single path of high-frequency clock signal with a frequency of 1GHz, a group of low-frequency clock signals with a frequency of 125MHz including four paths is obtained through signal frequency division and delay technology, a phase difference between each path of signals is 45 ° and a phase relationship is fixed, sampling is performed according to the group of low-frequency clock signals, and timing precision reaches 1 ns.
EXAMPLE III
Fig. 3 is a flowchart of a clock circuit generating method according to a third embodiment of the present invention. The embodiment of the invention is applicable to the condition of generating the clock circuit according to the hardware design information and the constraint information, and the method can be executed by the clock circuit generating device provided by the embodiment of the invention. As shown in fig. 3, the method of the embodiment of the present invention specifically includes:
step 301, receiving hardware design information and constraint information for a clock circuit, where the hardware design information includes a clock creation instruction, a clock division instruction, and a clock delay instruction.
The hardware design information may be a computer-readable hardware description language describing a hardware structure of the clock circuit, and the circuit structure and the timing relationship may be determined according to the hardware design information. The clock creation instruction may be a hardware description language instruction describing a hardware structure of the clock creation module, and may be, optionally, a hardware description language instruction of a phase-locked loop with a preset frequency. The clock dividing instruction may be a hardware description language instruction describing a hardware structure of the clock dividing module, and may be, optionally, a hardware description language instruction of a divider with a preset multiple. The clock delay instruction may be a hardware description language instruction describing a hardware structure of the clock delay module, and may be, optionally, a hardware description language instruction of a preset number of D flip-flops.
The constraint information may be a computer readable language that constrains the hardware structure of the clock circuit, and may be a definition of the clock signal generated by the clock circuit.
Step 302, adding a clock creating module in the basic circuit according to the clock creating instruction, where the clock creating module is configured to generate a source clock signal with a preset frequency, and output the source clock signal to the clock frequency dividing module and the clock delay module.
The basic circuit may be a preset circuit without any structure and function, and a module may be added to the basic circuit to generate a circuit with a specific structure and function.
The source clock signal may be a high frequency clock signal of a predetermined frequency. The predetermined frequency may be determined based on a minimum time interval resolvable to be reached by the clock. Optionally, the period of the source clock signal is equal to the target sampling time precision. The target sampling time precision may be the precision that the clock timing needs to achieve, i.e., the minimum time interval that can be resolved. The period of the source clock signal is equal to the target sampling time precision, and the preset frequency of the source clock signal can be calculated according to the target sampling time precision.
Optionally, the clock creation instruction may be a hardware description language instruction of a phase-locked loop with a preset frequency, and the phase-locked loop with the preset frequency may be added to the base circuit. The preset frequency of the phase-locked loop may be a preset frequency of a source clock signal output by the phase-locked loop.
And step 303, adding a clock frequency division module in the basic circuit according to the clock frequency division instruction, where the clock frequency division module is configured to perform even frequency division of a preset multiple on the source clock signal output by the clock creation module to generate a frequency division clock signal, and output the frequency division clock signal to a clock circuit external module and the clock delay module at the same time.
The clock frequency division module divides the source clock signal by even numbers to obtain a frequency division clock signal with a duty ratio of 50%. The even-number frequency division can reduce the frequency of the source clock signal by multiples to obtain a frequency-divided clock signal with lower frequency, and the multiple relation between the frequency of the obtained frequency-divided clock signal and the frequency of the source clock signal is matched with the frequency-divided multiples of the even-number frequency division.
Alternatively, the clock division instruction may be a hardware description language instruction of a divider with a preset multiple, and the preset multiple of the divider may be a division multiple for dividing the source clock signal by an even number.
Step 304, adding a clock delay module in the basic circuit according to the clock delay instruction, where the clock delay module is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and output the phase delay signals to the clock circuit external module.
The waveform of the phase delay signal is completely consistent with that of the frequency division clock signal, only phase difference exists, and the phase relation between each path of signal is fixed and unchanged. And the phase difference between two adjacent paths of signals in the frequency division clock signal and the phase delay signal obtained according to the source clock signal is equal, and the time interval between the starting points of the periods is equal to the period of the source clock signal. And if the frequency division multiples are different, the obtained multiple relation between the period of the frequency division clock signal and the period of the source clock signal is different.
Optionally, the clock delay instruction may be a hardware description language instruction of a preset number of D flip-flops, and each D flip-flop generates a path of phase delay signal.
And 305, determining the connection relation among the clock creating module, the clock frequency dividing module and the clock delay module in the basic circuit according to the constraint information to generate a clock circuit.
The circuit hardware structure can be defined by defining the clock signal according to the constraint information.
Optionally, the constraint information includes: clock creation constraint information, clock division constraint information, clock delay constraint information, phase relationship constraint information, and register constraint information.
The clock creating constraint information comprises creating a source clock with a preset frequency; the clock frequency division constraint information comprises even number frequency division of preset multiple for the source clock to generate a frequency division clock; the clock delay constraint information comprises defining a clock generated in a previous-stage component as a source clock, delaying the source clock by using the source clock, and generating a phase delay clock with a phase delay which is a preset phase difference with respect to the source clock; the phase relation constraint information comprises setting the frequency division clock and the phase delay clock as synchronous clocks to form a clock group; setting the source clock and the clock group as asynchronous clocks; the register constraint information includes instantiating the associated register.
Specifically, clock definition is performed according to constraint information, so that the setup and hold time of the register is in the clock domain of the source clock, and the comprehensive tool can perform checking to ensure satisfaction. The frequency division clock and the phase delay clock are set as synchronous clocks to form a clock group, a back-end tool can ensure that the phase deviation between the frequency division clock and the phase delay clock is within a set range, the clock group is adopted for timing, and simultaneous sampling can be carried out according to the rising edge and the falling edge of the frequency division clock signal and the phase delay signal, so that the timing of the target clock precision is realized.
Optionally, the correlation registers may include phase-locked loop correlation registers, divider correlation registers, and D flip-flop correlation registers. The instantiation of the relevant register in the RTL can maintain the circuit structure and avoid the unnecessary logic optimization of a back-end tool.
The embodiment of the invention provides a clock circuit generation method, which can obtain a clock signal based on one path, generates a group of clock circuits of low-frequency clock signals with only phase difference between each path of signals, fixed phase relation and equal phase difference between every two adjacent paths through a signal frequency division and delay technology, can realize a high-precision meter adopting a multi-path low-speed clock by sampling according to the group of low-frequency clock signals, solves the problem that the requirement on hardware performance is overhigh by adopting a single-path high-frequency clock signal for timing, avoids introducing DLL (delay locked loop) into the circuit, ensures the low-power consumption performance and high integration of an ASIC (application specific integrated Circuit), is simple to realize the ASIC, can detect each path through a constraint tool, and does not generate places which cannot be detected by the tool.
Example four
Fig. 4 is a schematic structural diagram of a clock circuit generating apparatus according to a fourth embodiment of the present invention, as shown in fig. 4, the apparatus includes: an information receiving module 401, a clock creation module adding module 402, a clock division module adding module 403, a clock delay module adding module 404, and a clock circuit generating module 405.
The information receiving module 401 is configured to receive hardware design information and constraint information for a clock circuit, where the hardware design information includes a clock creation instruction, a clock division instruction, and a clock delay instruction.
A clock creating module adding module 402, configured to add a clock creating module in the basic circuit according to the clock creating instruction, where the clock creating module is configured to generate a source clock signal with a preset frequency, and output the source clock signal to the clock frequency dividing module and the clock delay module.
A clock frequency division module adding module 403, configured to add a clock frequency division module in the basic circuit according to the clock frequency division instruction, where the clock frequency division module is configured to perform even frequency division of a preset multiple on the source clock signal output by the clock creating module, generate a frequency division clock signal, and output the frequency division clock signal to a clock circuit external module and the clock delay module at the same time.
A clock delay module adding module 404, configured to add a clock delay module in the basic circuit according to the clock delay instruction, where the clock delay module is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creating module and the frequency division clock signal output by the clock frequency division module, and output the phase delay signals to the clock circuit external module.
A clock circuit generating module 405, configured to determine, according to the constraint information, a connection relationship among the clock creating module, the clock dividing module, and the clock delaying module in the basic circuit, so as to generate a clock circuit.
In an optional implementation manner of the embodiment of the present invention, the constraint information includes: clock creation constraint information, clock frequency division constraint information, clock delay constraint information, phase relation constraint information and register constraint information; the clock creating constraint information comprises creating a source clock with a preset frequency; the clock frequency division constraint information comprises even number frequency division of preset multiple for the source clock to generate a frequency division clock; the clock delay constraint information comprises defining a clock generated in a previous-stage component as a source clock, delaying the source clock by using the source clock, and generating a phase delay clock with a phase delay which is a preset phase difference with respect to the source clock; the phase relation constraint information comprises setting the frequency division clock and the phase delay clock as synchronous clocks to form a clock group; setting the source clock and the clock group as asynchronous clocks; the register constraint information includes instantiating the associated register.
The device can execute the method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
The embodiment of the invention provides a clock circuit generating device, which can obtain a clock signal based on one path, generates a group of clock circuits of low-frequency clock signals with only phase difference between each path of signals, fixed phase relation and equal phase difference between every two adjacent paths through a signal frequency division and delay technology, can realize a high-precision meter adopting a multi-path low-speed clock by sampling according to the group of low-frequency clock signals, solves the problem that the requirement on hardware performance is overhigh by adopting a single-path high-frequency clock signal for timing, avoids introducing DLL (delay locked loop) into the circuit, ensures the low-power consumption performance and high integration degree of an ASIC (application specific integrated Circuit), is simple to realize the ASIC, can detect each path through a constraint tool, and does not generate places which cannot be detected by the tool.
EXAMPLE five
Fig. 5 is a schematic structural diagram of a computer device according to a fifth embodiment of the present invention. FIG. 5 illustrates a block diagram of an exemplary computer device 12 suitable for use in implementing embodiments of the present invention. The computer device 12 shown in FIG. 5 is only an example and should not bring any limitations to the functionality or scope of use of embodiments of the present invention.
As shown in FIG. 5, computer device 12 is in the form of a general purpose computing device. The components of computer device 12 may include, but are not limited to: one or more processors 16, a memory 28, and a bus 18 that connects the various system components (including the memory 28 and the processors 16).
Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, such architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, micro-channel architecture (MAC) bus, enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
Computer device 12 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer device 12 and includes both volatile and nonvolatile media, removable and non-removable media.
The memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)30 and/or cache memory 32. Computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 5, and commonly referred to as a "hard drive"). Although not shown in FIG. 5, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.
Computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), with one or more devices that enable a user to interact with computer device 12, and/or with any devices (e.g., network card, modem, etc.) that enable computer device 12 to communicate with one or more other computing devices. Such communication may be through an input/output (I/O) interface 22. Also, computer device 12 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via network adapter 20. As shown, network adapter 20 communicates with the other modules of computer device 12 via bus 18. It should be appreciated that although not shown in FIG. 4, other hardware and/or software modules may be used in conjunction with computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
The processor 16 executes various functional applications and data processing by running the program stored in the memory 28, thereby implementing the clock circuit generation method provided by the embodiment of the present invention: receiving hardware design information and constraint information aiming at a clock circuit, wherein the hardware design information comprises a clock creation instruction, a clock frequency division instruction and a clock delay instruction; adding a clock creating module in a basic circuit according to the clock creating instruction, wherein the clock creating module is used for generating a source clock signal with a preset frequency and outputting the source clock signal to the clock frequency dividing module and the clock delay module; adding a clock frequency division module in the basic circuit according to the clock frequency division instruction, wherein the clock frequency division module is used for carrying out even frequency division of preset multiple on the source clock signal output by the clock creation module to generate a frequency division clock signal, and outputting the frequency division clock signal to a clock circuit external module and the clock delay module simultaneously; adding a clock delay module in the basic circuit according to the clock delay instruction, wherein the clock delay module is used for generating phase delay signals with a preset number according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and outputting the phase delay signals to the clock circuit external module; and determining the connection relation among the clock creating module, the clock frequency dividing module and the clock delay module in the basic circuit according to the constraint information to generate a clock circuit.
EXAMPLE six
A sixth embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where when the computer program is executed by a processor, the computer program implements a clock circuit generation method provided in the embodiment of the present invention: receiving hardware design information and constraint information aiming at a clock circuit, wherein the hardware design information comprises a clock creation instruction, a clock frequency division instruction and a clock delay instruction; adding a clock creating module in a basic circuit according to the clock creating instruction, wherein the clock creating module is used for generating a source clock signal with a preset frequency and outputting the source clock signal to the clock frequency dividing module and the clock delay module; adding a clock frequency division module in the basic circuit according to the clock frequency division instruction, wherein the clock frequency division module is used for carrying out even frequency division of preset multiple on the source clock signal output by the clock creation module to generate a frequency division clock signal, and outputting the frequency division clock signal to a clock circuit external module and the clock delay module simultaneously; adding a clock delay module in the basic circuit according to the clock delay instruction, wherein the clock delay module is used for generating phase delay signals with a preset number according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and outputting the phase delay signals to the clock circuit external module; and determining the connection relation among the clock creating module, the clock frequency dividing module and the clock delay module in the basic circuit according to the constraint information to generate a clock circuit.
Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or computer device. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A clock circuit is characterized by comprising a clock creating module, a clock frequency dividing module and a clock delay module;
the clock creating module is used for generating a source clock signal with a preset frequency and outputting the source clock signal to the clock frequency dividing module and the clock delay module;
the clock frequency division module is used for performing even frequency division of preset multiple on the source clock signal output by the clock creation module to generate a frequency division clock signal, and outputting the frequency division clock signal to a clock circuit external module and the clock delay module at the same time;
the clock delay module is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and output the phase delay signals to the clock circuit external module;
the frequency division clock signal and the phase delay signal form a low-frequency clock signal group, and every two adjacent paths of signals in the low-frequency clock signal group have the same preset phase difference and have fixed phase relation.
2. The clock circuit of claim 1, wherein a period of the source clock signal is equal to the target sampling time precision;
the number of signals in the low-frequency clock signal group is one half of the preset multiple of the even frequency division;
the predetermined phase difference is equal to 180 ° divided by the number of signals in the set of low frequency clock signals.
3. The clock circuit of claim 1, wherein the clock creation module comprises: a phase locked loop of a preset frequency.
4. The clock circuit of claim 1, wherein the clock divider module comprises: a frequency divider with preset multiples;
the clock delay module comprises: the D triggers are preset in number, and each D trigger generates a path of phase delay signals.
5. The clock circuit of claim 4, wherein the clock delay module comprises: the trigger circuit comprises a first-stage D trigger, a preset number of intermediate-stage D triggers and a last-stage D trigger;
the first-stage D flip-flop is configured to receive the source clock signal and the frequency-divided clock signal, perform phase delay on the frequency-divided clock signal according to the source clock signal, generate a path of phase delay signal with a phase delayed by a preset phase difference from the frequency-divided clock signal, and output the phase delay signal to the outside of the clock circuit and a next-stage D flip-flop at the same time;
each intermediate-stage D flip-flop is configured to receive the source clock signal and the phase delay signal output by the previous-stage D flip-flop, perform phase delay on the phase delay signal according to the source clock signal, generate a path of phase delay signal with a phase delay that is a preset phase difference from the phase delay signal output by the previous-stage D flip-flop, and output the phase delay signal to the outside of the clock circuit and the next-stage D flip-flop at the same time;
the last stage D trigger is used for receiving the source clock signal and the phase delay signal output by the previous stage D trigger, performing phase delay on the phase delay signal according to the source clock signal, generating a path of phase delay signal with a phase delay which is a preset phase difference compared with the phase delay signal output by the previous stage D trigger, and outputting the phase delay signal to the outside of the clock circuit.
6. A clock circuit generation method, comprising:
receiving hardware design information and constraint information aiming at a clock circuit, wherein the hardware design information comprises a clock creation instruction, a clock frequency division instruction and a clock delay instruction;
adding a clock creating module in a basic circuit according to the clock creating instruction, wherein the clock creating module is used for generating a source clock signal with a preset frequency and outputting the source clock signal to the clock frequency dividing module and the clock delay module;
adding a clock frequency division module in the basic circuit according to the clock frequency division instruction, wherein the clock frequency division module is used for carrying out even frequency division of preset multiple on the source clock signal output by the clock creation module to generate a frequency division clock signal, and outputting the frequency division clock signal to a clock circuit external module and the clock delay module simultaneously;
adding a clock delay module in the basic circuit according to the clock delay instruction, wherein the clock delay module is used for generating phase delay signals with a preset number according to the source clock signal output by the clock creation module and the frequency division clock signal output by the clock frequency division module, and outputting the phase delay signals to the clock circuit external module;
and determining the connection relation among the clock creating module, the clock frequency dividing module and the clock delay module in the basic circuit according to the constraint information to generate a clock circuit.
7. The method of claim 6, the constraint information comprising: clock creation constraint information, clock frequency division constraint information, clock delay constraint information, phase relation constraint information and register constraint information;
the clock creating constraint information comprises creating a source clock with a preset frequency;
the clock frequency division constraint information comprises even number frequency division of preset multiple for the source clock to generate a frequency division clock;
the clock delay constraint information comprises defining a clock generated in a previous-stage component as a source clock, delaying the source clock by using the source clock, and generating a phase delay clock with a phase delay which is a preset phase difference with respect to the source clock;
the phase relation constraint information comprises setting the frequency division clock and the phase delay clock as synchronous clocks to form a clock group; setting the source clock and the clock group as asynchronous clocks;
the register constraint information includes instantiating the associated register.
8. A clock circuit generation apparatus, comprising:
the information receiving module is used for receiving hardware design information and constraint information aiming at a clock circuit, wherein the hardware design information comprises a clock creation instruction, a clock frequency division instruction and a clock delay instruction;
a clock creating module adding module, configured to add a clock creating module in a basic circuit according to the clock creating instruction, where the clock creating module is configured to generate a source clock signal with a preset frequency and output the source clock signal to the clock frequency dividing module and the clock delay module;
a clock frequency division module adding module, configured to add a clock frequency division module in the basic circuit according to the clock frequency division instruction, where the clock frequency division module is configured to perform even frequency division of a preset multiple on the source clock signal output by the clock creating module, generate a frequency division clock signal, and output the frequency division clock signal to a clock circuit external module and the clock delay module at the same time;
a clock delay module adding module, configured to add a clock delay module to the basic circuit according to the clock delay instruction, where the clock delay module is configured to generate a preset number of phase delay signals according to the source clock signal output by the clock creating module and the frequency division clock signal output by the clock frequency division module, and output the phase delay signals to the clock circuit external module;
and the clock circuit generating module is used for determining the connection relation among the clock creating module, the clock frequency dividing module and the clock delay module in the basic circuit according to the constraint information to generate a clock circuit.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the clock circuit generation method according to any one of claims 6 to 7 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the clock circuit generation method of any one of claims 6 to 7.
CN202011615548.9A 2020-12-30 2020-12-30 Clock circuit and clock circuit generating method, device, equipment and medium Pending CN112737571A (en)

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