US20020113272A1 - Embedded type flash memory structure and method for operating the same - Google Patents

Embedded type flash memory structure and method for operating the same Download PDF

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US20020113272A1
US20020113272A1 US09/781,430 US78143001A US2002113272A1 US 20020113272 A1 US20020113272 A1 US 20020113272A1 US 78143001 A US78143001 A US 78143001A US 2002113272 A1 US2002113272 A1 US 2002113272A1
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doped
region
voltage
line voltage
flash memory
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Ching-Hsiang Hsu
Ching-Sung Yang
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Powerchip Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM

Definitions

  • the present invention relates to a non-volatile memory structure and, more particularly, to a flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
  • Flash memories have been widely used in small electronic products such as notebook computers or digital cameras. Moreover, along with the trend of miniaturization of electronic products, the sizes of flash memories need to be smaller and smaller. However, when small-size flash memories are manufactured by means of sub-micrometer fabrication technology, the transistors of memory cells in the memory cell array must be operated at a small voltage about 3V because of short channel effects.
  • FIG. 1 shows a memory cell structure of a prior art flash memory.
  • N-type doped-regions used as a source 12 and a drain 14 are formed in a p-type semiconductor substrate 10 , and a channel is formed in the substrate 10 between the source 12 and drain 14 .
  • a silicon dioxide layer 16 , a trapping layer 18 (e.g., silicon nitride), and a silicon dioxide layer 20 are formed in turn on the surface of the substrate 10 .
  • a control gate 22 is then formed on the surface of the silicon dioxide layer 20 .
  • the operational voltage of a prior art flash memory cannot be easily reduced so that the operational voltage is too high.
  • the structure of the memory cell array is required to be denser and denser so that the channel length is reduced therewith, resulting in mutual influence of operation between each memory cell. If the operational voltage cannot be relatively reduced, short channel effects will arise so that the phenomenon of punch through will occur.
  • complex design of peripheral circuits is required for higher operational voltages, the above high-voltage operational method will complicate the design of peripheral circuits.
  • the simplest way to resolve the above short channel effects is to reduce the operational voltage or to change the operational mode to facilitate the miniaturization of memory cell. Accordingly, the present invention proposes an improved structure of flash memory cell and a method for operating the same to resolve the above problems in the prior art.
  • the primary object of the present invention is to provide an improved structure of flash memory cell and a method for operating the same.
  • a shallow doped-region is added below the doped-region used as the drain. Using these two different doped-regions to share the voltage, the voltage can be controlled and the operational voltage of the memory cell can be reduced. Moreover, the design of peripheral circuits will be simpler.
  • Another object of the present invention is to provide an embedded type flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same.
  • an n-well is formed in a p-type substrate.
  • a shallow p-well is formed in the n-well, and a drain and a source of shallower n-type doped-regions are formed in the shallow p-well and the n-well, respectively.
  • a dielectric insulating layer and a poly-silicon gate are stacked above the n-well to connect all the drains.
  • FIG. 1 is a diagram of the memory cell structure of a prior art flash memory
  • FIG. 2 is a diagram of the flash memory cell structure of the present invention.
  • FIG. 3 is a diagram of the memory array of the present invention.
  • FIGS. 4 (A), 4 (B), and 4 (C) show the programming process, the erasing process, and the reading process according to an embodiment of the present invention, respectively.
  • the present invention is characterized in that a second doped-region is added to share the voltage of a first shallow doped-region used as a drain to reduce the operational voltage of the memory cell so that both the effects of low operational voltage and high density can be achieved.
  • a flash memory cell structure is shown in FIG. 2.
  • a first deep doped-region is formed in a p-type semiconductor substrate 32 by means of ion implantation.
  • the first doped-region is an n-well 34 .
  • a second doped-region is formed in the n-well 34 .
  • the second doped-region is a shallow p-well 35 .
  • N-type ions are implanted in the surface of the n-well 34 and the shallow p-well 35 to form first shallow doped-regions.
  • the first shallow doped-region in the n-well 34 is used as a source 38
  • the first shallow doped-region in the shallow p-well 35 is used as a drain 36 .
  • the doping depth of the n-well 34 is much larger than that of the first shallow doped-region used as the drain 36 .
  • a dielectric insulating layer 40 is stacked above the n-well 34 between the drain 36 and the source 38 .
  • the dielectric insulating layer 40 comprises a silicon oxide layer 42 , a trapping layer 44 (usually being silicon nitride), and a silicon oxide layer 46 .
  • the dielectric insulating layer 40 is thus called an oxide-nitride-oxide film, briefly termed an ONO film.
  • a gate 48 such as highly doped poly-silicon is used to connect all the drains 36 . Because of the functions of the n-type drain 36 and the shallow p-well 35 thereunder, the original higher voltage in the prior art drain is split into two parts so that the operational voltage can be effectively reduced. The operational voltage will be clearly described below.
  • the poly-silicon gate 48 of the flash memory cell 30 forms a word line 50
  • the drain 36 forms a bit line 52 .
  • a shallow p-well 35 is implanted below the n-type drain 36 between every two adjacent word lines 50 . Every two word lines 50 share a shallow p-well 35 .
  • the object of reducing the operational voltage is accomplished by individually applying voltages to the shallow p-well 35 and the bit line 52 .
  • the above trapping layer 42 in the dielectric insulating layer 40 is used as a charge-storing region for accepting and keeping electrons or holes injected into the dielectric insulating layer 40 so as to perform the programming or erasing process.
  • a source line voltage V S , a bit line voltage V BL , and a word line voltage V WL are applied to the source 38 , the drain 36 , and the gate 48 of the flash memory cell 30 , respectively.
  • a shallow p-well voltage V PW is also applied to the shallow p-well 35 to facilitate the operations of programming, erasing, and reading of the memory cell 30 .
  • FIG. 4(A) shows a programming process of the flash memory cell 30 .
  • a positive bit line voltage V BL about 2 ⁇ 5V, e.g., V BL 2.5V, is applied to the drain 36 .
  • a sufficiently large negative voltage about ⁇ 2 ⁇ 5V, e.g., V PW ⁇ 2.5V, is applied to the p-well 35 .
  • BTBT band-to-band tunneling
  • FIG. 4(B) shows an erasing process of the flash memory cell 30 .
  • the bit line voltage V BL is a floating state.
  • a negative voltage about ⁇ 3 ⁇ 7V, e.g., V PW ⁇ 5V, is applied to the p-well. This sufficiently large negative voltage and the OV of the drain and the channel are exploited so that a sufficiently large BTBT current can be generated in the channel region.
  • FIG. 4(C) shows a reading process of the flash memory cell 30 .
  • the word line voltage V WL of a positive voltage about 2 ⁇ 5V, e.g., V WL 3.3V, is applied to the gate 48 .
  • the present invention exploits the functions of an n-type drain and another shallow doped p-well to respectively control and share the voltage so as to reduce the operational voltage of the flash memory cell.
  • the design of peripheral circuits can also be simplified. Because short channel effects or the phenomenon of punch through will not occur in the present invention, the miniaturization of the memory cell can be enhanced so that both the effects of high density and low operational voltage can be achieved.
  • the present invention uses a flash memory cell having a p-type semiconductor substrate to illustrate the structure and the operational method of the present invention.
  • the present invention can also use a flash memory cell having an n-type semiconductor substrate to achieve the same effect.
  • the flash memory cell having an n-type semiconductor substrate the first deep doped-region and the first shallow doped-region are changed to be p-type doped-regions, and the second doped-region is a corresponding n-type doped-region.
  • the other structure and the relevant positions are the same as above and thus will not be further illustrated.
  • the operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished by only applying voltages reverse to those of the above flash memory cell having a p-type semiconductor substrate. That is, during the operational process, positive and negative voltages applied to the flash memory cell having a p-type semiconductor substrate are respectively changed to negative and positive voltages, and original zero voltages, ground states, and floating states are kept invariant. Thereby, the operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished through these reverse operational voltages.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The present invention provides an embedded type flash memory structure and a method for operating the same. The memory structure of the present invention comprises a first deep doped-region formed on the surface of a semiconductor substrate. A second doped-region is implanted in the first deep doped-region. A plurality of first shallow doped-regions are respectively formed in the second doped-region and the first deep doped-region to be used as drains and sources. A dielectric insulating layer and a poly-silicon gate are stacked above the first deep doped-region between the source and the drain. The present invention also proposes programming, erasing, and reading processes corresponding to the flash memory cell structure.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a non-volatile memory structure and, more particularly, to a flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same. [0001]
    • BACKGROUND OF THE INVENTION
  • Flash memories have been widely used in small electronic products such as notebook computers or digital cameras. Moreover, along with the trend of miniaturization of electronic products, the sizes of flash memories need to be smaller and smaller. However, when small-size flash memories are manufactured by means of sub-micrometer fabrication technology, the transistors of memory cells in the memory cell array must be operated at a small voltage about 3V because of short channel effects. [0002]
  • FIG. 1 shows a memory cell structure of a prior art flash memory. N-type doped-regions used as a [0003] source 12 and a drain 14 are formed in a p-type semiconductor substrate 10, and a channel is formed in the substrate 10 between the source 12 and drain 14. A silicon dioxide layer 16, a trapping layer 18 (e.g., silicon nitride), and a silicon dioxide layer 20 are formed in turn on the surface of the substrate 10. A control gate 22 is then formed on the surface of the silicon dioxide layer 20. When a programming process is performed to the memory cell, a sufficiently large voltage must be applied to the drain and the source so that the above action can be accomplished by means of the channel formed by this high voltage difference. Therefore, the operational voltage of a prior art flash memory cannot be easily reduced so that the operational voltage is too high. Moreover, the structure of the memory cell array is required to be denser and denser so that the channel length is reduced therewith, resulting in mutual influence of operation between each memory cell. If the operational voltage cannot be relatively reduced, short channel effects will arise so that the phenomenon of punch through will occur. Furthermore, because complex design of peripheral circuits is required for higher operational voltages, the above high-voltage operational method will complicate the design of peripheral circuits.
  • The simplest way to resolve the above short channel effects is to reduce the operational voltage or to change the operational mode to facilitate the miniaturization of memory cell. Accordingly, the present invention proposes an improved structure of flash memory cell and a method for operating the same to resolve the above problems in the prior art. [0004]
    • SUMMARY OF THE INVENTION
  • The primary object of the present invention is to provide an improved structure of flash memory cell and a method for operating the same. A shallow doped-region is added below the doped-region used as the drain. Using these two different doped-regions to share the voltage, the voltage can be controlled and the operational voltage of the memory cell can be reduced. Moreover, the design of peripheral circuits will be simpler. [0005]
  • Another object of the present invention is to provide an embedded type flash memory structure having the characteristics of low operational voltage and high density and a method for operating the same. [0006]
  • According to the present invention, an n-well is formed in a p-type substrate. A shallow p-well is formed in the n-well, and a drain and a source of shallower n-type doped-regions are formed in the shallow p-well and the n-well, respectively. A dielectric insulating layer and a poly-silicon gate are stacked above the n-well to connect all the drains. [0007]
  • The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:[0008]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram of the memory cell structure of a prior art flash memory; [0009]
  • FIG. 2 is a diagram of the flash memory cell structure of the present invention; [0010]
  • FIG. 3 is a diagram of the memory array of the present invention; and [0011]
  • FIGS. [0012] 4(A), 4(B), and 4(C) show the programming process, the erasing process, and the reading process according to an embodiment of the present invention, respectively.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention is characterized in that a second doped-region is added to share the voltage of a first shallow doped-region used as a drain to reduce the operational voltage of the memory cell so that both the effects of low operational voltage and high density can be achieved. [0013]
  • A flash memory cell structure is shown in FIG. 2. A first deep doped-region is formed in a p-[0014] type semiconductor substrate 32 by means of ion implantation. The first doped-region is an n-well 34. A second doped-region is formed in the n-well 34. The second doped-region is a shallow p-well 35. N-type ions are implanted in the surface of the n-well 34 and the shallow p-well 35 to form first shallow doped-regions. The first shallow doped-region in the n-well 34 is used as a source 38, and the first shallow doped-region in the shallow p-well 35 is used as a drain 36. The doping depth of the n-well 34 is much larger than that of the first shallow doped-region used as the drain 36. A dielectric insulating layer 40 is stacked above the n-well 34 between the drain 36 and the source 38. The dielectric insulating layer 40 comprises a silicon oxide layer 42, a trapping layer 44 (usually being silicon nitride), and a silicon oxide layer 46. The dielectric insulating layer 40 is thus called an oxide-nitride-oxide film, briefly termed an ONO film. A gate 48 such as highly doped poly-silicon is used to connect all the drains 36. Because of the functions of the n-type drain 36 and the shallow p-well 35 thereunder, the original higher voltage in the prior art drain is split into two parts so that the operational voltage can be effectively reduced. The operational voltage will be clearly described below.
  • Please also refer to FIG. 3. The poly-[0015] silicon gate 48 of the flash memory cell 30 forms a word line 50, and the drain 36 forms a bit line 52. A shallow p-well 35 is implanted below the n-type drain 36 between every two adjacent word lines 50. Every two word lines 50 share a shallow p-well 35. The object of reducing the operational voltage is accomplished by individually applying voltages to the shallow p-well 35 and the bit line 52.
  • The [0016] above trapping layer 42 in the dielectric insulating layer 40 is used as a charge-storing region for accepting and keeping electrons or holes injected into the dielectric insulating layer 40 so as to perform the programming or erasing process.
  • The operational method corresponding to the flash memory cell structure of the present invention will be illustrated below. Please refer to FIGS. 2 and 3 simultaneously. A source line voltage V[0017] S, a bit line voltage VBL, and a word line voltage VWL are applied to the source 38, the drain 36, and the gate 48 of the flash memory cell 30, respectively. A shallow p-well voltage VPW is also applied to the shallow p-well 35 to facilitate the operations of programming, erasing, and reading of the memory cell 30.
  • FIG. 4(A) shows a programming process of the [0018] flash memory cell 30. A positive bit line voltage VBL about 2˜5V, e.g., VBL=2.5V, is applied to the drain 36. The source line voltage is a ground state (VS=0) . A sufficiently large negative voltage about −2˜−5V, e.g., VPW=−2.5V, is applied to the p-well 35. A negative word line voltage about −2˜−7V, e.g., VWL=−3.3V, is also exploited to generate a sufficiently large band-to-band tunneling (BTBT) current between the interfaces of the gate 48 and the drain 36 and the shallow p-well 35 so that induced thermal holes will pass through the silicon oxide layer 42 to let the holes be trapped in the charge-storing region of the trapping layer 44. Thereby, the charge status after the programming process can be stored to achieve the function of programming.
  • FIG. 4(B) shows an erasing process of the [0019] flash memory cell 30. The bit line voltage VBL is a floating state. The source line voltage is a ground state (VS=0). The word line voltage VWL is a sufficiently large positive voltage about 2˜5V, e.g., VWL=3.3V. Thereby, a device channel will be formed. A negative voltage about −3˜−7V, e.g., VPW=−5V, is applied to the p-well. This sufficiently large negative voltage and the OV of the drain and the channel are exploited so that a sufficiently large BTBT current can be generated in the channel region. Part of hot electrons will be attracted by the sufficiently large vertical electric field of the word line voltage VWL to pass the energy barrier of the silicon oxide layer 42 and reach the trapping layer 44 to be trapped in the same charge-storing region as that in the above programming process of the trapping layer 44. Thereby, holes in the charge-storing region can be compensated. The operation of erasing is thus completed.
  • FIG. 4(C) shows a reading process of the [0020] flash memory cell 30. The word line voltage VWL of a positive voltage about 2˜5V, e.g., VWL=3.3V, is applied to the gate 48. The bit line voltage is a ground state (VBL=0). The source line voltage Vs is a lower positive voltage (VS=1V). The voltage of the p-well Vpw is a ground state (VPW=0). The operation of reading to the bit of the flash memory cell 30 is thus completed.
  • The present invention exploits the functions of an n-type drain and another shallow doped p-well to respectively control and share the voltage so as to reduce the operational voltage of the flash memory cell. The design of peripheral circuits can also be simplified. Because short channel effects or the phenomenon of punch through will not occur in the present invention, the miniaturization of the memory cell can be enhanced so that both the effects of high density and low operational voltage can be achieved. [0021]
  • The present invention uses a flash memory cell having a p-type semiconductor substrate to illustrate the structure and the operational method of the present invention. The present invention can also use a flash memory cell having an n-type semiconductor substrate to achieve the same effect. In the flash memory cell having an n-type semiconductor substrate, the first deep doped-region and the first shallow doped-region are changed to be p-type doped-regions, and the second doped-region is a corresponding n-type doped-region. The other structure and the relevant positions are the same as above and thus will not be further illustrated. The operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished by only applying voltages reverse to those of the above flash memory cell having a p-type semiconductor substrate. That is, during the operational process, positive and negative voltages applied to the flash memory cell having a p-type semiconductor substrate are respectively changed to negative and positive voltages, and original zero voltages, ground states, and floating states are kept invariant. Thereby, the operations of programming, erasing, and reading of the flash memory cell having an n-type semiconductor substrate can be accomplished through these reverse operational voltages. [0022]
  • Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims. [0023]

Claims (12)

I claim:
1. An embedded type flash memory structure, comprising:
a semiconductor substrate;
a first deep doped-region formed on the surface of said semiconductor substrate;
a plurality of first shallow doped-regions formed in said first deep doped-region and respectively used as sources and drains;
a second doped-region formed in said first deep doped-region and below said first shallow doped-region used as a drain to enclose the drain;
a dielectric insulating layer stacked above said first deep doped-region and connecting said first shallow doped-region; and
a poly-silicon layer formed on the surface of said dielectric insulating layer and used as a gate.
2. The embedded type flash memory structure as claimed in claim 1, wherein
said semiconductor substrate can be a p-type semiconductor material or an n-type semiconductor material.
3. The embedded type flash memory structure as claimed in claim 1, wherein
said first deep doped-region and said first shallow doped-region are doped with first type ions, and said semiconductor substrate and said second doped-region are doped with second type ions, said first type ions being different from said second type ions.
4. The embedded type flash memory structure as claimed in claim 2 or 3, wherein when said semiconductor substrate is a p-type semiconductor substrate, said first deep doped-region and said first shallow doped-region are n-type doped-regions, and said second doped-region is a corresponding p-type doped-region.
5. The embedded type flash memory structure as claimed in claim 2 or 3, wherein when said semiconductor substrate is an n-type semiconductor substrate, said first deep doped-region and said first shallow doped-region are p-type doped-regions, and said second doped-region is a corresponding n-type doped-region.
6. The embedded type flash memory structure as claimed in claim 1, wherein the doping depth of said first deep doped-region is much larger than that of said first shallow doped-region.
7. The embedded type flash memory structure as claimed in claim 1, wherein said dielectric insulating layer comprises a silicon oxide layer, a trapping layer, and a silicon oxide layer.
8. The embedded type flash memory structure as claimed in claim 1, wherein said dielectric insulting layer is used a charge-storing region for accepting and keeping holes injected thereinto.
9. An operational method of an embedded type flash memory, said flash memory being a p-type semiconductor substrate having a first deep doped-region as a source, a first shallow doped-region as a drain, a second doped-region, and a poly-silicon gate formed thereon, a source line voltage, a bit line voltage, a doped well voltage, and a word line voltage being respectively applied to said source, said drain, said second doped-region, and said gate, said operational method comprising the steps of:
performing a programming process, wherein said word line voltage is a negative voltage, said bit line voltage is a positive voltage, said doped well voltage is a negative voltage, and said source line voltage is a ground state;
performing an erasing process, wherein said word line voltage is a positive voltage, said bit line voltage is a floating state, said doped well voltage is a negative voltage, and said source line voltage is a ground state; and
performing a reading process, wherein said word line voltage is a positive voltage, said bit line voltage and said doped well voltage are ground states, and said source line voltage is a lower positive voltage.
10. The operational method as claimed in claim 9, wherein the voltages shared by said bit line voltage and said doped well voltage can be controlled according to necessity when performing said programming, erasing, and reading processes.
11. An operational method of an embedded type flash memory, said flash memory being an n-type semiconductor substrate having a first deep doped-region as a source, a first shallow doped-region as a drain, a second doped-region, and a poly-silicon gate formed thereon, a source line voltage, a bit line voltage, a doped well voltage, and a word line voltage being respectively applied to said source, said drain, said second doped-region, and said gate, said operational method comprising the steps of:
performing a programming process, wherein said word line voltage is a positive voltage, said bit line voltage is a negative voltage, said doped well voltage is a positive voltage, and said source line voltage is a ground state;
performing an erasing process, wherein said word line voltage is a negative voltage, said bit line voltage is a floating state, said doped well voltage is a positive voltage, and said source line voltage is a ground state; and
performing a reading process, wherein said word line voltage is a negative voltage, said bit line voltage and said doped well voltage are ground states, and said source line voltage is a lower negative voltage.
12. The operational method as claimed in claim 11, wherein the voltages shared by said bit line voltage and said doped well voltage can be controlled according to necessity when performing said programming, erasing, and reading processes.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040161896A1 (en) * 2002-07-03 2004-08-19 Jiun-Ren Lai [structure of a memory device and fabrication method thereof]
WO2004105092A2 (en) * 2003-05-14 2004-12-02 Fairchild Semiconductor Corporation Esd protection for semiconductor products
US20050093055A1 (en) * 2003-11-05 2005-05-05 Leo Wang Flash memory and method thereof
US20110116323A1 (en) * 2006-12-27 2011-05-19 Yukio Hayakawa Semiconductor device, method of controlling the same, and method of manufacturing the same
US20110267897A1 (en) * 2006-11-20 2011-11-03 Taiwan Semiconductor Manufacturing Company Ltd. Non-Volatile Memory Cells Formed in Back-End-of-Line Processes

Families Citing this family (13)

* Cited by examiner, † Cited by third party
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US6742617B2 (en) * 2000-09-25 2004-06-01 Skywalker Robotics, Inc. Apparatus and method for traversing compound curved and other surfaces
TW495977B (en) * 2001-09-28 2002-07-21 Macronix Int Co Ltd Erasing method for p-channel silicon nitride read only memory
US7782668B2 (en) * 2007-11-01 2010-08-24 Jonker Llc Integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
US7974127B2 (en) * 2007-11-06 2011-07-05 Macronix International Co., Ltd. Operation methods for memory cell and array for reducing punch through leakage
US7876615B2 (en) * 2007-11-14 2011-01-25 Jonker Llc Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data
US7852672B2 (en) * 2007-11-14 2010-12-14 Jonker Llc Integrated circuit embedded with non-volatile programmable memory having variable coupling
US8580622B2 (en) * 2007-11-14 2013-11-12 Invensas Corporation Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling
US7787295B2 (en) * 2007-11-14 2010-08-31 Jonker Llc Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling
US8305805B2 (en) * 2008-11-03 2012-11-06 Invensas Corporation Common drain non-volatile multiple-time programmable memory
US8203861B2 (en) 2008-12-30 2012-06-19 Invensas Corporation Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit
US8471328B2 (en) 2010-07-26 2013-06-25 United Microelectronics Corp. Non-volatile memory and manufacturing method thereof
US8988103B2 (en) 2010-09-15 2015-03-24 David K. Y. Liu Capacitively coupled logic gate
US9305931B2 (en) 2011-05-10 2016-04-05 Jonker, Llc Zero cost NVM cell using high voltage devices in analog process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5677215A (en) * 1993-11-17 1997-10-14 Lg Semicon Co., Ltd. Method of fabricating a nonvolatile semiconductor memory device
US5751631A (en) * 1996-10-21 1998-05-12 Liu; David K. Y. Flash memory cell and a new method for sensing the content of the new memory cell
US5999443A (en) * 1997-02-01 1999-12-07 Holtek Semiconductor Inc. Low-voltage triple-well non-volatile semiconductor memory
US5956271A (en) * 1997-12-12 1999-09-21 Texas Instruments Incorporated Channel hot electron programmed memory device having improved reliability and operability
US6091101A (en) * 1998-03-30 2000-07-18 Worldwide Semiconductor Manufacturing Corporation Multi-level flash memory using triple well
TW406424B (en) * 1998-09-28 2000-09-21 United Microelectronics Corp Manufacture of the flash memory
US6262914B1 (en) * 1999-08-11 2001-07-17 Texas Instruments Incorporated Flash memory segmentation

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040161896A1 (en) * 2002-07-03 2004-08-19 Jiun-Ren Lai [structure of a memory device and fabrication method thereof]
US6849526B2 (en) * 2002-07-03 2005-02-01 Macronix International Co., Ltd. Method of improving device resistance
WO2004105092A2 (en) * 2003-05-14 2004-12-02 Fairchild Semiconductor Corporation Esd protection for semiconductor products
WO2004105092A3 (en) * 2003-05-14 2005-10-06 Fairchild Semiconductor Esd protection for semiconductor products
US20050093055A1 (en) * 2003-11-05 2005-05-05 Leo Wang Flash memory and method thereof
US20110267897A1 (en) * 2006-11-20 2011-11-03 Taiwan Semiconductor Manufacturing Company Ltd. Non-Volatile Memory Cells Formed in Back-End-of-Line Processes
US8247293B2 (en) * 2006-11-20 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory cells formed in back-end-of-line processes
US20110116323A1 (en) * 2006-12-27 2011-05-19 Yukio Hayakawa Semiconductor device, method of controlling the same, and method of manufacturing the same
US8716082B2 (en) * 2006-12-27 2014-05-06 Spansion Llc Semiconductor device, method of controlling the same, and method of manufacturing the same
US20150001611A1 (en) * 2006-12-27 2015-01-01 Spansion Llc Semiconductor device, method of controlling the same, and method of manufacturing the same
US9472564B2 (en) * 2006-12-27 2016-10-18 Cypress Semiconductor Corporation System with memory having voltage applying unit

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