CN108269808B - SONOS device and manufacturing method thereof - Google Patents
SONOS device and manufacturing method thereof Download PDFInfo
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- CN108269808B CN108269808B CN201810024869.8A CN201810024869A CN108269808B CN 108269808 B CN108269808 B CN 108269808B CN 201810024869 A CN201810024869 A CN 201810024869A CN 108269808 B CN108269808 B CN 108269808B
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Abstract
The invention discloses an SONOS device.A first grid structure of a selection tube of a storage unit is formed in a shallow trench, and a second grid structure of the storage tube and a second channel region at the bottom are formed on the second side of the first grid structure; two sides of the first grid structure and the second grid structure comprise only two source-drain injection regions, so that the memory unit can be in a 1.5T-shaped structure, and the area of a device can be reduced. The first polysilicon gate and the second polysilicon gate of the first gate structure are not overlapped longitudinally and transversely, so that electric leakage between the first polysilicon gate and the second polysilicon gate can be reduced, power consumption of a device is reduced, reliability of the device is improved, quality requirements for an insulating layer between the first polysilicon gate and the second polysilicon gate are reduced, and mutual interference between the first polysilicon gate and the second polysilicon gate can be prevented. The invention also discloses a manufacturing method of the SONOS device.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a SONOS device; the invention also relates to a SONOS device and a manufacturing method thereof.
Background
Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile memory with low operating voltage and better COMS process compatibility is widely applied to various embedded electronic products such as financial IC cards, automotive electronics and the like. The currently common memory cell structure is composed of a complete storage tube and a complete selection-gate (SG) to form a 2-transistor structure (2transistors, 2T), i.e. a 2T-type SONOS nonvolatile memory, each transistor has a complete source, drain and gate, and the two transistors share a layer of polysilicon. Threshold voltage (Vt) of a storage tube in the depletion type SONOS nonvolatile memory is less than 0, Vt of a selection tube is still greater than 0, and the 2T depletion type SONOS nonvolatile memory is favored by a plurality of low-power consumption applications due to low power consumption. But the inherent disadvantage of the 2T structure is its large chip area loss.
As shown in fig. 1, the structure diagram of a memory cell of a conventional 2T depletion type SONOS nonvolatile memory includes:
a storage tube 301 and a selection tube 302 formed on a P-type semiconductor substrate such as a silicon substrate 9;
the gate structure of the storage tube 301 includes an ONO layer and a polysilicon gate 1, the ONO layer is composed of an oxide layer (O)6, a nitride layer (N)5 and an oxide layer (O)4, the oxide layer 6 is generally called a tunneling oxide layer for storing charge tunneling, the nitride layer 5 is used as a storage layer, and the oxide layer 4 is generally called a blocking oxide layer.
The gate structure of the select transistor 302 includes a gate oxide layer 7 and a polysilicon gate 1 a. Generally, the polysilicon gate 1a and the polysilicon gate 1 are formed simultaneously. Side walls are also formed on the sides of the polysilicon gates 1 and 1a, the side walls are usually formed by oxide layers or nitride layers, and in fig. 1, the side walls include 3 layers of structures, namely an oxide layer 21, a nitride layer 22 and an oxide layer 23.
The channel region of the storage tube 301 includes an N-type implant region 10, and the N-type implant region 10 makes the channel region N-type doped, thereby making the storage tube 301 a depletion structure.
In fig. 1, the channel region of the selection tube 302 is doped directly by the P-type semiconductor substrate 9, or the P-type impurity modulation may be performed alone, so that the selection tube 302 has an enhancement structure with a threshold voltage greater than 0V.
An N-type lightly doped source drain (LDD) region 11 and an N-type heavily doped source drain region 8 are formed in a self-aligned manner on both sides of the polysilicon gates 1 and 1a, and in fig. 1, the LDD11 and the source drain region 8 between the polysilicon gates 1 and 1a are used as a common doping structure for the storage tube 301 and the selection tube 302.
As shown in fig. 1, the two polysilicon gates 1 and 1a in the 2T structure include common doped regions, i.e., LDD11 and source drain regions 8, which makes the polysilicon gates 1 and 1a have a larger spacing, and thus occupy a larger area and bring a larger chip area loss. Compared with a 2T structure, the 1.5T structure occupies a smaller chip area, and the conventional 1.5T type SONOS non-volatile memory generally has two types:
in the first structure, the Vt of the storage tube and the select-gate (sg) are both greater than zero V, in which case the select tube and the storage tube can share the same channel, but since the Vt of the storage tube is greater than zero V, a higher positive voltage must be applied to the gate (gate) of the storage tube during the read operation, and thus the power consumption is higher. Because the 2T depletion type SONOS non-volatile memory is adopted in the low-power consumption 2T SONOS non-volatile memory, when the memory is read, the gate of the storage tube is connected with zero potential, and data can be read, because the Vt of an erasing state is less than 0, and the Vt of a programming state is more than 0, namely Vte <0& Vtp >0, wherein Vte is the threshold voltage of the erasing state, and Vtp is the threshold voltage of the programming state.
In the second structure, a depletion type storage tube with Vt less than 0V is adopted as the storage tube; the selection tube adopts an enhanced selection tube with Vt larger than 0V, and the 1.5T type SONOS non-volatile memory is a SONOS device. As shown in fig. 2, it is a structure diagram of a memory cell of a conventional SONOS device; the difference from the structure shown in fig. 1 is that the polysilicon gates 1 and 1a of the memory cell 201 in fig. 2 are isolated by a sidewall, and the sidewall between the polysilicon gates 1 and 1a in fig. 2 is composed of an oxide layer 24 and a nitride layer 25. The LDD11 and source drain regions 8 are no longer formed on the surface of the P-type semiconductor substrate 9 between the polysilicon gates 1 and 1 a. An oxide layer 3 is formed on top of the polysilicon gate 1. A nitride layer 26 and an oxide layer 27 are also formed on both side surfaces of the polysilicon gate 1, and an oxide layer 24a, a silicon nitride 26, and an oxide layer 27 are formed on the side surface of the polysilicon gate 1a on the side away from the polysilicon gate 1. In fig. 2, one source drain region 8 is saved, and the source drain regions 8 on both sides of the polysilicon gates 1a and 1 need to be conducted through a channel formed by connecting a part of the channel covered by the polysilicon gate 1a and a part of the channel covered by the polysilicon gate 1 in series, so that the source drain region 8 does not need to be additionally arranged between the polysilicon gates 1 and 1a, and the structure shown in fig. 2 is also called as a 1.5T type. Saving one source drain region 8 enables the spacing between the polysilicon gates 1 and 1a to be made very small. However, as shown in fig. 2, since the polysilicon gate 1 controls the channel region at the bottom and forms a channel on the surface with a threshold voltage different from that of the polysilicon gate 1a which controls the channel region at the bottom and forms a channel on the surface, the doping structures of the channel regions corresponding to the bottoms of the polysilicon gates 1 and 1a are different, and in fig. 2, the channel region at the bottom of the polysilicon gate 1 is composed of an N-type implantation region 10, so that the threshold voltage corresponding to the polysilicon gate 1 in an unprogrammed state is smaller than 0V; the channel region at the bottom of the polysilicon gate 1a is composed of a P-type region, and is directly composed of a P-type semiconductor substrate 9 in fig. 2, so that the threshold voltage corresponding to the polysilicon gate 1a is greater than 0V.
Fig. 3 is a diagram illustrating an array structure of the SONOS device shown in fig. 2; fig. 3 shows 4 memory cells 201, which are respectively denoted by Cell a, Cell B, Cell C, and Cell D, and the source drain region 8 adjacent to the polysilicon gate 1a of the select transistor is a first source drain region, and the source drain region 8 adjacent to the polysilicon gate 1 of the memory transistor is a second source drain region, as can be seen from fig. 3:
the second source drain region of each memory cell 201 in the same column is connected to the Bit Line (BL) of the corresponding column, two bit lines are shown in fig. 3, and are respectively denoted by BL1 and BL 2.
The polysilicon gates 1a of the memory cells 201 in the same row are connected to corresponding memory Word Lines (WLS) in the same row, two memory word lines WLS are shown in fig. 3, and are respectively denoted by WLS1 and WLS 2; the polysilicon gates 1 of the memory cells 201 in the same row are all connected to the corresponding select Word Lines (WL) in the same row, two of which are shown in fig. 3 and are denoted by WL1 and WL2, respectively; the first source-drain regions of the memory cells 201 in the same row are all connected to the source line SL of the corresponding row.
The P-type semiconductor substrate 9 of all the memory cells 201 is connected to a substrate electrode line VBPW.
Watch 1
The programming, erasing and reading operations of Cell a in fig. 3 are exemplified to illustrate the voltages that the memory Cell structure shown in fig. 2 is subjected to in various operating states, and the programming, erasing and reading voltages are set according to the bias manner in table one, as can be seen from table one, when Cell a is programmed, memory word line WLS is added with 7.2V, and select word line WL is added with-4.5V, so that finally a voltage difference of 11.7V is formed between polysilicon gates 1 and 1 a. As shown in fig. 2, the polysilicon gates 1 and 1a are adjacent in the transverse direction, the side surfaces are overlapped in the longitudinal direction, and the polysilicon gates 1 and 1a are isolated by the side wall composed of the oxide layer 24 and the nitride layer 25, so that the voltage difference of 11.7V puts high requirements on the side wall material for isolating the polysilicon gates 1 and 1a, and the high voltage for a long time can degrade the performance of the device and affect the reliability of the device. In addition, the back-to-back structure of the polysilicon gates 1 and 1a shown in fig. 2 is also easy to cause leakage between the polysilicon gates 1 and 1a and to have the defect of mutual interference, which affect the performance and reliability of the device.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an SONOS device, which can reduce electric leakage between polysilicon gates of a selection tube and a storage tube, avoid mutual interference between the polysilicon gates of the selection tube and the storage tube, avoid degradation of an insulating layer between the polysilicon gates of the selection tube and the storage tube, and improve the reliability of the device. Therefore, the invention also provides a manufacturing method of the SONOS device.
In order to solve the above technical problem, the present invention provides a memory cell of a storage area of a SONOS device, which includes a storage pipe and a selection pipe.
The first gate structure of the select transistor includes: the first shallow trench is formed on the surface of the second conductive type semiconductor substrate, the first gate dielectric layers are formed on the side surfaces and the bottom surfaces of the first shallow trench, the first polysilicon gate in the first shallow trench formed with the first gate dielectric layers is filled, and the first dielectric layer is formed on the surface of the first polysilicon gate.
The first channel region of the selection tube is composed of the semiconductor substrate which is located on the side surface and the bottom surface of the first shallow trench and covered by the first polysilicon gate, and the first channel region is of an enhancement type channel structure.
And a second channel region consisting of a first conductive type lightly doped region is formed on the surface of the semiconductor substrate on the first side of the first shallow trench of the first grid structure, and the second channel region is of a depletion channel structure.
And a second gate structure of the storage tube is formed at the top of the second channel region, the second gate structure comprises an ONO layer and a second polysilicon gate which are sequentially formed on the surface of the second channel region, and the ONO layer is a three-layer structure consisting of a second oxide layer, a third nitride layer and a fourth oxide layer which are sequentially formed on the surface of the second channel region.
A first source drain injection region with a first conduction type heavy doping is formed on the surface of the semiconductor substrate on the second side of the first polysilicon gate; a second source-drain injection region with a heavily doped first conductive type is formed on the surface of the semiconductor substrate on the first side of the second polysilicon gate; the first source-drain injection region and the second side of the first polysilicon gate are self-aligned; and the second source-drain injection region is self-aligned with the first side of the second polysilicon gate.
The first source-drain injection region and the second source-drain injection region are connected through the first channel region and the second channel region, and the memory unit is made to be in a 1.5T-shaped structure.
An isolation structure which is not overlapped longitudinally and transversely is formed between the first polysilicon gate and the second polysilicon gate, so that electric leakage between the first polysilicon gate and the second polysilicon gate is reduced, power consumption of a device is reduced, and reliability of the device is improved.
In a further improvement, each of the memory cells of the storage region of the SONOS device is arranged in an array structure, and the array structure is:
the adjacent memory cells on the same column share the same first source-drain injection region, and the adjacent memory cells on the same column share the same second source-drain injection region.
The second source-drain injection regions of the memory cells on the same column are all connected to the same bit line.
The first source-drain injection regions of the memory cells on the same row are all connected to the same source line.
The first polysilicon gates of each of the memory cells on the same row are connected to the same select word line.
The second polysilicon gates of each of the memory cells on the same row are connected to the same memory word line.
In a further improvement, the SONOS device further includes a logic area, and a CMOS logic transistor is formed in the logic area.
The further improvement is that the logic region is isolated by shallow trench field oxygen to form an active region of the CMOS logic tube, the shallow trench field oxygen is filled in a second shallow trench, and the second shallow trench in the logic region is identical to a first shallow trench process structure corresponding to the first gate structure of the selection tube in the storage region.
The CMOS logic tube comprises an NMOS tube and a PMOS tube, a third grid structure of the CMOS logic tube comprises a second grid dielectric layer and a third polysilicon grid, and the second polysilicon grid and the third polysilicon grid are formed simultaneously by adopting the same process.
The further improvement is that a first conductive type lightly doped drain region is also superposed in the first source drain injection region, and a first conductive type lightly doped drain region is also superposed in the second source drain injection region.
In a further improvement, a side wall is formed on a side surface of the second polysilicon gate.
The storage tube and the selection tube are both N-type devices, the first conduction type is N-type, and the second conduction type is P-type; or, the storage tube and the selection tube are both P-type devices, the first conduction type is P-type, and the second conduction type is N-type.
In order to solve the above technical problem, the present invention provides a method for manufacturing a SONOS device, in which a memory cell of a storage region of the SONOS device includes a storage pipe and a selection pipe, and the manufacturing steps include:
step one, providing a second conductive type semiconductor substrate, and forming a first shallow trench on the surface of the semiconductor substrate.
And secondly, forming a first gate dielectric layer on the side surface and the bottom surface of the first shallow trench.
Filling polycrystalline silicon in the first shallow trench to form a first polycrystalline silicon gate, and forming a first dielectric layer on the surface of the first polycrystalline silicon gate; the first shallow trench, the first gate dielectric layer and the first polysilicon gate form a first gate structure of the selection tube; the first channel region of the selection tube is composed of the semiconductor substrate which is located on the side surface and the bottom surface of the first shallow trench and covered by the first polysilicon gate, and the first channel region is of an enhancement type channel structure.
And fourthly, injecting first conductive type light doping ions into the surface of the semiconductor substrate on the first side of the first shallow groove of the first grid structure to form a second channel region, wherein the second channel region is of a depletion channel structure.
And fifthly, forming an ONO layer formed by overlapping a second oxide layer, a third nitride layer and a fourth oxide layer on the surface of the semiconductor substrate, and carrying out photoetching on the ONO layer to ensure that the ONO layer only remains in the storage area.
And sixthly, depositing to form a second polycrystalline silicon layer, wherein the second polycrystalline silicon layer is superposed on the surface of the ONO layer in the logic area.
Step seven, photoetching and etching the second polysilicon layer and the ONO layer in the storage area to form a second grid structure of the storage tube; the second grid structure comprises an ONO layer and a second polysilicon gate which are sequentially formed on the surface of the second channel region, and the second polysilicon gate consists of the etched second polysilicon layer.
Eighthly, performing source-drain injection of first conductive type heavy doping and simultaneously forming a first source-drain injection region and a second source-drain injection region, wherein the first source-drain injection region is formed on the surface of the semiconductor substrate on the second side of the first polysilicon gate; the second source-drain injection region is formed on the surface of the semiconductor substrate on the first side of the second polysilicon gate; the first source-drain injection region and the second side of the first polysilicon gate are self-aligned; and the second source-drain injection region is self-aligned with the first side of the second polysilicon gate.
The first source-drain injection region and the second source-drain injection region are connected through the first channel region and the second channel region, and the memory unit is made to be in a 1.5T-shaped structure.
An isolation structure which is not overlapped longitudinally and transversely is formed between the first polysilicon gate and the second polysilicon gate, so that electric leakage between the first polysilicon gate and the second polysilicon gate is reduced, power consumption of a device is reduced, and reliability of the device is improved.
In a further improvement, each of the memory cells of the storage region of the SONOS device is arranged in an array structure, and the array structure is:
the adjacent memory cells on the same column share the same first source-drain injection region, and the adjacent memory cells on the same column share the same second source-drain injection region.
The second source-drain injection regions of the memory cells on the same column are all connected to the same bit line.
The first source-drain injection regions of the memory cells on the same row are all connected to the same source line.
The first polysilicon gates of each of the memory cells on the same row are connected to the same select word line.
The second polysilicon gates of each of the memory cells on the same row are connected to the same memory word line.
In a further improvement, the SONOS device further includes a logic area, and a CMOS logic transistor is formed in the logic area.
In a further improvement, a second shallow trench is formed in the logic area at the same time of forming the first shallow trench in the step one; and filling an oxidation layer in the second shallow trench to form shallow trench field oxygen, and isolating the active region in the logic region by the shallow trench field oxygen.
In a further improvement, the CMOS logic tube comprises an NMOS tube and a PMOS tube;
and fifthly, after removing the ONO layer outside the storage area, performing threshold voltage adjustment injection corresponding to the CMOS logic tube in the logic area, and forming a second gate dielectric layer on the surface of the semiconductor substrate in the logic area.
And finally, in the sixth step, the second polycrystalline silicon layer is simultaneously formed on the surface of the second gate dielectric layer in the logic area.
Then, in the seventh step, the second polysilicon layer and the second dielectric layer in the logic area are simultaneously etched by lithography to form a third gate structure of the CMOS logic tube; the third gate structure of the CMOS logic tube comprises a structure formed by overlapping the second gate dielectric layer and the third polysilicon gate.
In a further improvement, before the source-drain implantation in the step eight, a step of performing a first conductivity type lightly doped drain implantation to form a first conductivity type lightly doped drain region is further included.
Then forming a side wall on the side surface of the second polysilicon gate;
and then performing source-drain implantation in the step eight.
The storage tube and the selection tube are both N-type devices, the first conduction type is N-type, and the second conduction type is P-type; or, the storage tube and the selection tube are both P-type devices, the first conduction type is P-type, and the second conduction type is N-type.
The first grid structure of the selection tube is set to be a structure formed in the shallow trench, the first channel region formed by the first grid structure covering the semiconductor substrate and the second channel region of the storage tube can be connected together, and finally the storage unit is in a 1.5T-shaped structure, so that the area of the device can be reduced.
In addition, the first grid structure with the shallow groove can realize that the first polysilicon gate of the first grid structure of the selection tube and the second polysilicon gate of the second grid structure of the storage tube are not overlapped in the longitudinal direction and the transverse direction, so that the first polysilicon gate and the second polysilicon gate form good physical isolation; in addition, because the first polysilicon gate and the second polysilicon gate are in a non-overlapping physical isolation structure, the degradation of an isolation insulating layer between the first polysilicon gate and the second polysilicon gate caused by high voltage between the first polysilicon gate and the second polysilicon gate can be avoided, so that the reliability of a device can be improved, the quality requirement on the isolation insulating layer between the first polysilicon gate and the second polysilicon gate is reduced, and the manufacturing process can be simplified; in addition, the first polysilicon gate and the second polysilicon gate are in a non-overlapped physical isolation structure, and mutual interference between the first polysilicon gate and the second polysilicon gate can be avoided.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a diagram of a memory cell structure of a conventional 2T depletion type SONOS non-volatile memory;
FIG. 2 is a diagram of a memory cell structure of a prior art SONOS device;
FIG. 3 is a diagram of an array structure of the prior art SONOS device shown in FIG. 2;
FIG. 4 is a diagram of a memory cell structure of a SONOS device according to an embodiment of the present invention;
FIG. 5 is a diagram of an array structure of the SONOS device of the embodiment of the invention shown in FIG. 4;
fig. 6A-6B are memory cell structure diagrams in steps of a method for manufacturing a SONOS device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 4, it is a structural diagram of a memory cell 401 of a SONOS device according to an embodiment of the present invention; FIG. 5 is a diagram of an array structure of the SONOS device of the embodiment of the invention shown in FIG. 4; the memory cell 401 of the storage area of the SONOS device according to the embodiment of the present invention includes a storage pipe and a selection pipe.
The first gate structure of the select transistor includes: the structure comprises a first shallow trench formed on the surface of a second conductive type semiconductor substrate such as a silicon substrate 101, a first gate dielectric layer such as a gate oxide layer 102 formed on the side surface and the bottom surface of the first shallow trench, a first polysilicon gate 103 filled in the first shallow trench formed with the first gate dielectric layer 102, and a first dielectric layer 104 formed on the surface of the first polysilicon gate 103. The first dielectric layer 104 can be an oxide layer formed by thermally oxidizing the surface of the first polysilicon gate 103.
The first channel region of the selection tube is composed of the semiconductor substrate 101 which is located on the side surface and the bottom surface of the first shallow trench and covered by the first polysilicon gate 103, and the first channel region is in an enhancement type channel structure.
A second channel region 105 composed of a first conductive type lightly doped region is formed on the surface of the semiconductor substrate 101 on the first side of the first shallow trench of the first gate structure, and the second channel region 105 is in a depletion channel structure.
A second gate structure of the storage tube is formed on the top of the second channel region 105, the second gate structure includes an ONO layer and a second polysilicon gate 111 sequentially formed on the surface of the second channel region 105, and the ONO layer is a three-layer structure composed of a second oxide layer 108, a third nitride layer 109 and a fourth oxide layer 110 sequentially formed on the surface of the second channel region 105.
A first source-drain injection region 107a with a heavily doped first conductivity type is formed on the surface of the semiconductor substrate 101 on the second side of the first polysilicon gate 103; a second source-drain injection region 107b with a heavily doped first conductivity type is formed on the surface of the semiconductor substrate 101 on the first side of the second polysilicon gate 111; the first source-drain implantation region 107a and the first side of the first polysilicon gate 103 are self-aligned; the second source-drain implantation region 107b is self-aligned to the first side of the second polysilicon gate 111.
The first source-drain injection region 107a and the second source-drain injection region 107b are connected through the first channel region and the second channel region 105, and the memory cell 401 is in a 1.5T-shaped structure.
An isolation structure which is not overlapped in the longitudinal direction and the transverse direction is formed between the first polysilicon gate 103 and the second polysilicon gate 111, so that electric leakage between the first polysilicon gate 103 and the second polysilicon gate 111 is reduced, power consumption of the device is reduced, and reliability of the device is improved.
Each of the memory cells 401 of the storage area of the SONOS device is arranged in an array structure, as shown in fig. 5, 4 memory cells 401 are shown, which are respectively denoted by Cell a, Cell B, Cell C, and Cell D, and the array structure is:
the memory cells 401 adjacent to each other on the same column share the same first source/drain injection region 107a, and the memory cells 401 adjacent to each other on the same column share the same second source/drain injection region 107 b.
The second source drain implant regions 107b of each of the memory cells 401 in the same column are all connected to the same bit line, two bit lines are shown in fig. 5, being BL1 and BL 2.
The first source-drain implant regions 107a of the memory cells 401 in the same row are all connected to the same source line SL.
The first polysilicon gates 103 of each of the memory cells 401 in the same row are all connected to the same select word line, two of which are shown in fig. 5 and denoted as WL1 and WL2, respectively.
The second polysilicon gates 111 of each of the memory cells 401 in the same row are all connected to the same memory word line, two memory word lines WLS are shown in fig. 5, denoted WLS1 and WLS2, respectively.
The SONOS device further comprises a logic area, and a CMOS logic tube is formed in the logic area.
And an active area of the CMOS logic tube is formed in the logic area through shallow trench field oxygen isolation, the shallow trench field oxygen is filled in a second shallow trench, and the second shallow trench in the logic area has the same process structure as a first shallow trench corresponding to the first grid structure of the selection tube in the storage area.
The CMOS logic tube comprises an NMOS tube and a PMOS tube, a third gate structure of the CMOS logic tube comprises a second gate dielectric layer and a third polysilicon gate, and the second polysilicon gate 111 and the third polysilicon gate are formed simultaneously by adopting the same process.
A first conductive lightly doped drain region 106 is further overlapped in the first source drain implantation region 107a, and a first conductive lightly doped drain region 106 is further overlapped in the second source drain implantation region 107 b.
A side wall is formed on the side surface of the second polysilicon gate 111, and in fig. 4, the side wall on the side surface of the second polysilicon gate 111 includes an oxide layer 112a, silicon nitride 112b, and an oxide layer 112 c.
In the embodiment of the invention, the storage tube and the selection tube are both N-type devices, the first conduction type is N-type, and the second conduction type is P-type. In other embodiments can also be: the storage tube and the selection tube are both P-type devices, the first conduction type is P-type, and the second conduction type is N-type.
The bias modes of the programming, erasing and reading operations of the SONOS device according to the embodiment of the present invention can also be set according to table one, and when the memory cell 401 is programmed, a high voltage difference of 11.7V is also generated between the first polysilicon gate 103 and the second polysilicon gate 111. However, since the first polysilicon gate 103 and the second polysilicon gate 111 are not overlapped in the longitudinal direction and the transverse direction, the first polysilicon gate 103 and the second polysilicon gate 111 are well physically isolated, and compared with the back-to-back structure between the polysilicon gates between the selection transistor and the storage transistor in the prior art, the embodiment of the invention can greatly reduce the electric leakage between the first polysilicon gate 103 and the second polysilicon gate 111, thereby reducing the power consumption of the device; in addition, because the first polysilicon gate 103 and the second polysilicon gate 111 are in a non-overlapping physical isolation structure, the degradation of an isolation insulating layer between the first polysilicon gate 103 and the second polysilicon gate 111 caused by high voltage between the first polysilicon gate 103 and the second polysilicon gate 111 can be avoided, so that the reliability of a device can be improved, the quality requirement on the isolation insulating layer between the first polysilicon gate 103 and the second polysilicon gate 111 can be reduced, and the manufacturing process can be simplified; in addition, the first polysilicon gate 103 and the second polysilicon gate 111 are in a non-overlapping physical isolation structure, so that mutual interference between the first polysilicon gate 103 and the second polysilicon gate 111 can be avoided.
As shown in fig. 6A to 6B, which are memory cell structure diagrams in steps of a manufacturing method of a SONOS device according to an embodiment of the present invention, a memory cell 401 of a memory area of the SONOS device in the manufacturing method of the SONOS device according to the embodiment of the present invention includes a memory pipe and a selection pipe, and the manufacturing steps include:
step one, as shown in fig. 6A, a second conductive type semiconductor substrate 101 is provided, and a first shallow trench is formed on the surface of the semiconductor substrate 101.
Step two, as shown in fig. 6A, a first gate dielectric layer 102 is formed on the side surface and the bottom surface of the first shallow trench.
Step three, as shown in fig. 6A, filling polysilicon in the first shallow trench to form a first polysilicon gate 103, and forming a first dielectric layer 104 on the surface of the first polysilicon gate 103; the first shallow trench, the first gate dielectric layer 102 and the first polysilicon gate 103 form a first gate structure of the selection tube; the first channel region of the selection tube is composed of the semiconductor substrate 101 which is located on the side surface and the bottom surface of the first shallow trench and covered by the first polysilicon gate 103, and the first channel region is in an enhancement type channel structure.
Step four, as shown in fig. 6A, a first conductive type lightly doped ion implantation is performed to form a second channel region 105 on the surface of the semiconductor substrate 101 on the first side of the first shallow trench of the first gate structure, where the second channel region 105 is in a depletion type channel structure.
Step five, as shown in fig. 6B, forming an ONO layer formed by overlapping the second oxide layer 108, the third nitride layer 109 and the fourth oxide layer 110 on the surface of the semiconductor substrate 101, and performing photolithography etching on the ONO layer to make the ONO layer only remain in the storage region.
And sixthly, depositing to form a second polycrystalline silicon layer as shown in fig. 6B, wherein the second polycrystalline silicon layer is superposed on the surface of the ONO layer in the logic area.
Seventhly, as shown in fig. 6B, performing photolithography etching on the second polysilicon layer and the ONO layer in the storage region to form a second gate structure of the storage tube; the second gate structure includes an ONO layer and a second polysilicon gate 111 sequentially formed on the surface of the second channel region 105, and the second polysilicon gate 111 is formed by etching the second polysilicon layer.
Eighthly, as shown in fig. 4, performing source-drain implantation of the first conductive type heavily doped to form a first source-drain implantation region 107a and a second source-drain implantation region 107b at the same time, wherein the first source-drain implantation region 107a is formed on the surface of the semiconductor substrate 101 on the second side of the first polysilicon gate 103; the second source-drain injection region 107b is formed on the surface of the semiconductor substrate 101 on the first side of the second polysilicon gate 111; the first source-drain implantation region 107a and the first side of the first polysilicon gate 103 are self-aligned; the second source-drain implantation region 107b is self-aligned to the first side of the second polysilicon gate 111.
The first source-drain injection region 107a and the second source-drain injection region 107b are connected through the first channel region and the second channel region 105, and the memory cell 401 is in a 1.5T-shaped structure.
An isolation structure which is not overlapped in the longitudinal direction and the transverse direction is formed between the first polysilicon gate 103 and the second polysilicon gate 111, so that electric leakage between the first polysilicon gate 103 and the second polysilicon gate 111 is reduced, power consumption of the device is reduced, and reliability of the device is improved.
In the method according to the embodiment of the present invention, the SONOS device further includes a logic area, and a CMOS logic transistor is formed in the logic area.
Forming a second shallow trench in the logic area while forming the first shallow trench in the first step; and filling an oxidation layer in the second shallow trench to form shallow trench field oxygen, and isolating the active region in the logic region by the shallow trench field oxygen.
The CMOS logic tube comprises an NMOS tube and a PMOS tube;
in the fifth step, after the ONO layer outside the storage region is removed, a step of performing threshold voltage adjustment injection corresponding to the CMOS logic transistor in the logic region and a step of forming a second gate dielectric layer on the surface of the semiconductor substrate 101 formed in the logic region are further included.
And sixthly, simultaneously forming the second polycrystalline silicon layer on the surface of the second gate dielectric layer in the logic area.
Then, in the seventh step, the second polysilicon layer and the second dielectric layer in the logic area are simultaneously etched by lithography to form a third gate structure of the CMOS logic tube; the third gate structure of the CMOS logic tube comprises a structure formed by overlapping the second gate dielectric layer and the third polysilicon gate.
And a step of forming a first conductive type lightly doped drain region 106 by performing a first conductive type lightly doped drain implantation before the source drain implantation in the step eight.
Then, forming a side wall on the side surface of the second polysilicon gate 111; in fig. 4, the sidewall of the side surface of the second polysilicon gate 111 includes an oxide layer 112a, a silicon nitride layer 112b, and an oxide layer 112 c.
And then performing source-drain implantation in the step eight.
In the embodiment of the invention, the storage tube and the selection tube are both N-type devices, the first conduction type is N-type, and the second conduction type is P-type. In other embodiments can also be: the storage tube and the selection tube are both P-type devices, the first conduction type is P-type, and the second conduction type is N-type.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. The SONOS device is characterized in that a storage unit of a storage area of the SONOS device comprises a storage tube and a selection tube;
the first gate structure of the select transistor includes: the first shallow trench is formed on the surface of the second conductive type semiconductor substrate, the first gate dielectric layers are formed on the side surfaces and the bottom surface of the first shallow trench, the first polysilicon gate in the first shallow trench formed with the first gate dielectric layers is filled, and the first dielectric layer is formed on the surface of the first polysilicon gate;
the first channel region of the selection tube is composed of the semiconductor substrate which is positioned on the side surface and the bottom surface of the first shallow trench and covered by the first polysilicon gate, and the first channel region is in an enhancement type channel structure;
a second channel region composed of a first conductive type lightly doped region is formed on the surface of the semiconductor substrate on the first side of the first shallow trench of the first grid structure, and the second channel region is of a depletion channel structure;
a second gate structure of the storage tube is formed at the top of the second channel region, the second gate structure comprises an ONO layer and a second polysilicon gate which are sequentially formed on the surface of the second channel region, and the ONO layer is a three-layer structure consisting of a second oxide layer, a third nitride layer and a fourth oxide layer which are sequentially formed on the surface of the second channel region;
a first source drain injection region with a first conduction type heavy doping is formed on the surface of the semiconductor substrate on the second side of the first polysilicon gate; a second source-drain injection region with a heavily doped first conductive type is formed on the surface of the semiconductor substrate on the first side of the second polysilicon gate; the first source-drain injection region and the second side of the first polysilicon gate are self-aligned; the second source drain injection region is self-aligned with the first side of the second polysilicon gate;
the first source-drain injection region and the second source-drain injection region are connected through the first channel region and the second channel region, and the memory unit is made to be in a 1.5T-shaped structure;
an isolation structure which is not overlapped longitudinally and transversely is formed between the first polysilicon gate and the second polysilicon gate, so that electric leakage between the first polysilicon gate and the second polysilicon gate is reduced, power consumption of a device is reduced, and reliability of the device is improved.
2. The SONOS device of claim 1, wherein: each memory cell of the storage area of the SONOS device is arranged into an array structure, and the array structure is as follows:
the adjacent memory cells on the same column share the same first source-drain injection region, and the adjacent memory cells on the same column share the same second source-drain injection region;
the second source-drain injection regions of the memory cells on the same column are connected to the same bit line;
the first source-drain injection regions of the memory cells on the same row are connected to the same source line;
the first polysilicon gates of all the memory cells on the same row are connected to the same selection word line;
the second polysilicon gates of each of the memory cells on the same row are connected to the same memory word line.
3. The SONOS device of claim 1, wherein: the SONOS device further comprises a logic area, and a CMOS logic tube is formed in the logic area.
4. The SONOS device of claim 3, wherein: and an active area of the CMOS logic tube is formed in the logic area through shallow trench field oxygen isolation, the shallow trench field oxygen is filled in a second shallow trench, and the second shallow trench in the logic area has the same process structure as a first shallow trench corresponding to the first grid structure of the selection tube in the storage area.
5. The SONOS device of claim 3, wherein: the CMOS logic tube comprises an NMOS tube and a PMOS tube, a third grid structure of the CMOS logic tube comprises a second grid dielectric layer and a third polysilicon grid, and the second polysilicon grid and the third polysilicon grid are formed simultaneously by adopting the same process.
6. The SONOS device of claim 1, wherein: and a first conductive type lightly doped drain region is also superposed in the first source drain injection region, and a first conductive type lightly doped drain region is also superposed in the second source drain injection region.
7. The SONOS device of claim 1, wherein: and forming a side wall on the side surface of the second polysilicon gate.
8. The SONOS device of any one of claims 1 to 7, wherein: the storage tube and the selection tube are both N-type devices, the first conduction type is N-type, and the second conduction type is P-type; or, the storage tube and the selection tube are both P-type devices, the first conduction type is P-type, and the second conduction type is N-type.
9. A manufacturing method of a SONOS device is characterized in that a storage unit of a storage area of the SONOS device comprises a storage tube and a selection tube, and the manufacturing steps comprise:
providing a second conductive type semiconductor substrate, and forming a first shallow trench on the surface of the semiconductor substrate;
forming a first gate dielectric layer on the side surface and the bottom surface of the first shallow trench;
filling polycrystalline silicon in the first shallow trench to form a first polycrystalline silicon gate, and forming a first dielectric layer on the surface of the first polycrystalline silicon gate; the first shallow trench, the first gate dielectric layer and the first polysilicon gate form a first gate structure of the selection tube; the first channel region of the selection tube is composed of the semiconductor substrate which is positioned on the side surface and the bottom surface of the first shallow trench and covered by the first polysilicon gate, and the first channel region is in an enhancement type channel structure;
implanting first conductive type lightly doped ions into the surface of the semiconductor substrate on the first side of the first shallow trench of the first grid structure to form a second channel region, wherein the second channel region is of a depletion channel structure;
fifthly, forming an ONO layer formed by overlapping a second oxide layer, a third nitride layer and a fourth oxide layer on the surface of the semiconductor substrate, and carrying out photoetching on the ONO layer to ensure that the ONO layer is only reserved in the storage area;
depositing to form a second polycrystalline silicon layer, wherein the second polycrystalline silicon layer is superposed on the surface of the ONO layer in the storage area;
step seven, photoetching and etching the second polysilicon layer and the ONO layer in the storage area to form a second grid structure of the storage tube; the second grid structure comprises an ONO layer and a second polysilicon gate which are sequentially formed on the surface of the second channel region, and the second polysilicon gate consists of the etched second polysilicon layer;
eighthly, performing source-drain injection of first conductive type heavy doping and simultaneously forming a first source-drain injection region and a second source-drain injection region, wherein the first source-drain injection region is formed on the surface of the semiconductor substrate on the second side of the first polysilicon gate; the second source-drain injection region is formed on the surface of the semiconductor substrate on the first side of the second polysilicon gate; the first source-drain injection region and the second side of the first polysilicon gate are self-aligned; the second source drain injection region is self-aligned with the first side of the second polysilicon gate;
the first source-drain injection region and the second source-drain injection region are connected through the first channel region and the second channel region, and the memory unit is made to be in a 1.5T-shaped structure;
an isolation structure which is not overlapped longitudinally and transversely is formed between the first polysilicon gate and the second polysilicon gate, so that electric leakage between the first polysilicon gate and the second polysilicon gate is reduced, power consumption of a device is reduced, and reliability of the device is improved.
10. The method of fabricating the SONOS device of claim 9, wherein: each memory cell of the storage area of the SONOS device is arranged into an array structure, and the array structure is as follows:
the adjacent memory cells on the same column share the same first source-drain injection region, and the adjacent memory cells on the same column share the same second source-drain injection region;
the second source-drain injection regions of the memory cells on the same column are connected to the same bit line;
the first source-drain injection regions of the memory cells on the same row are connected to the same source line;
the first polysilicon gates of all the memory cells on the same row are connected to the same selection word line;
the second polysilicon gates of each of the memory cells on the same row are connected to the same memory word line.
11. The method of fabricating the SONOS device of claim 9, wherein: the SONOS device further comprises a logic area, and a CMOS logic tube is formed in the logic area.
12. The method of fabricating the SONOS device of claim 11, wherein: forming a second shallow trench in the logic area while forming the first shallow trench in the first step; and filling an oxidation layer in the second shallow trench to form shallow trench field oxygen, and isolating the active region in the logic region by the shallow trench field oxygen.
13. The method of fabricating the SONOS device of claim 12, wherein: the CMOS logic tube comprises an NMOS tube and a PMOS tube;
after removing the ONO layer outside the storage area, the fifth step further comprises a step of adjusting and injecting the threshold voltage corresponding to the CMOS logic tube in the logic area and a step of forming a second gate dielectric layer on the surface of the semiconductor substrate formed in the logic area;
then, in the sixth step, the second polysilicon layer is simultaneously formed on the surface of the second gate dielectric layer in the logic area;
then, in the seventh step, the second polysilicon layer and the second gate dielectric layer in the logic area are simultaneously etched by lithography to form a third gate structure of the CMOS logic tube; the third gate structure of the CMOS logic tube comprises a structure formed by overlapping the second gate dielectric layer and a third polysilicon gate, and the second polysilicon gate and the third polysilicon gate are formed simultaneously by adopting the same process.
14. The method of fabricating the SONOS device of claim 9, wherein:
step eight, before the source-drain injection, the step of carrying out first conductive type light doping drain injection to form a first conductive type light doping drain area is also included;
then forming a side wall on the side surface of the second polysilicon gate;
and then performing source-drain implantation in the step eight.
15. The method of fabricating the SONOS device of any one of claims 9 to 14, wherein: the storage tube and the selection tube are both N-type devices, the first conduction type is N-type, and the second conduction type is P-type; or, the storage tube and the selection tube are both P-type devices, the first conduction type is P-type, and the second conduction type is N-type.
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