US10817637B2 - System and method of designing integrated circuit by considering local layout effect - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 230000000694 effects Effects 0.000 title claims abstract description 13
- 230000002093 peripheral effect Effects 0.000 claims abstract description 23
- 230000006870 function Effects 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000001419 dependent effect Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 235000001892 vitamin D2 Nutrition 0.000 claims description 2
- 238000012986 modification Methods 0.000 claims 2
- 230000004048 modification Effects 0.000 claims 2
- 238000004458 analytical method Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 16
- 238000000622 liquid--liquid extraction Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 9
- 230000008859 change Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000003247 decreasing effect Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/10—Noise analysis or noise optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Definitions
- the exemplary embodiments of the herein described subject matter relate to an integrated circuit (IC), and more particularly, to a system and method of designing an IC by considering a local layout effect.
- IC integrated circuit
- ICs for processing digital signals may be designed based on standard cells.
- ICs may each include instances of the standard cells, and instances corresponding to one standard cell may have the same structure, namely, the same layout. Instances may be placed in order for an IC to realize a desired function, and interconnections that electrically connect the instances may be generated, thereby generating a layout of the IC.
- a standard cell including patterns provided in a plurality of arrays may include patterns having a reduced size, and moreover, a size of the standard cell may decrease. Therefore, an influence of a peripheral structure (i.e., layout) may increase on an instance of a standard cell included in an IC, and the influence of the peripheral layout may be referred to as a local layout effect (LLE) or a layout dependent effect (LDE).
- LLE local layout effect
- LDE layout dependent effect
- the herein described exemplary embodiments describe a method of designing an IC by considering an LLE, and moreover, provides a system and a method to manufacture an IC having a layout with decreased LLE.
- Methods may comprise generating a layout of an IC so as to decrease LLEs, and/or reflect the LLEs in the IC to analyze a performance of the IC.
- an integrated circuit is designed using a standard cell library, including instances of standard cells, a pre-placer configured to place first instances of pre-placement cells to decrease occurrence of a local layout effect (LLE) causing structure caused by placement of second instances of logic cells, an instance placer configured to place the second instances in an area where the first instances are not placed, and a router configured to generate layout data of the IC by routing connections of the placed first and second instances.
- LLE local layout effect
- an integrated circuit is manufactured including instances of standard cells, including placing first instances of pre-placement cells to decrease occurrence of a local layout effect (LLE) causing structures caused by placement of second instances of logic cells, placing the second instances in an area where the first instances are not placed, and generating layout data of the IC by routing connections of the first and second instances.
- LLE local layout effect
- an instance characterizer is configured to refer to local layout effect (LLE) data including information about a physical characteristic of a standard cell dependent on a peripheral layout and calculate a physical characteristic of an instance placed in the IC based on context data including a context of the placed instance, based on context data, including a context of the placed instance, of a peripheral layout of the placed instance and a performance analyzer configured to generate result data including performance information about the IC, based on the calculated physical characteristic of the placed instance.
- LLE local layout effect
- methods of manufacturing an IC may include use of LLE data and context data.
- the local layout effect (LLE) data may include information about a physical characteristic of a standard cell that is dependent on a peripheral layout
- the context data may include a context of the placed instance with respect to a peripheral layout of an instance placed in the IC.
- a physical characteristic of the placed instance may be estimated based on the LLE data and the context data to generate performance result information about the IC.
- FIG. 1 illustrates a block diagram of a computing system including a memory storing a program, according to an exemplary embodiment
- FIG. 2 illustrates a schematic plan view of an IC according to an exemplary embodiment
- FIG. 3 illustrates a block diagram of a program of FIG. 1 according to an exemplary embodiment
- FIG. 4 illustrates a block diagram of a placer of FIG. 3 according to an exemplary embodiment
- FIGS. 5 to 8 are diagrams illustrating exemplary operations of a pre-placer of FIG. 4 according to exemplary embodiments
- FIGS. 9A and 9B illustrate examples of an implementation group of FIG. 3 ;
- FIGS. 10A and 10B are diagrams illustrating exemplary operations of an instance shifter of FIG. 9A or 9B according to exemplary embodiments;
- FIG. 11 illustrates a block diagram of an analysis group of FIG. 3 according to an exemplary embodiment
- FIG. 12 illustrates a block diagram of an LLE data generator according to an exemplary embodiment
- FIGS. 13A and 13B illustrate exemplary operations of generating, by a cell context generator of FIG. 12 , a context of a standard cell according to exemplary embodiments;
- FIG. 14 illustrates an example of LLE data according to an exemplary embodiment
- FIG. 15 is a block diagram of a context data generator according to an exemplary embodiment
- FIG. 16 illustrates an exemplary operation of an instance context extractor of FIG. 15 ;
- FIG. 17 is a flowchart illustrating an IC designing method according to an exemplary embodiment
- FIG. 18 is a flowchart illustrating an example of operation S 120 of FIG. 17 ;
- FIG. 19 is a flowchart illustrating a method of shifting an instance for removing an LLE causing structure, according to an exemplary embodiment
- FIG. 20 is a flowchart illustrating an IC designing method according to an exemplary embodiment.
- FIG. 21 is a flow chart illustrating the manufacturing process of an integrated circuit, including methods of designing according to FIGS. 17-20 .
- Each block, unit and/or module may correspond to a separate segment or segments of software (e.g., a subroutine) which configure the computer, or may correspond to segment(s) of software that are shared with one or more other blocks, units and/or modules.
- each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions.
- each block, unit and/or module of the embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the scope of the inventive concepts. Further, the blocks, units and/or modules of the embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concepts.
- FIG. 1 illustrates a block diagram of a computing system 10 including a memory storing a program, according to an exemplary embodiment. An operation of designing an IC according to an exemplary embodiment may be performed by the computing system 10 .
- the computing system 10 may be a fixed computing system such as a desktop computer, a workstation, or a server, or may be a portable computing system such as a laptop computer. As illustrated in FIG. 1 , the computing system 10 may include a central processing unit (CPU) 11 , input/output (I/O) devices 12 , a network interface 13 , random access memory (RAM) 14 , read-only memory (ROM) 15 , and a storage device 16 .
- the CPU 11 , the I/O devices 12 , the network interface 13 , the RAM 14 , the ROM 15 , and the storage device 16 may be connected to a bus 17 and may communicate with each other through the bus 17 .
- the CPU 11 may be referred to as a processing unit and may include a core for executing an arbitrary instruction set (for example, intel architecture-32 (IA-32), 64 bit extension IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.) like a micro-processor, an application processor (AP), a digital signal processor (DSP), a graphics processing unit (GPU), etc.
- the CPU 11 may access a memory (i.e., the RAM 14 or the ROM 15 ) through the bus 17 and may execute instructions stored in the RAM 14 or the ROM 15 . As illustrated in FIG.
- the RAM 14 may store a program 20 according to an exemplary embodiment or at least some elements of the program 20 , and the program 20 may allow the CPU 11 to perform an operation of designing an IC. That is, the program 20 may include a plurality of instructions executable by the CPU 11 , and the plurality of instructions included in the program 20 may allow the CPU 11 to perform operations of designing the IC according to an exemplary embodiment.
- the storage device 16 may include a non-volatile memory, such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), or the like, and may include a storage medium such as an optical disk, a magnetic disk, or the like. Also, the storage device 16 may be detachably attached to the computing system 10 . The storage device 16 may store the program 20 according to an exemplary embodiment.
- EEPROM electrically erasable programmable read-only memory
- flash memory phase change random access memory
- RRAM resistance random access memory
- NFGM nano floating gate memory
- PoRAM polymer random access memory
- MRAM magnetic random access memory
- FRAM ferroelectric random access memory
- the storage device 16 may store the program 20 according to an exemplary embodiment.
- the program 20 or at least some elements of the program 20 may be loaded from the storage device 16 to the RAM 14 before being executed by the CPU 11 .
- the storage device 16 may store a file written in a program language, and the program 20 generated by a compiler or the like or at least some elements of the program 20 may be loaded to the RAM 14 .
- the storage device 16 may store data, which is to be processed by the CPU 11 , or data obtained through processing by the CPU 11 .
- the CPU 11 may process the data stored in the storage device 16 to generate new data, based on the program 20 and may store the generated data in the storage device 16 .
- the storage device 16 may store input data D 010 of FIG. 3 obtained through processing by the program 20 and may store layout data D 100 and/or result data D 200 of FIG. 3 generated by the program 20 .
- the I/O devices 12 may include an input device, such as a keyboard, a pointing device, or the like, and may include an output device such as a display device, a printer, or the like.
- a user may trigger, through the I/O devices 12 , execution of the program 20 by the CPU 11 or may input the input data D 010 of FIG. 3 , and may check the layout data D 100 of FIG. 3 , the result data D 200 of FIG. 3 , an error message, and/or the like.
- the network interface 13 may provide access to a network outside the computing system 10 .
- the network may include a plurality of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or arbitrary other type links.
- the input data D 010 of FIG. 3 may be provided to the computing system 10 through the network interface 13
- the layout data D 100 and/or the result data D 200 may be provided to another computing system through the network interface 13 .
- FIG. 2 illustrates a schematic plan view of an IC 5 according to an exemplary embodiment.
- each of the elements included in the IC 5 may not match a scale and may be exaggerated or reduced.
- the IC 5 may include instances C 01 to C 07 of standard cells.
- instances for example, C 02 to C 05
- instances corresponding to different standard cells e.g., C 01 , C 06 and C 07
- the instances C 01 to C 07 may be aligned and placed in a plurality of rows R 01 to R 04 .
- the instances C 01 to C 07 may have a length H (i.e., a height) which is prescribed in a direction (i.e., a Y direction) vertical to the plurality of rows R 01 to R 04 extending in an X direction, and may have the same or different lengths (i.e., widths) in a direction (i.e., the X direction) parallel to the plurality of rows R 01 to R 04 .
- Each of the plurality of rows R 01 to R 04 where the instances C 01 to C 06 are aligned may be set to have a height matching a minimum height of a standard cell.
- a standard cell corresponding to instances having a height matching a height H of a row like instances C 01 to C 05 and C 07 of FIG. 2 may be referred to as a single height cell, and a standard cell corresponding to instances having a height matching a multiple of the height H of the row, like the instance C 06 of FIG. 2 , may be referred to as a multi-height cell.
- a standard cell which is added to an IC design may be selected from a cell library (for example, D 310 of FIG. 3 ) that includes information about a plurality of standard cells, and a layout of the IC 5 may be generated by arranging an instance of the selected standard cell.
- the instance as placed in the IC 5 may have a physical characteristic that is different from an intrinsic physical characteristic of the standard cell, based on layouts of instances adjacent to the instance.
- a threshold voltage Vth and a saturation current Idsat of a transistor included in the instance may vary according to the adjacent layouts to the instance, and thus, the physical characteristics of the instance included in the IC 5 may differ from intrinsic physical characteristics of a standard cell as defined in the cell library.
- the influence of a layouts peripheral to an instance may be referred to as a local layout effect (LLE). Accurately checking an LLE of an instance is difficult until the arrangement of the instance and layouts peripheral to the instance are determined.
- a physical characteristic (for example, a threshold voltage Vth, a saturation current Idsat, etc.) of a transistor may be changed by a pattern of a front-end-layer (or a front-end-of-layer) formed near the transistor.
- the physical characteristic of the transistor may be changed by a length of a pattern of a front-end-layer aligned in the Y direction and a distance between patterns of the front-end-layer which are spaced apart from each other in the Y direction.
- the front-end-layer may be a layer of material in the manufactured IC forming and/or associated with forming of the transistor and may denote a layer formed by a front-end-of-line where elements such as a transistor, a capacitor, and a resistor are manufactured in a semiconductor manufacturing process.
- the standard cells corresponding to instances C 01 to C 07 may include insulative and/or conductive patterns of a front-end-layer provided in an edge or an internal portion.
- an IC designing method capable of being performed by the computing system 10 of FIG. 1 may consider an LLE, based on a front-end-layer.
- instances may be arranged so as to decrease occurrence of an LLE by the front-end-layer, and thus, the LLE and a performance change of an IC caused by the LLE may be removed or reduced.
- an actual physical characteristic of an instance may be calculated based on a front-end-layer near the instance, and thus, an actual performance of an IC may be analyzed by reflecting an LLE, and the IC may be optimally designed to remove or reduce an undesired performance margin.
- FIG. 3 illustrates a block diagram of the program 20 of FIG. 1 according to an exemplary embodiment.
- the program 20 may include a plurality of instructions that may allow the CPU 11 to perform an operation of designing an IC according to an exemplary embodiment. All of elements of the program 20 illustrated in FIG. 3 may be stored in the RAM 14 of FIG. 1 , or at least some of the elements may be stored in the RAM 14 of FIG. 1 and the other some elements may be stored in the ROM 15 or the storage device 16 of FIG. 1 .
- the program 20 may include an implementation group 100 and an analysis group 200
- the implementation group 100 may include a plurality of procedures 120 and 140
- the analysis group 200 may include a plurality of procedures 220 and 240 .
- Each of the procedures may denote a series of instructions for performing a certain task.
- a procedure may be referred to as a function, a routine, a subroutine, or a subprogram.
- Each of the procedures may process data (for example, D 010 ) provided from the outside and/or data (for example, D 100 ) generated by another procedure.
- the CPU 11 of FIG. 1 which performs an operation by executing a procedure (for example, 120 , 140 , 220 , or 240 ) may be expressed as the procedure (for example, 120 , 140 , 220 , or 240 ) in performing the operation.
- a cell library D 310 , a design rule D 320 , and LLE data D 330 may be stored in a storage medium 30 and, for example, the storage medium 30 may be the storage device 16 of FIG. 1 .
- the cell library D 310 may include at least one of piece of information (for example, function information, timing information, layout information, and power information) about physical characteristics of a plurality of standard cells.
- the design rule D 320 may include rules which a layout of an IC observes, in order for the IC to be manufactured by a semiconductor process and/or in order to prevent performance of the IC from being reduced. Also, described below, the design rule D 320 may further include information for detecting a structure causing an LLE.
- the LLE data D 330 may include information about a physical characteristic change of a standard cell caused by the LLE. As described below with reference to FIGS. 12 to 14 , the LLE data D 330 may be generated by an LLE data generator 300 and may be prepared before the implementation group 100 and the analysis group 200 of FIG. 3 are executed.
- the implementation group 100 may refer to pieces of data D 310 , D 320 , and D 330 stored in the storage medium 30 and may generate layout data D 100 from input data D 010 .
- the input data D 010 may be data that defines an IC, and for example, may include a netlist which includes instances of standard cells and information about electrical connection relationships between the instances. Also, the input data D 010 may further include information (for example, a timing condition, a power condition, an area condition, etc.) about a requirement of the IC.
- the implementation group 100 may generate the layout data D 100 , including physical information about a layout of the IC, from the input data D 010 defining the IC, based on the pieces of data D 310 , D 320 , and D 330 stored in the storage medium 30 .
- the implementation group 100 may access the result data D 200 which includes information about performance of the IC and is generated based on the layout data D 100 by the analysis group 200 .
- the implementation group 100 may change the layout of the IC according to whether a performance of the IC based on the layout data D 100 satisfies the requirement of the IC included in the input data D 010 , based on the result data D 200 and may generate new layout data D 100 representing the changed layout.
- the result data D 200 may include a performance reduction or a performance margin of the IC based on an LLE, and the implementation group 100 may generate the new layout data D 100 representing a layout of an optimally designed IC, based on the result data D 200 .
- a placer 120 of the implementation group 100 may place instances defined in the input data D 010 with reference to the cell library D 310 .
- the placer 120 may obtain layouts of the instances defined in the input data D 010 with reference to the cell library D 310 and may place instances (i.e., layouts of the instances), based on information about the requirement of the IC included in the input data D 010 and the design rule D 320 .
- the placer 120 may place instances so as to decrease occurrence of a structure causing an LLE. Details of the placer 120 will be described below with reference to FIGS. 4 to 8 .
- a router 140 may generate interconnections that electrically connect the instances placed by the placer 120 .
- the router 140 may generate an interconnection which includes a pattern and/or a via formed in a wiring layer, based on a routing source, namely, a plurality of wiring layers and vias.
- the router 140 may generate the interconnections, based on information about a connection relationship of the instances defined in the input data D 010 and the design rule D 320 .
- the router 140 may generate the interconnections, based on the information about the requirement of the IC included in the input data D 010 .
- the analysis group 200 may refer to the pieces of data D 310 , D 320 , and D 330 stored in the storage medium 30 and may generate the result data D 200 from the layout data D 100 .
- the layout data D 100 may include physical information about the layout of the IC, and for example, may include data having a GDSII format. Although it is illustrated in FIG. 3 that the analysis group 200 accesses the layout data D 100 generated by the implementation group 100 , the layout data D 100 may be generated by a computing system different from a computing system where the analysis groups is performed, and may be provided to the analysis group 200 .
- the analysis group 200 may analyze the performance of the IC, based on the layout data D 100 and may generate the result data D 200 including information about the performance of the IC. As described below, the analysis group 200 may estimate an LLE which occurs in the layout of the IC, and thus, the actual performance of the IC may be reflected in the result data D 200 .
- An instance characterizer 220 of the analysis group 200 may calculate a physical characteristic of an instance included in the layout data D 100 with reference to the LLE data D 330 . That is, the instance characterizer 220 may estimate a peripheral layout of the instance, namely, an LLE affecting the instance in context, thereby calculating the physical characteristic of the instance. For example, even in instances of the same standard cells, physical characteristics of the instances estimated by the instance characterizer 220 may differ. As described below with reference to FIGS. 15 and 16 , the instance characterizer 220 may calculate the physical characteristic of the instance, based on a pattern of a front-end-layer included in the instance and a pattern of a front-end-layer formed in a peripheral layout.
- a performance analyzer 240 may analyze the performance of the IC, based on the physical characteristic of the instance extracted by the instance characterizer 220 . For example, the performance analyzer 240 may analyze a timing characteristic, a power characteristic, a noise characteristic, etc. of the IC. Also, the performance analyzer 240 may generate the result data D 200 including a result obtained by determining whether the performance of the IC satisfies the requirement, based on the information about the requirement of the IC included in the input data D 010 .
- FIG. 4 illustrates a block diagram of the placer 120 of FIG. 3 according to an exemplary embodiment.
- the placer 120 may place the instances defined in the input data D 010 .
- the placer 120 may include a pre-placer 122 and an instance placer 124 and may access the input data D 010 , the cell library D 310 , and the design rule D 320 .
- the pre-placer 122 may place instances of pre-placement cells.
- Each of the pre-placement cells may correspond to instances (referred to as first instances) which are placed before instances (referred to as second instances) of logic cells included in an IC are placed, and as a non-limiting example, may be a well-edge cell, a well-bias cell, a decap cell, or the like.
- the cell library D 310 may include information about each of the pre-placement cells.
- the input data D 010 may define some of instances of each of the pre-placement cells, and the pre-placer 122 may generate and place the instances of each of the pre-placement cells with reference to the cell library D 310 , based on the design rule D 320 .
- the pre-placer 122 may place the first instances (i.e., instances of the pre-placement cells) so as to decrease occurrence of an LLE causing structure caused by placement of the second instances (i.e., instances of the logic cells).
- the design rule D 320 may include an LLE rule D 322
- the LLE rule D 322 may include information about the LLE causing structure.
- the LLE rule D 322 may include information defining a structure where patterns formed in a front-end-layer are aligned, and as described below with reference to FIGS.
- the pre-placer 122 may place the first instances so as to decrease patterns of a front-end-layer included in the second instances being aligned, based on the LLE rule D 322 .
- the LLE rule D 322 may include information about an opposite length and/or an interval between adjacent patterns formed in the front-end-layer.
- the instance placer 124 may place the second instances in an area where the first instances are not placed.
- the area where the second instances are placed may be limited by the first instances placed by the pre-placer 122 , and thus, an LLE causing structure provided by the second instances may be reduced or removed. Therefore, the second instances may have physical characteristics close to an intrinsic physical characteristic of a standard cell defined in the cell library D 310 , and a difference between the physical characteristics of the second instances which have been placed and the physical characteristics of the second instances which are predicted in generating (for example, logical combining) the input data D 010 may be reduced.
- the cell library D 310 may include information defining a physical characteristic of the standard cell, and the input data D 010 may be generated based on the cell library D 310 .
- a difference between a performance of an IC based on the layout data D 100 and a performance of the IC which is predicted in generating the input data D 010 may be reduced, and thus, the IC may be optimally designed in generating the input data D 010 .
- FIGS. 5 to 8 are diagrams illustrating exemplary operations of the pre-placer 122 of FIG. 4 according to exemplary embodiments.
- the pre-placer 122 may place first instances of a pre-placement cell so as to decrease an LLE causing structure based on placement of second instances.
- FIGS. 5 to 8 illustrate examples of instances placed by the pre-placer 122 , and it may be understood that an operation of the pre-placer 122 is not limited to the examples illustrated in FIGS. 5 to 8 .
- FIGS. 5 to 8 as will be described with reference to FIG. 4 .
- an LLE rule 322 of FIG. 4 is assumed as including information defining a structure, where patterns of a front-end-layer are aligned, as an LLE causing structure, and at least some of the second instances are assumed as including patterns of front-end-layers formed in opposite edges. Therefore, the pre-placer 122 may place the first instances so that edges of an area where the second instances are placed are not aligned in a series of rows. Thus, the pre-placer 122 may appropriately place the first instances to allow the edges of the area, where the second instances are placed, not to be aligned in the plurality of rows, thereby decreasing edges of the second instances being aligned. As a result, patterns of front-end-layers formed in the edges of the second instances being aligned are reduced.
- the pre-placer 122 may place the first instances so that edges of first instances closest to each other are not aligned in a direction vertical to a plurality of rows (for example, R 11 to R 19 of FIG. 5 ).
- the pre-placer 122 may place the first instances so that edges of first instances placed in rows adjacent to each other are not aligned.
- the pre-placer 122 may place the first instances so that edges of first instances placed in odd rows (or even rows unlike the illustration of FIG. 6 ) are not aligned (due to the design rule of FIG. 4 ).
- the pre-placer 122 may place first instances C 11 a to C 19 a so that left edges and right edges of the first instances C 11 a , C 13 a , C 15 a , C 17 a , and C 19 a placed in odd rows R 11 , R 13 , R 15 , R 17 , and R 19 are respectively aligned in Y 10 and Y 12 , and left edges and right edges of the first instances C 12 a , C 14 a , C 16 a , and C 18 a placed in even rows R 12 , R 14 , R 16 , and R 18 are respectively aligned in Y 11 and Y 13 .
- FIG. 1 shows that left edges and right edges of the first instances C 11 a , C 13 a , C 15 a , C 17 a , and C 19 a placed in odd rows R 11 , R 13 , R 15 , R 17 , and R 19 are respectively aligned in Y 10 and Y 12
- the pre-placer 122 may place the first instances C 11 b to C 19 b so that left edges of first instances (for example, C 11 b to C 13 b ) sequentially placed in a series of rows (for example, R 11 to R 13 ) are respectively aligned in Y 14 , Y 15 , and Y 16 , and right edges are respectively aligned in Y 17 , Y 18 , and Y 19 .
- the pre-placer 122 may place first instances C 21 a to C 25 a so that left edges of the first instances (for example, C 21 a and C 22 a ) sequentially placed in odd rows (for example, R 21 and R 23 ) are respectively aligned in Y 20 and Y 21 , and right edges are respectively aligned in Y 22 and Y 23 .
- first instances C 21 a to C 25 a so that left edges of the first instances (for example, C 21 a and C 22 a ) sequentially placed in odd rows (for example, R 21 and R 23 ) are respectively aligned in Y 20 and Y 21 , and right edges are respectively aligned in Y 22 and Y 23 .
- the pre-placer 122 may place first instances C 21 b to C 25 b so that left edges of the first instances C 21 b to C 25 b sequentially placed in odd rows R 21 , R 23 , R 25 , R 27 , and R 29 are respectively aligned in Y 24 , Y 25 , Y 26 , Y 25 , and Y 24 , and right edges are respectively aligned in Y 27 , Y 28 , Y 29 , Y 28 , and Y 27 .
- the pre-placer 122 may place instances of dummy cells to be adjacent to first instances, in order to decrease occurrence of an LLE causing structure based on placement of second instances.
- Each of the dummy cells may be a cell irrelevant to a function of an IC and may include a pre-placement cell or a filler cell.
- the cell library D 310 of FIG. 4 may include information about a dummy cell, and the pre-placer 122 may place the instances of the dummy cells with reference to the cell library D 310 .
- the pre-placer 122 may place instances of different dummy cells (for example, dummy cells having different widths) to be adjacent to an edge of at least one first instance having an edge vertical to a series of rows.
- a pre-placement cell may be a multi-height cell (i.e., a 4x multi-height cell) corresponding to a height of four rows, and the pre-placer 122 may alternately place two or more dummy cells having different widths to be adjacent to an edge of an instance of the pre-placement cell.
- a first instance C 31 a of the pre-placement cell which is the 4x multi-height cell may be placed by the pre-placer 122 , and the pre-placer 122 may alternately place instances D 31 a to D 34 a and D 36 a to D 39 a of different dummy cells to be adjacent to an edge of the first instance D 31 a in a series of rows R 32 to R 35 where the first instance C 31 a is placed.
- the instances D 31 a and D 33 a of a dummy cell having a left edge aligned in Y 30 may be respectively placed in even rows R 32 and R 34
- the instances D 32 a and D 34 a of a dummy cell having a left edge aligned in Y 31 may be respectively placed in odd rows R 33 and R 35
- the instances D 36 a and D 38 a of a dummy cell having a right edge aligned in Y 32 may be respectively placed in odd rows R 35 and R 33
- the instances D 37 a and D 39 a of a dummy cell having a right edge aligned in Y 33 may be respectively placed in even rows R 34 and R 32
- instances D 30 a and D 35 a of a dummy cell may be respectively placed in rows R 31 and R 36 adjacent to a series of rows R 32 to R 35 where the first instance C 31 a is placed.
- instances D 31 b to D 34 b and D 36 b to D 39 b of different dummy cells may be alternately placed adjacent to an edge of a first instance C 31 b in a series of rows R 32 to R 35 where the first instance C 31 b is placed.
- an instance D 32 b of a dummy cell having a left edge aligned in Y 34 may be placed in a row R 33
- instances D 31 b and D 34 b of a dummy cell having a left edge aligned in Y 35 may be respectively placed in rows R 32 and R 35
- an instance D 33 b of a dummy cell having a left edge aligned in Y 36 may be placed in a row R 34 .
- an instance D 38 b of a dummy cell having a right edge aligned in Y 37 may be placed in the row R 33
- instances D 36 b and D 39 b of a dummy cell having a right edge aligned in Y 38 may be respectively placed in the rows R 35 and R 32
- an instance D 37 b of a dummy cell having a right edge aligned in Y 39 may be placed in the row R 34
- instances D 30 b and D 35 b of a dummy cell may be respectively placed in the rows R 31 and R 36 adjacent to the series of rows R 32 to R 35 where the first instance C 31 b is placed.
- a plurality of first instances C 41 a to C 49 a of a pre-placement cell may be aligned and placed in a series of rows R 41 to R 49 by the pre-placer 122 , based on the design rule D 320 of FIG. 4 for example.
- the pre-placer 122 may alternately place instances D 41 a to D 49 a and D 41 a ′ to D 49 a ′ of different dummy cells to be adjacent to edges of the first instances C 41 a to C 49 a aligned in the series of rows R 41 to R 49 .
- instances D 42 a , D 44 a , D 46 a , and D 48 a of a dummy cell having a left edge aligned in Y 40 may be placed in even rows R 42 , R 44 , R 46 , and R 48 , and instances D 41 a , D 43 a , D 45 a , D 47 a , and D 49 a of a dummy cell having a left edge aligned in Y 41 may be respectively placed in odd rows R 41 , R 43 , R 45 , R 47 , and R 49 .
- instances D 41 a ′ to D 49 a ′ of a dummy cell having a right edge aligned in Y 42 or Y 43 may be alternately placed adjacent to right edges of the first instances C 41 a to C 49 a.
- the pre-placer 122 may alternately place instances D 41 b to D 49 b and D 41 b ′ to D 49 b ′ of different dummy cells to be adjacent to edges of first instances C 41 b to C 49 b aligned in the series of rows R 41 to R 49 .
- instances D 43 b , D 46 b , and D 49 b of a dummy cell having a left edge aligned in Y 44 may be respectively placed in rows R 43 , R 46 , and R 49
- instances D 42 b , D 45 b , and D 48 b of a dummy cell having a left edge aligned in Y 45 may be respectively placed in rows R 42 , R 45 , and R 48
- instances D 41 b , D 44 b , and D 47 b of a dummy cell having a left edge aligned in Y 46 may be respectively placed in rows R 41 , R 44 , and R 47 .
- instances D 41 b ′ to D 49 b ′ of a dummy cell having a right edge aligned in Y 47 , Y 48 , or Y 49 may be alternately placed adjacent to right edges of the first instances C 41 b to C 49 b.
- FIGS. 9A and 9B illustrate examples of the implementation group 100 of FIG. 3 according to an exemplary embodiment.
- an implementation group 100 a or 100 b may include an instance shifter 126 a or 166 b.
- the instance shifter 126 a or 166 a may shift at least one first or second instance associated with an LLE causing structure among first and second instances which are respectively placed by a pre-placer 122 a and an instance placer 124 a or 124 b , thereby removing the LLE causing structure from a layout of an IC or decreasing an LLE based on the LLE causing structure.
- FIG. 9A illustrates an example where the instance shifter 126 a is included in a placer 120 a
- FIG. 9B illustrates an example where the instance shifter 166 b is included in an engineering change order (ECO) 160 b .
- ECO engineering change order
- the placer 120 b of FIG. 9B may include an instance shifter similarly to the arrangement illustrated in FIG. 9A .
- FIGS. 9A and 9B details which are the same as or similar to the details described above with reference to FIG. 4 are omitted.
- the implementation group 100 a may include a placer 120 a and a router 140 a .
- the placer 120 a may include a pre-placer 122 a , an instance placer 124 a , and an instance shifter 126 a .
- the pre-placer 122 a may place instances (first instances) of a pre-placement cell
- the instance placer 124 a may place instances (second instances) of a logic cell in an area where the first instances are not placed.
- the instance shifter 126 a may shift at least one first or second instance associated with an LLE causing structure among first and second instances, based on an LLE rule D 322 included in a design rule D 320 .
- the LLE rule D 322 may include information defining at least one LLE causing structure
- the instance shifter 126 a may detect an LLE causing structure from a layout of an IC including the first and second instances placed by the pre-placer 122 a and the instance placer 124 a , based on the LLE rule D 322 .
- the instance shifter 126 a may shift at least one first or second instance associated with the detected LLE causing structure, thereby removing the LLE causing structure or decreasing an LLE based on the LLE causing structure.
- the router 140 a may generate interconnections which include the first or second instance shifted by the instance shifter 126 a and connect the first and second instances of the IC, thereby generating layout data D 100 .
- the implementation group 100 b may include a placer 120 b , a router 140 b , and an ECO 160 b .
- the ECO 160 b may include an instance shifter 166 b .
- the ECO 160 b may denote a process of replacing a placed instance or adding a new instance depending on the case after instances of a standard cell are placed and interconnections connecting the instances are generated.
- the ECO 160 b may locally perform a routing operation in association with the replaced or added instance. Therefore, processes (for example, logic combination, routing, timing analysis, etc.) of designing an IC are omitted, and moreover, restrictive changes may be reflected in the IC by the ECO 160 b.
- the instance shifter 166 b may be included in the ECO 160 b , and similarly to the instance shifter 126 a of FIG. 9A , the instance shifter 166 b may shift at least one first or second instance associated with the LLE causing structure, based on the LLE rule D 322 included in the design rule D 320 .
- the instance shifter 166 b may generate the layout data D 100 of the IC including the shifted first or second instance.
- FIGS. 10A and 10B are diagrams illustrating exemplary operations of the instance shifter 126 a or 166 b of FIG. 9A or 9B according to exemplary embodiments.
- the instance shifter 126 a or 166 b may detect an LLE causing structure, based on the LLE rule D 322 and may shift at least one first or second instance associated with the detected LLE causing structure, thereby removing the LLE causing structure or decreasing an LLE based on the LLE causing structure.
- FIGS. 10A and 10B illustrate examples where an instance is shifted by the instance shifter 126 a or 166 b , and it may be understood that an operation of the instance shifter 126 a or 166 b is not limited to the examples illustrated in FIGS. 10A and 10B .
- FIGS. 10A and 10B will be described with reference to FIG. 9A .
- the instance shifter 126 a may detect an LLE causing structure.
- the LLE rule D 322 of FIG. 9A may define patterns of a front-end-layer, which are aligned to have a certain length or more according to instances of a standard cell being placed, as an LLE causing structure, and as illustrated in FIG. 10A , section (a), the instance shifter 126 a may detect patterns of a front-end-layer, which are aligned in a series of four rows R 51 to R 54 , as an LLE causing structure LLE 1 . As illustrated in FIG.
- the instance shifter 126 a may shift an instance C 51 in a left direction (i.e., a ⁇ X direction) and may shift an instance C 52 in a right direction (i.e., a +X direction).
- the instance shifter 126 a may shift at least one instance, including a pattern of a front-end-layer contributing to the LLE causing structure LLE 1 , in an up direction (i.e., a +Y direction) or a down direction (i.e., a ⁇ Y direction) as well as the left direction or the right direction, may shift and place the at least one instance to and in an area within or outside a certain distance, and may exchange a position with another instance. Therefore, as illustrated in FIG. 10A , section (b), the LLE causing structure LLE 1 may be removed by instances C 51 ′ and C 52 ′ shifted by the instance shifter 126 a.
- the instance shifter 126 a may shift two or more instances adjacent to each other in the same row.
- section (a) in order to remove an LLE causing structure LLE 2 including patterns of a front-end-layer which are aligned in a series of four rows R 61 to R 64 , the instance shifter 126 a may shift two or more instances C 61 and C 62 , which are adjacent to each other in the row R 61 , in the same direction (i.e., a left direction or a ⁇ X direction).
- the instance shifter 126 a may shift two or more instances C 63 and C 64 , which are adjacent to each other in the row R 63 , in opposite directions. Also, in order to remove the LLE causing structure LLE 2 , the instance shifter 126 a may shift at least one instance, including a pattern of a front-end-layer contributing to the LLE causing structure LLE 2 , in an up direction (i.e., a +Y direction) or a down direction (i.e., a ⁇ Y direction) as well as the left direction or a right direction, may shift and place the at least one instance to and in an area within or outside a certain distance, and may exchange a position with another instance. Therefore, as illustrated in FIG. 10B , section (b), the LLE causing structure LLE 2 may be removed by instances C 61 ′ and C 62 ′ shifted by the instance shifter 126 a.
- FIG. 3 the implementation group 100 of FIG. 3 according to an exemplary embodiment has been described with reference to FIGS. 4 to 10B .
- the analysis group 200 of FIG. 3 will be described with reference to FIGS. 11 to 16 .
- FIG. 11 illustrates a block diagram of the analysis group 200 of FIG. 3 according to an exemplary embodiment.
- the analysis group 200 may include an instance characterizer 220 and a performance analyzer 240 and may generate result data D 200 from layout data D 100 , based on a cell library D 310 and LLE data D 330 .
- the result data D 200 generated by the analysis group 200 may include information about an actual performance of an IC in which an LLE is reflected.
- the instance characterizer 220 may access LLE data D 330 and context data D 150 .
- the LLE data D 330 may include information about a physical characteristic change of a standard cell caused by the LLE
- the context data D 150 may include peripheral layout information about an instance extracted from the layout data D 010 .
- the instance characterizer 220 may calculate physical characteristics based on an LLE of instances included in the IC with reference to the LLE data D 330 and the context data D 150 . Details of the LLE data D 330 will be described below with reference to FIGS. 12 to 14 , and details of the context data D 150 will be described below with reference to FIGS. 15 and 16 .
- the performance analyzer 240 may access the cell library D 310 and the layout data D 010 .
- the performance analyzer 240 may analyze a performance of the IC based on the layout data D 010 , based on information about a physical characteristic of the standard cell included in the cell library D 310 and information about a physical characteristic of an instance provided by the instance characterizer 220 and may generate the result data D 200 including actual performance information about the IC in which an LLE is reflected.
- FIG. 12 illustrates a block diagram of an LLE data generator 300 for generating LLE data D 330 , according to an exemplary embodiment.
- the LLE data generator 300 may include a procedure including a series of instructions, and an operation of the LLE data generator 300 may be performed by a processor (for example, the CPU 11 of FIG. 1 ) that executes the series of instructions.
- the LLE data generator 300 may generate the LLE data D 330 from the cell library D 310 and may include a cell context generator 320 and an LLE estimator 340 .
- the cell context generator 320 may place various layouts near a layout of a standard cell included in the cell library D 310 , thereby generating a plurality of contexts of a first standard cell. For example, as described below with reference to FIG. 13A , the cell context generator 320 may place standard cells, including a pattern of a front-end-layer, near a target standard cell, thereby generating a context of the target standard cell. Also, as described below with reference to FIG. 13B , the cell context generator 320 may place arbitrary patterns, formed in a front-end-layer, near the standard cell, thereby generating a context of the standard cell. Various contexts of the standard cell generated by the cell context generator 320 may be used for the LLE estimator 340 to estimate an LLE corresponding to each of the contexts.
- the LLE estimator 340 may be provided with information about the contexts of the standard cell from the cell context generator 320 , may estimate an LLE occurring in each of the contexts, and may generate the LLE data D 330 including information about a change in a physical characteristic of the standard cell based on the LLE.
- the cell library D 310 may include a characteristic function for calculating a value representing the physical characteristic of the standard cell, and the LLE estimator 340 may determine parameters of the characteristic function, based on the context provided from the cell context generator 320 .
- the LLE estimator 340 may generate the LLE data D 330 which includes the parameter determined by the LLE estimator 340 or a result of the characteristic function based on the determined parameter.
- FIGS. 13A and 13B illustrate exemplary operations of generating, by the cell context generator 320 of FIG. 12 , a context of a standard cell according to exemplary embodiments.
- the cell context generator 320 may place standard cells C 71 to C 74 , included in the cell library D 310 , near a standard cell C 70 of which a context is to be generated, thereby generating various contexts of the standard cell C 70 .
- the cell context generator 320 may generate a context of a target standard cell (for example, C 70 ) including a pattern of a front-end-layer and may randomly place standard cells (for example, C 71 to C 74 ), including a pattern of a front-end-layer among standard cells defined in the cell library D 310 , near the target standard cell (for example, C 70 ), thereby generating the context of the target standard cell.
- the cell context generator 320 may place a polygon of a layer, having various shapes, near a standard cell C 80 , thereby generating a context of the standard cell C 80 .
- the cell context generator 320 may randomly place a plurality of patterns P 11 to P 16 , respectively including different patterns of a front-end-layer, near the standard cell C 80 , thereby generating contexts of the standard cell C 80 .
- FIG. 14 illustrates an example of LLE data D 330 according to an exemplary embodiment.
- the LLE estimator 340 of the LLE data generator 300 may estimate an LLE corresponding to various contexts generated by the cell context generator 320 , thereby generating the LLE data D 330 .
- FIG. 14 illustrates a portion of the LLE data D 330 representing a change in a physical characteristic of an inverter INV which is a standard cell corresponding to an LLE.
- the LLE estimator 340 may generate the LLE data D 330 , based on a context and parameters of a characteristic function determined based on the context. For example, the LLE estimator 340 may generate the LLE data D 330 which includes the context and the parameters of the characteristic function determined based on the context, and may generate the LLE data D 330 which includes the context and a value of a characteristic function corresponding to the context. Also, as illustrated in FIG. 14 , the LLE estimator 340 may generate the LLE data D 330 including a ratio or a difference between the value of the characteristic function corresponding to the context and a value of a characteristic function based on an intrinsic parameter of a standard cell, instead of the value of the characteristic function corresponding to the context.
- the intrinsic parameter of the standard cell may denote a parameter of a characteristic function for calculating a value representing an intrinsic physical characteristic of the standard cell like a case where an LLE does not occur in the standard cell or a case where an average LLE occurs in the standard cell.
- columns of a table may represent intervals between patterns of a front-end-layer in an X direction, and rows of the table may represent lengths of the patterns of the front-end-layer which are aligned in a Y direction.
- the physical characteristic of the inverter INV may be a value of a characteristic function based on an intrinsic parameter of the inverter INV.
- the table may include the changes in physical characteristic, respectively corresponding to various contexts of the inverter INV, as items, and for example, each of the items may correspond to a delay time of the inverter INV.
- each of the items may correspond to a delay time of the inverter INV.
- the delay time of the inverter INV may be further deteriorated by 7.37% (i.e., extension by 7.37%) than a delay time REF based on an intrinsic parameter, based on an LLE caused by the patterns of the front-end-layer.
- the delay time REF of the inverter INV based on the intrinsic parameter may be included in the cell library D 310 or may be calculated from a characteristic function and an intrinsic parameter included in the cell library D 310 .
- the LLE data D 330 including the table of FIG. 14 may be used for the instance characterizer 220 to characterize a layout of an IC.
- FIG. 15 is a block diagram of a context data generator 400 according to an exemplary embodiment.
- the context data generator 400 may include a procedure including a series of instructions, and an operation of the context data generator 400 may be performed by a processor (for example, the CPU 11 of FIG. 1 ) that executes the series of instructions.
- the context data generator 400 may be included in the implementation group 100 of FIG. 2 , and thus, context data D 150 may be generated along with layout data D 100 .
- the context data generator 400 may be included in the analysis group 200 of FIG. 3 , and thus, the context data D 150 may be generated from the layout data D 100 .
- the context data generator 400 may include an instance selector 420 and an instance context extractor 440 .
- the instance selector 420 may select an instance, of which a context is to be generated, from a layout of an IC. For example, the instance selector 420 may provide all instances included in the IC to the instance context selector 440 , or may select some instances from among the instances included in the IC to provide the selected instances to the instance context extractor 440 . In an embodiment, the instance selector 420 may recognize instances included in a critical path of the IC, based on input data D 010 or layout data D 100 , or may select the instances included in the critical path to provide the selected instances to the instance context extractor 440 . Also, in an embodiment, the instance selector 420 may select instances included in a clock tree of the IC to provide the selected instances to the instance context extractor 440 . The instance selector 420 may select instances, which are high in relation to a performance of the IC which is to be analyzed, among the instances included in the IC and may provide the selected instances to the instance context extractor 440 .
- the instance context extractor 440 may generate the context data D 150 , including information (i.e., a context) about peripheral layouts of the instances selected by the instance selector 420 , from the layout data D 100 .
- the instance context extractor 440 may generate the context data D 150 including a context of an instance, based on a pattern of a front-end-layer included in the instance and a pattern of a front-end-layer included in a peripheral layout of the instance.
- the cell context generator 320 of FIG. 12 may place arbitrary various layouts near a standard cell so as to generate the LLE data D 330 , thereby generating various contexts of the standard cell.
- the instance context extractor 440 of FIG. 15 may extract a context of an instance from an actual peripheral layout of an instance placed in a layout of the IC, based on the layout data D 100 .
- FIG. 16 illustrates an exemplary operation of the instance context extractor 440 of FIG. 15 .
- FIG. 16 is a plan view illustrating a portion of a layout of an IC, and the instance context extractor 440 may generate a context of an instance INV_ 1 of an inverter INV. That is, the instance INV_ 1 may be an instance selected by the instance selector 420 of FIG. 15 and may be provided to the instance context extractor 440 .
- the instance context extractor 440 may extract a context of an instance, based on a pattern of a front-end-layer included in the instance and a pattern of a front-end-layer included in a peripheral layout of the instance. For example, as illustrated in FIG. 15 , the instance context extractor 440 may extract, as a context of the instance INV_ 1 , a length DY of aligned patterns of a front-end-layer included in an LLE causing structure LLE 3 related to the instance INV_ 1 and an X-direction distance DX between patterns of a front-end-layer adjacent to the aligned patterns. That is, in the embodiment of FIG.
- the instance context extractor 440 may extract 3 y and 8 x as the context of the instance INV_ 1 . Therefore, the instance characterizer 220 of FIG. 11 may deteriorate by 3.06% (i.e., extension by 3.06%) a delay time of the instance INV_ 1 , based on LLE data D 330 including the table of FIG. 14 and context data D 150 including the context of the instance INV_ 1 .
- FIG. 17 is a flowchart illustrating an IC designing method according to an exemplary embodiment.
- FIG. 17 illustrates a method of generating a layout of an IC by considering an LLE, and the method illustrated in FIG. 17 may be performed by the implementation group 100 of FIG. 3 .
- the IC designing method may include operations S 120 , S 140 , and S 160 .
- Operation S 120 involves placing first instances of pre-placement cells so as to decrease occurrence of an LLE causing structure resulting from placement of second instances of logic cells.
- the LLE causing structure may include patterns of a front-end-layer, and in order to decrease occurrence of the LLE causing structure caused by patterns of a front-end-layer included in the second instances, the first instances may be pre-placed.
- the first instances may be instances of a pre-placement cell and may be defined in input data D 010 or may be added based on a design rule D 320 .
- the LLE rule D 322 included in the design rule D 320 may include information about the LLE causing structure, and the first instances may be placed so as to decrease occurrence of the LLE causing structure, based on the LLE rule D 322 .
- Operation S 140 involves placing the second instances in an area where the first instances are not placed.
- the second instances may be instances of a logic cell and may start to be placed adjacent to the placed first instances so as to observe the design rule D 320 . Due to the placement of the first instances which occurred in operation S 120 , an occurrence of LLE causing structure resulting from placement of the second instances may be reduced.
- Operation S 160 involves routing connections of the first and second instances. For example, interconnections that connect the first and second instances may be generated, and layout data D 100 which includes information about placement of the first and second instances and physical information about the interconnections may be generated.
- FIG. 18 is a flowchart illustrating an example of operation S 120 of FIG. 17 according to an exemplary embodiment.
- operation S 120 involves placing first instances of pre-placement cells so as to decrease occurrence of an LLE causing structure caused by placement of second instances of logic cells.
- operation S 120 is illustrated as including two operations S 122 and S 124 .
- operation S 120 may include one of the two operations, or two operations S 122 and S 124 which may be performed in parallel or sequentially.
- Operation S 122 involves placing the first instances in order for edges of the first instances not to be aligned. For example, as described above with reference to FIGS. 5 and 6 , the first instances may be placed so that edges of first instances closest to each other are not aligned. Accordingly, an LLE causing structure based on the second instances including a pattern of a front-end-layer formed in an edge is reduced.
- Operation S 124 involves alternately placing instances of dummy cells having different widths.
- a pre-placement cell may include a multi-height cell placed in a series of rows, and an instance corresponding to the multi-height cell may include an edge vertical to the series of rows.
- a plurality of instances of the pre-placement cell may be aligned and placed based on the design rule D 320 and, thus, edges of first instances vertical to the series of rows may be provided.
- the instances of the dummy cells having different widths may be alternately placed adjacent to an edge of at least one first instance vertical to the series of rows, and thus, an LLE causing structure based on the second instances including a pattern of a front-end-layer formed in an edge is reduced.
- FIG. 19 is a flowchart illustrating a method of shifting an instance for removing an LLE causing structure, according to an exemplary embodiment.
- operations S 182 and S 184 illustrated in FIG. 19 may be included in operation S 140 of FIG. 17 , or may be performed by, for example, an ECO after operation S 160 of FIG. 17 is performed.
- Operation S 182 involves detecting an LLE causing structure.
- An LLE rule D 322 included in a design rule D 320 may include information about the LLE causing structure, and the LLE causing structure may be detected from instances (for example, the first and second instances placed in operations S 120 and S 140 of FIG. 17 ), based on the LLE rule D 322 .
- the LLE rule D 322 may define patterns of a front-end-layer, which are aligned to have a certain length or more, as an LLE causing structure, and the patterns of the front-end-layer which are aligned to have the certain length or more may be detected based on the LLE rule D 322 .
- Operation S 184 involves shifting at least one instance associated with the LLE causing structure. That is, in order to remove the detected LLE causing structure, at least one of instances (for example, the first and second instances of FIG. 17 ) associated with patterns of a front-end-layer included in the LLE causing structure may be shifted. For example, as illustrated in FIG. 10A , one instance may be shifted in one row, and as illustrated in FIG. 10B , two or more instances may be shifted in one row.
- FIG. 20 is a flowchart illustrating an IC designing method according to an exemplary embodiment.
- FIG. 20 illustrates a method of analyzing a performance of an IC by considering an LLE, and the IC designing method may include operations S 220 , S 240 , S 260 , and S 280 .
- Operation S 220 involves calculating a physical characteristic of an instance based on LLE data D 330 and context data D 150 .
- the physical characteristic of the instance may denote a physical characteristic which is changed or maintained from an intrinsic physical characteristic of a standard cell corresponding to the instance, based on an LLE caused by a peripheral layout (i.e., a context) of the instance.
- LLE data D 330 may include information about the changes in a physical characteristic of a standard cell corresponding to various contexts
- context data D 150 may include information about a context of an instance extracted from the layout data D 100 .
- the LLE data D 330 may be generated in operation S 260
- the context data D 150 may be generated in operation S 280 .
- Operation S 240 analyzes a performance of an IC based on the physical characteristic of the instance.
- a netlist of the IC may be extracted from the layout data D 100 , based on a cell library D 310 and the calculated physical characteristic of the instance, and the extracted netlist may include information about elements (for example, a resistor and/or a capacitor) for reflecting an actual operation based on the layout of the IC.
- a performance (for example, timing characteristic, power characteristic, noise characteristic, etc.) of the IC may be analyzed based on the extracted netlist, and result data D 200 including information about the performance of the IC may be generated.
- Operation S 260 involves generating the LLE data D 330 from the cell library D 310 . Operation S 260 may be performed before operations S 220 and S 240 are performed, and may include operations S 262 and S 264 .
- Operation S 262 involves generating a plurality of contexts of a standard cell.
- another standard cell for example, the same or different standard cells included in the cell library S 310 may be variously placed near the standard cell, and thus, the plurality of contexts of the standard cell may be generated.
- patterns having various shapes formed in a front-end-layer may be placed near the standard cell, and thus, the plurality of contexts of the standard cell may be generated.
- the cell library D 310 may include a characteristic function of the standard cell, and parameters of the characteristic function respectively corresponding to the contexts may be determined. Accordingly, a plurality of physical characteristics based on a plurality of contexts may be calculated for one standard cell, and the LLE data D 330 including information about the physical characteristics may be generated. For example, the LLE data D 330 including a ratio or a difference between a value of a characteristic function corresponding to an intrinsic parameter of a standard cell and a value of a characteristic function corresponding to a parameter determined based on a context may be generated.
- Operation S 280 involves generating the context data D 150 from the layout data D 100 . Operation S 280 may be performed before operations S 220 and S 240 are performed, and may include operations S 282 and S 284 .
- Operation S 282 involves selecting instances of which contexts are to be generated. All or some of the instances included in the IC may be selected based on the input data D 010 or the layout data D 100 . For example, instances included in a critical path of the IC may be selected, or instances included in a clock tree may be selected.
- Operation S 284 involves extracting contexts of the selected instances.
- the context data D 150 including information (i.e., a context) about a peripheral layout of each of the instances which have been selected in operation S 282 may be generated from the layout data D 100 .
- a context of a selected instance may be extracted based on a pattern of a front-end-layer included in the selected instance and a pattern of a front-end-layer included in a peripheral layout of the selected instance.
- FIG. 21 is a flow chart illustrating the manufacturing process of an integrated circuit, including methods of designing according to FIGS. 17-20 .
- a netlist is generated in step S 1300 .
- the net list may comprise a gate level netlist and, as is known, may comprise a plurality of instances with gate level logic functions (e.g., NAND logic, NOR logic, inversion, etc.) and interconnections between these instances.
- the netlist may be generated by hardware description language (e.g., Verilog) provided by a circuit engineer.
- step S 1310 a plurality of design rules are created. These design rules may be provided by process engineers that design various semiconductor processes to create various portions of an integrated circuit. For example, an engineer specializing in plasma processing used for etching, may provide design rule(s) designating a minimum via (or contact hole) size, whereas an engineer specializing in chemical mechanical polishing, may provide design rule(s) describing wiring densities which may require the use of dummy patterns in certain circumstances. Examples of design rules have been identified at D 320 of FIG. 3 and the accompanying text.
- a plurality of standard cell layouts is created to form a standard cell library.
- the standard cell layouts may comprise a layout design to implement a logic function of a corresponding instance of the netlist.
- a standard cell layout may describe a plurality of layers and their patterning that form the elements of the standard cell layout, such as one or more of wiring, vias, active regions of a semiconductor substrate, device isolation regions in a semiconductor substrate (e.g., to define the active regions), source/drain regions of transistors, channel regions of transistors, gate regions of transistors, etc.
- Some of the standard cells layouts may be designed to conform with (not violate) the plurality of design rules.
- the standard cell layouts may be designed so that a first layout region may violate one or more of the plurality of design rules and another region does not violate the one or more design rules.
- the first layout region may be separately designed and correspond to a graphical representation of a portion of the standard cell layout.
- the first layout region may be fixed so that the representation of this region does not vary (e.g., in size, relative location and location of its elements) whereas the other region may be allowed to vary.
- Further exemplary detail of the standard cell layouts have been previously described herein in further detail, e.g., with respect to FIGS. 2-16 .
- some of the standard cell layouts may correspond to the standard cells previously discussed above.
- an integrated circuit layout is generated, such as the layout for the entire integrated circuit.
- the integrated circuit layout may be generated by a place and routing function, using the gate level netlist and the standard cell layouts of the standard cell library.
- Standard cells layouts may correspond to instances of the netlist so that logical functions of an instance of the netlist may be implemented by the layout structure of the corresponding standard cell layout.
- step S 1340 design rule checking may be performed on the integrated circuit layout to determine if it violates any of the design rules. Portions of the layout that correspond to the first layout region (or similar regions) may be identified and design rule violations corresponding to these portions may be ignored or may not be tested for design rule violations. If there are design rule violations in other portions not identified so, the layout may be modified (step S 1350 ) and tested again at step S 1340 until it passes this design rule checking step.
- step S 1360 photomasks may be created based upon the integrated circuit layout.
- step S 1370 a plurality of layers may be formed on a semiconductor substrate. The plurality of layers may be patterned using the photomasks created in step S 1350 . The patterned layers may correspond to the integrated circuit layout and portions of these patterned layers may correspond to standard cells of the standard cell library. The thus formed integrated circuit may be packaged in a semiconductor package and used in various manners in systems according to its intended use.
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DE102019124928A1 (en) | 2018-09-28 | 2020-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | INTEGRATED CIRCUIT DESIGN USING FUZZY MACHINE LEARNERS |
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CN111177996B (en) * | 2020-01-02 | 2023-06-30 | 天津飞腾信息技术有限公司 | Special pattern evading method and device for optimizing manufacturability of integrated circuit |
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