KR102320823B1 - Integrated circuit and method of designing layout thereof - Google Patents

Abstract

A method for designing a layout of an integrated circuit implemented by a computer system or processor according to an embodiment of the present disclosure includes the steps of receiving input layout data, checking a design rule with respect to a plurality of patterns, and merging the first of the violating first and second patterns with a third pattern connected to the same net as the first pattern and generating output layout data.

Description

INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT THEREOF

TECHNICAL FIELD The present invention relates to an integrated circuit, and more particularly, to an integrated circuit and a method for designing a layout of the integrated circuit.

As semiconductor manufacturing process technology develops, the size of transistors is getting smaller and, accordingly, a larger number of transistors are being integrated into semiconductor devices. For example, System-On-Chip (SOC), which refers to an integrated circuit (IC) that includes all the components of a computer or other electronic system on a single chip, is widely used in various applications. In addition, as the performance of the application is improved, a semiconductor device including more components is required.

Meanwhile, as the size of a transistor integrated in a semiconductor device becomes smaller and smaller, the difficulty of a process for manufacturing a semiconductor device increases. To this end, as well as advances in semiconductor manufacturing process technology, the importance of design for manufacturing (DFM) in consideration of the semiconductor manufacturing process in the stage of designing a semiconductor device and using a more convenient semiconductor manufacturing process is increasing. have.

The technical idea of the present disclosure relates to an integrated circuit and a method for designing a layout of the integrated circuit, and to provide an integrated circuit and a computer implemented method for designing the layout thereof.

A computer implemented method for layout design of an integrated circuit including a plurality of patterns in one layer according to an aspect of the technical concept of the present disclosure includes arrangement information of the plurality of patterns and each of the plurality of patterns in a plurality of receiving input layout data including coloring information corresponding to one of the masks; checking a design rule of the layer with respect to the plurality of patterns; For the first and second patterns that violate the design rule, changing the arrangement information so that the first pattern is merged with a third pattern connected to the same net as the first pattern, and the first and third patterns The method may include updating the coloring information so that the merged pattern corresponds to the mask corresponding to the third pattern.

According to an aspect of the technical concept of the present disclosure, a computer implemented method for layout design of an integrated circuit including a plurality of patterns in one layer includes: receiving input layout data including arrangement information of the plurality of patterns; generating coloring information in which each of the plurality of patterns corresponds to one mask among a plurality of masks, and generating output layout data including the coloring information, wherein the coloring information is generated Changing the arrangement information so that at least two patterns connected to the same net among the plurality of patterns are merged, and the plurality of patterns and a pattern merged from the at least two patterns are combined with the plurality of patterns. The method may include generating the coloring information to correspond to one of the masks.

A computer-readable non-transitory storage medium according to an aspect of the inventive concept may store a plurality of instructions for executing a computer-implemented method for designing a layout of the integrated circuit.

According to the method of designing the layout of an integrated circuit according to the technical spirit of the present disclosure, a patterning technique using a multi-mask can be easily utilized, and the degree of integration of the resulting layout of the integrated circuit can be improved.

In addition, according to the method for designing the layout of the integrated circuit according to the technical spirit of the present disclosure, it is possible to shorten the time required for designing the layout of the integrated circuit.

1 is a flowchart illustrating a method of designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
2 is a diagram schematically illustrating multi-mask patterning.
3 is a plan view illustrating a layout of an integrated circuit including a plurality of patterns.
4 is a plan view illustrating a layout of an integrated circuit including patterns that violate a design rule.
5A and 5B are diagrams illustrating a process in which a method for designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure is applied to the layout of the integrated circuit.
6 is a flowchart illustrating an example of step S40 of FIG. 1 according to an exemplary embodiment of the present disclosure.
7 is a flowchart illustrating an example of step S60 of FIG. 1 according to an exemplary embodiment of the present disclosure.
8 is a plan view illustrating a layout of an integrated circuit including a plurality of standard cells.
9A and 9B are diagrams illustrating a process in which a method for designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure is applied to the layout of the integrated circuit.
10 is a flowchart illustrating an example of step S62 of FIG. 7 according to an exemplary embodiment of the present disclosure.
11A and 11B are diagrams illustrating a process in which a method for designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure is applied to the layout of the integrated circuit.
12 is a flowchart illustrating a method of designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
13 is a flowchart illustrating an example of step S140 of FIG. 12 according to an exemplary embodiment of the present disclosure.
14 is a block diagram illustrating a computer-readable storage medium according to an exemplary embodiment of the present disclosure.
15 is a block diagram illustrating a computer system according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art. Since the present invention may have various changes and may have various forms, specific embodiments will be illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals are used for like elements. In the accompanying drawings, the dimensions of the structures are enlarged or reduced than the actual size for clarity of the present invention.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Also, terms such as first and second may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be termed a second component, and similarly, a second component may also be termed a first component.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings in the context of the related art, and unless explicitly defined in the present application, they should be interpreted in an ideal or excessively formal meaning. doesn't happen

1 is a flowchart illustrating a method of designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure. The integrated circuit or the layout of the integrated circuit may include a structure in which a plurality of layers are stacked, and may include a plurality of patterns formed in each of the plurality of layers. The pattern may refer to a shape of a material formed according to a semiconductor manufacturing process, and a plurality of patterns may be formed on one layer. For example, the pattern may be formed on a specific layer to form a via that electrically connects conductors formed on different layers, or a line for moving an electrical signal in one layer may be formed. The pattern may be formed through a mask process, an etching process, and/or a deposition process.

In order to increase the degree of integration of an integrated circuit, a size of a pattern or an interval between different patterns is required to be reduced. Accordingly, multi-mask patterning using a plurality of masks instead of a single mask may be used to form patterns included in one layer. According to multi-mask patterning, each of the plurality of patterns included in one layer may correspond to one of the plurality of masks, and may be formed based on the corresponding mask. For example, two patterns to be formed on one layer may be disposed closer to each other when they are respectively formed based on two different masks than when they are formed based on one mask. Details of the multi-mask patterning will be described later with reference to FIG. 2 .

Corresponding each of the plurality of patterns to be formed in one layer to one of the plurality of masks may be referred to as coloring the plurality of patterns, and includes a correspondence between the plurality of patterns and the plurality of masks. The data to be used may be referred to as coloring information. That is, patterns having the same color may be formed based on the same mask, and patterns having different colors may be formed based on different masks. The method for designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure enables multi-mask patterning to be easily utilized by effectively performing coloring on a plurality of patterns, thereby improving the degree of integration of the integrated circuit. . In addition, the time required to design the layout of the integrated circuit may be reduced.

The layouts of the integrated circuit shown in the drawings below may be graphic data derived from layout data defining the layout of the integrated circuit. In addition, in the following description, components included in the layout of the integrated circuit are defined from the layout data, and may be created, removed, or modified by changing the layout data.

Referring to FIG. 1 , in step S20, an operation of receiving input layout data may be performed. The input layout data may include geometric information about the layout of the integrated circuit, such as Graphic Data System II (GDSII). For example, the input layout data may include arrangement information for a plurality of patterns formed in one layer, and the arrangement information may include information about a location, size, and a connected net of each of the plurality of patterns. can Also, in this embodiment, the input layout data may include coloring information. The coloring information included in the input layout data may be defined as a default when the layout of the integrated circuit is generated, or may be generated by a coloring algorithm of a semiconductor design tool based on the layout of the integrated circuit.

In operation S40 , an operation of checking design rules for a plurality of patterns may be performed. A design rule may include a plurality of numerical values to be observed in a process of designing a layout of an integrated circuit based on a given semiconductor manufacturing process. For example, a design rule may include a minimum width of a pattern, and may include a minimum spacing between two patterns formed in one layer. In addition, the design rule may include a minimum distance between patterns formed based on the same mask in multi-mask patterning and a minimum distance between patterns each formed based on different masks. In the present embodiment, the plurality of patterns may be formed on the same layer, and it may be determined whether a design rule is complied with with respect to the plurality of patterns.

In operation S60 , an operation of merging the first pattern among the first and second patterns violating the design rule with the third pattern may be performed. For example, the first and second patterns may correspond to the same mask, and the distance between the first and second patterns may be smaller than a minimum distance between patterns formed based on the same mask according to a design rule. . The third pattern is a pattern connected to the same net as the first pattern, and the first pattern may be merged with the third pattern. The net corresponds to a node in the circuit diagram equivalent to the layout of the integrated circuit, and patterns connected to the same net may have the same potential (or substantially similar potential due to parasitic resistance) during operation of the integrated circuit.

The merged pattern from the first and third patterns may correspond to a mask corresponding to the third pattern. Accordingly, the violated design rule for the first and second patterns may be observed for the merged pattern and the second pattern from the first and third patterns. Merging of the first and third patterns may be realized by deleting arrangement information corresponding to the first and third patterns from the input layout data, and generating arrangement information corresponding to the merged pattern. Also, by updating the coloring information, the merged pattern may correspond to the mask to which the third pattern corresponds.

When the first and second patterns violate a design rule, the mask to which the first or second patterns correspond may be changed in order to overcome this. However, if the mask corresponding to the first pattern is changed, the design rule may be violated between the first pattern and the patterns adjacent to the first pattern, and to overcome this, the mask corresponding to another pattern is changed action may be repeated. Alternatively, the position of the first or second pattern may be changed such that the first and second patterns conform to the design rule. However, if the position of the first pattern is changed, a chain movement of other patterns (eg, a pattern in the same layer as the first pattern or a pattern in a different layer) may occur according to the movement of the first pattern, and , space may be wasted unnecessarily. Accordingly, the method for designing the layout of the integrated circuit according to the exemplary embodiment of the present disclosure can reduce the time required for designing the layout of the integrated circuit by enabling coloring to be easily performed. When the plurality of patterns satisfy the design rule in step S40, step S60 may be omitted, and step S80 may be performed subsequent to step S40.

In step S80, an operation of generating output layout data may be performed. For example, output layout data including the changed arrangement information or updated coloring information may be generated in step S60. Since the output layout data includes not only arrangement information of a plurality of patterns but also coloring information, a semiconductor manufacturing process for manufacturing an integrated circuit may be derived based on the output layout data.

2 is a diagram schematically illustrating multi-mask patterning. As described above, since the plurality of patterns formed on one layer is formed based on the plurality of masks, the degree of integration of the integrated circuit may be improved.

Referring to FIG. 2 , a plurality of patterns P1 to P4 may be formed based on a plurality of masks 101 to 103 . That is, each of the plurality of patterns P1 to P4 formed in the layer positioned on the first layer L1 (or included in the layer positioned on the first layer L1) is a plurality of masks 101 to 103 . It may be formed based on one of the For example, the first and second patterns P1 and P2 may be formed based on the first mask 101 , and the third pattern P3 may be formed based on the second mask 102 , , the fourth pattern P4 may be formed based on the third mask 103 .

According to the multi-mask patterning, the degree of integration of patterns formed in one layer may be improved. For example, in FIG. 2 , the first pattern and the third pattern may be respectively formed based on different masks 101 and 102 , and thus may be spaced apart from each other by a closer distance than when the same mask is formed. The number of masks used to form a plurality of patterns formed in one layer may be determined based on a semiconductor manufacturing process, and a time taken for manufacturing an integrated circuit may be considered in determining the number of masks.

Although only the plurality of masks 101 to 103 for forming the plurality of patterns P1 to P4 are illustrated in FIG. 2 , the plurality of patterns P1 to P4 are additionally performed in the deposition process and/or etching process. can be formed according to In addition, although the plurality of patterns P1 to P4 in FIG. 2 are illustrated as protruding on the first layer L1, the plurality of patterns formed in one layer according to exemplary embodiments of the present disclosure is It may be a pattern for forming a hole or a via.

3 is a plan view illustrating a layout of an integrated circuit including a plurality of patterns. Specifically, FIG. 3 shows a plan view of a plurality of patterns P1 to P4 formed based on the multi-mask patterning shown in FIG. 2 , and the plurality of patterns P1 to P4 is located on the first layer L1. It can be formed in layers.

As described above, the design rule may include D_same, which is the minimum spacing between two patterns formed in one layer based on the same mask, and two patterns formed in one layer based on different masks. It may include D_diff, which is the minimum distance between them. Due to the effect of multi-mask patterning, D_diff may be smaller than D_same. In the layout of the integrated circuit according to the input layout data, a distance between the plurality of patterns may be greater than or equal to D_diff. The distance between the patterns formed based on different masks may be the minimum distance achievable from a given semiconductor manufacturing process, and accordingly, the distance between the plurality of patterns formed in one layer in the input layout data is greater than D_diff. or may be designed to be the same. A coloring operation of matching each of the plurality of patterns spaced apart from each other by D_diff or more to one of the plurality of masks may be performed, and coloring information may be generated.

2 and 3 together, the distance D1 between the first pattern P1 and the third pattern P3 formed based on different masks 101 and 102, respectively, is D_diff according to the design rule. may be greater than (ie, D1 > D_diff). If D1 is smaller than D_diff, the first pattern P1 and the third pattern P3 may be classified as patterns that violate the design rule. Similarly, the distance D3 between the first pattern P1 and the third pattern P3 respectively formed based on the different masks 101 and 103 may be greater than D_diff according to the design rule (ie, D3 ). > D_diff). The distance D2 between the first pattern P1 and the second pattern P2 formed based on the same mask, that is, the first mask 101 may be greater than D_same according to the design rule (ie, D2 > D_same). ). As such, a violation of a design rule by colored patterns may be referred to as a color conflict.

4 is a plan view illustrating a layout of an integrated circuit including patterns that violate a design rule. As described above, the plurality of patterns formed in one layer may correspond to one of the plurality of masks by coloring, and the coloring information may be defined as a default when generating the layout of the integrated circuit, and the integrated circuit It may be generated by a coloring algorithm of a semiconductor design tool based on the layout of . In FIG. 4 , first, second, sixth, and seventh patterns 10_1 , 10_2 , 10_6 , and 10_7 may be formed based on a first mask, and third and eighth patterns 10_3 and 10_8 . may be formed based on the second mask, and the fourth and fifth patterns 10_4 and 10_5 may be formed based on the third mask.

Referring to FIG. 4 , the layout 10 of the integrated circuit may include a plurality of patterns 10_1 to 10_8 formed in one layer. The first pattern 10_1 and the second pattern 10_2 formed based on the first mask may be spaced apart by Dx, and when Dx is smaller than D_same according to the design rule, the first pattern 10_1 and the second pattern 10_1 and the second pattern ( 10_2) can be classified as a pattern that violates the design rule.

As a method for complying with the design rule, when the first pattern 10_1 corresponds to a mask different from the first mask, for example, a second mask, the first pattern 10_1 and the third pattern 10_3 conform to the design rule. Design rules may be violated due to D_same. Also, when the first pattern 10_1 corresponds to the third mask, the first pattern 10_1 and the fourth pattern 10_4 may violate the design rule due to D_same according to the design rule. As such, mapping one of the violating patterns to another mask may create new patterns that violate the design rule.

As another method for complying with the design rule, when the first pattern 10_1 is moved so that the first pattern 10_1 is spaced apart from the second pattern 10_2 further than D_same, the first pattern 10_1 and the first pattern As the distance between other patterns adjacent to (10_1), for example, the fourth pattern 10_4 or the fifth pattern 10_5 decreases, the design rule may be violated due to D_diff according to the design rule. As such, moving the position of one of the violated patterns may create new patterns that violate the design rule.

5A and 5B are diagrams illustrating a process in which a method for designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure is applied to the layout of the integrated circuit. Specifically, FIGS. 5A and 5B are diagrams illustrating a process of resolving the violation of the design rule with respect to the first and second patterns 10_1 and 10_2 that violate the design rule in the layout 10 of the integrated circuit of FIG. 4 . am. 4 , the layout 10 ′ of the integrated circuit in FIGS. 5A and 5B may include a plurality of patterns 10_1 ′ to 10_8 ′ formed in the same layer, and the first and second patterns 10_1 ′ to 10_8 ′ 10_1' and 10_2' are formed based on the same mask (ie, the first mask), and a distance between the first and second patterns 10_1' and 10_2' may be smaller than D_same.

According to an exemplary embodiment of the present disclosure, among the patterns adjacent to the first and second patterns 10_1 ′ and 10_2 ′ that violate the design rule, the same as the first or second pattern 10_1 ′, 10_2 ′ A pattern connected to the net can be selected. For example, as shown in FIG. 5A , when the first pattern 10_1 ′ and the third pattern 10_3 ′ are connected to the same net, for example, a power supply net, the third pattern 10_3 ′ may be selected. . As shown as a group G in FIG. 5A , the first pattern 10_1 ′ and the third pattern 10_3 ′ connected to the same net may be grouped.

According to an exemplary embodiment of the present disclosure, grouped patterns may be merged. That is, a plurality of grouped patterns may be merged into one pattern. For example, as shown in FIG. 5B , the first pattern 10_1 ′ and the third pattern 10_3 ′ of FIG. 5A may be merged, and accordingly, the first pattern 10_1 ′ and the third pattern 10_1 ′ and the third pattern 10_3 ′ may be merged. A merged pattern 10_13 may be generated from 10_3'). The merged pattern 10_13 may be formed by extending the first pattern 10_1' and/or the third pattern 10_3'. The merged pattern 10_13 may correspond to one of a plurality of masks, for example, coloring information such that the merged pattern 10_13 corresponds to a mask (ie, the second mask) corresponding to the third pattern 10_3'. can be updated.

Referring to FIG. 5B , the design rule may be observed due to the merged pattern 10_13 corresponding to the second mask. That is, since the merged pattern 10_13 corresponds to the second mask, the distance between the second pattern 10_2' corresponding to the first mask and the merged pattern 10_13 may be compared with D_diff according to the design rule, The distance between the two patterns 10_2' and the merged pattern 10_13 may be greater than D_diff. Accordingly, the color collision generated between the first pattern 10_1 ′ and the second pattern 10_2 ′ of FIG. 5A may be easily resolved.

Although FIGS. 5A and 5B show an example in which two patterns are merged, it will be understood that the technical spirit of the present disclosure is not limited thereto. That is, the group G in FIG. 5A may further include other patterns connected to the same net as the first pattern 10_1' as well as the first pattern 10_1' and the third pattern 10_3', and the group ( The patterns grouped by G) can be merged.

6 is a flowchart illustrating an example of step S40 of FIG. 1 according to an exemplary embodiment of the present disclosure. As described above with reference to FIG. 1 , in step S40 of FIG. 1 , an operation of checking a design rule for a plurality of patterns formed in one layer may be performed. That is, whether a color collision occurs may be checked. FIG. 6 will be described based on a state in which the design rule is violated with respect to the first pattern and the second pattern corresponding to the first mask among the plurality of patterns in step S40 of FIG. 1 . That is, in FIG. 6 , the distance between the first pattern and the second pattern may be smaller than D_same according to the design rule.

According to an exemplary embodiment of the present disclosure, before step S60 of FIG. 1 is performed, an operation of matching a pattern violating a design rule to another mask may be performed in step S40. That is, before selecting the third pattern connected to the same net as the first pattern by step S60 and merging the first pattern and the third pattern, the first or second pattern without affecting the patterns adjacent to the first and second patterns By matching only the two patterns to the other masks, it can be judged whether the design rule can be complied with. That is, when the design rule is not complied with by matching only the first or second pattern to the other mask, the first pattern and the third pattern may be merged by step S60 . Hereinafter, an example of step S40 of FIG. 1 will be described in detail with reference to FIG. 6 .

Referring to FIG. 6 , in step S41 performed subsequent to step S20 of FIG. 1 , an operation of matching the first or second pattern to a mask different from the first mask may be performed. That is, the first or second pattern may correspond to a mask different from the first mask. In step S43, an operation of checking design rules for patterns adjacent to the first and second patterns (eg, patterns spaced apart from the first and second patterns by a predetermined distance or less) and the first and second patterns This can be done. As the mask corresponding to the first or second pattern is changed due to operation S41, it may be determined whether patterns adjacent to the first and second patterns and the first and second patterns comply with the design rule.

In operation S45, an operation of determining whether patterns adjacent to the first and second patterns and the first and second patterns pass a design rule may be performed. If the design rule is passed, an operation of updating the coloring information may be performed in step S49. That is, the coloring information may be updated so that the mask corresponding to the first or second pattern is changed. Step S80 of FIG. 1 for generating output layout data including the updated coloring information may be performed subsequent to step S49.

If the design rule is not passed in step S45, an operation of determining whether another mask to correspond to the first or second pattern exists in step S47 may be performed. As described above, the number of masks usable for the plurality of patterns formed in one layer may be predetermined, and it is determined by step S41 whether there are other masks other than the masks corresponding to the first or second pattern. It may be determined in step S45. When there is another mask to correspond to the first or second pattern, step S41 may be performed subsequent to step S47. On the other hand, when there is no mask corresponding to the first or second pattern, step S60 of FIG. 1 of merging the first pattern and the third pattern may be performed following step S47.

7 is a flowchart illustrating an example of step S60 of FIG. 1 according to an exemplary embodiment of the present disclosure. As described above with reference to FIG. 1 , an operation of merging the first pattern among the first and second patterns violating the design rule with the third pattern may be performed in step S60 of FIG. 1 . FIG. 7 will be described based on a state in which a design rule is violated with respect to the first pattern and the second pattern corresponding to the first mask among the plurality of patterns in step S60 of FIG. 1 .

Referring to FIG. 7 , in operation S62 , an operation of changing arrangement information of input layout data so that the first and third patterns are merged may be performed. The third pattern is a pattern connected to the same net as the net to which the first pattern is connected, and in step S62 , arrangement information included in the input layout data may be changed so that the first pattern and the third pattern are merged. For example, arrangement information corresponding to the first pattern and the third pattern may be deleted, and arrangement information corresponding to the merged pattern may be generated from the first pattern and the third pattern. An example of step S62 will be described in detail with reference to FIG. 10 .

In operation S64 , an operation of updating the coloring information so that the merged pattern from the first and third patterns corresponds to a mask corresponding to the third pattern may be performed. Since the merged pattern corresponds to the mask corresponding to the third pattern, the design rule may be observed with respect to the merged pattern and the second pattern.

8 is a plan view illustrating a layout 20 of an integrated circuit including a plurality of standard cells. A standard cell may refer to a unit of an integrated circuit whose size satisfies a predetermined rule in its layout. For example, the height of the layout of the standard cells (ie, the length in the first direction perpendicular to the stacking direction of the layout) may be constant, and the width of the standard cells (ie, the stacking direction of the layout and perpendicular to the first direction) may be constant. The length in the second direction) may be different depending on the standard cell. The standard cell may include at least one input pin and/or at least one output pin, process an input signal received through the input pin, and output an output signal through the output pin.

An integrated circuit may be defined as a plurality of standard cells, and a tool for designing the integrated circuit may use a standard cell library containing information about the plurality of standard cells to design the integrated circuit, that is, complete the layout of the integrated circuit. can Tools for designing integrated circuits can connect pins and patterns formed in layers different from those in which the standard cell is formed by placing vias on pins (i.e., input pins and output pins) included in standard cells. . That is, an input signal or an output signal of the standard cell may move by placing a via in the pin of the standard cell.

The via may be formed by a via hole formed by a pattern and a via plug filling the via hole. In the process of designing the layout 20 of the integrated circuit, a design rule may define a spacing between vias. For example, the design rule may include a via-to-via space rule, and the via-to-via space rule may include a minimum spacing between vias. The via-to-via space rule may be determined based on processes for forming vias in a semiconductor manufacturing process, for example, a mask process for forming a pattern for forming vias, an etching process, and/or an etching process.

According to multi-mask patterning, patterns for forming each of the plurality of vias may be formed based on one of the plurality of masks. That is, each of the plurality of vias may be formed based on one of the plurality of masks. Accordingly, the operation of coloring the plurality of patterns formed in one layer may include the operation of coloring the plurality of vias. Also, similarly to checking a design rule for a plurality of patterns, a design rule may be checked for a plurality of vias, and vias violating a design rule may occur. Hereinafter, it may be understood that vias violate a design rule as patterns for forming vias violate a design rule, and coloring vias may be understood as coloring patterns for forming vias.

Referring to FIG. 8 , the layout 20 of the integrated circuit may include a plurality of standard cells 21 to 24 , and the plurality of standard cells 21 to 24 may include a plurality of pins 21_5 , 21_6 , 22_5 , and 22_6 . , 23_5, 23_6, 24_5, and 24_6) and a plurality of vias 21_1, 21_2, 22_1, 22_2, 23_1, 23_2, 24_1, and 24_2, respectively.

In the example illustrated in FIG. 8 , the via 21_1 included in the first standard cell 21 and the via 24_1 included in the fourth standard cell 24 may violate a design rule. Specifically, the via 21_1 and the via 24_1 may correspond to the same mask (ie, the first mask), and may violate a via-to-via space rule that defines a distance between vias in the same mask. . In order to comply with the via-to-via space rule, associating the via 21_1 or via 24_1 with a mask different from the first mask causes the via 21_1 or other vias adjacent to the via 24_1 to be separated as described above. This can cause re-coloring. In addition, in order to comply with the via-to-via space rule, moving the via 21_1 or the via 24_1 to increase the distance between the via 21_1 and the via 24_1 is performed in the first standard cell 21 . ) or the fourth standard cell 24 , or may cause the via 21_1 or other vias adjacent to the via 24_1 to violate the via-to-via space rule. By merging two or more vias according to an exemplary embodiment of the present disclosure, a violation of a design rule, that is, a color collision, may be resolved, and details thereof will be described below with reference to FIGS. 9A and 9B .

9A and 9B are diagrams illustrating a process in which a method for designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure is applied to the layout of the integrated circuit. Specifically, FIGS. 9A and 9B are diagrams illustrating a process of resolving the violation of the design rule with respect to the vias 21_1 and 24_1 violating the design rule in the layout 20 of the integrated circuit of FIG. 8 . Similarly to FIG. 8 , in FIGS. 9A and 9B , the layout 20' of the integrated circuit shows the pins 21_5', 21_6', 22_5', 22_6', 23_5' of the plurality of memory cells 21' to 24', and vias 21_1', 21_2', 22_1', 22_2', 23_1', 23_2', 24_1', and 24_2' connected to 23_6', 24_5', 24_6'. Via 21_1' and via 24_1' correspond to the same mask (ie, the first mask), and via 21_1' and via 24_1' define a distance between vias corresponding to the same mask. Via-to-via space rules may be violated.

According to an exemplary embodiment of the present disclosure, among the patterns adjacent to the vias 21_1 ′ and 24_1 ′ that violate the design rule, a pattern connected to the same net as one of the vias 21_1 ′ and 24_1 ′ is selected. can For example, as shown in FIG. 9A , the via 22_1 ′ connected to the pin 22_5 ′ of the second standard cell 22 ′ may be connected to the conductive line 29 connected to the via 21_1 ′. That is, the via 22_1 ′ may be connected to the same net as the via 21_1 ′.

According to an exemplary embodiment of the present disclosure, the vias 21_1 ′ and the via 22_1 ′ of FIG. 9A connected to the same net may be merged. For example, as shown in FIG. 9B , a merged via 20_12 may be created from the vias 21_1 ′ and 22_1 ′ of FIG. 9A , and the merged via 20_12 is a bar-type via. type via) can be formed. The merged via 20_12 may correspond to one of a plurality of masks, and for example, the merged pattern 20_12 is colored to correspond to the mask (ie, the second mask) corresponding to the via 22_1 ′ of FIG. 9A . Information may be updated.

Referring to FIG. 9B , a design rule may be observed due to the merged via 20_12 corresponding to the second mask. That is, the merged via 20_12 corresponds to the second mask such that the distance between the via 24_1 ′ corresponding to the first mask and the merged via 20_12 defines a distance between vias corresponding to different masks. The -to-via space rule may be applied. Accordingly, the via 24_1 ′ and the merged via 20_12 may conform to the design rule.

10 is a flowchart illustrating an example of step S62 of FIG. 7 according to an exemplary embodiment of the present disclosure. As described above with reference to FIG. 7 , in step S62 of FIG. 7 , an operation of changing the arrangement information of the input layout data so that the first and third patterns are merged may be performed. Here, the first pattern may correspond to the same mask as the second pattern, and the first pattern and the second pattern may violate a design rule. Also, the third pattern may be connected to the same net as the net to which the first pattern is connected.

Referring to FIG. 10 , in step S62_2 , first and third patterns commonly connected to the power net and corresponding to the same mask may be selected. The power supply net is a net for supplying a power supply voltage, eg, VDD or a ground voltage, to all or a part of the integrated circuit, and may be connected to a plurality of patterns entirely or locally in the layout of the integrated circuit. Accordingly, in this example, when the first pattern among the first pattern and the second pattern that violates the design rule is connected to the power supply net, the third pattern connected to the power supply net may be selected. For example, in the example shown in FIG. 9A , the net to which the conductive wire 29 and the vias 21_1' and 22_1' are connected may be a power supply net.

In step S62_4 , an operation of generating a merged pattern by extending the first and second patterns may be performed. For example, as shown in FIG. 9B , the vias 21_1 ′ and 22_1 ′ of FIG. 9A may be merged to form a bar-type via. Then, in step S62_6, an operation of changing the layout information so that the layout of the integrated circuit includes the merged pattern may be performed. That is, arrangement information corresponding to the first pattern and the third pattern may be deleted from the input layout data, and arrangement information of the merged pattern may be added to the input layout data.

11A and 11B are diagrams illustrating a process in which a method for designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure is applied to the layout of the integrated circuit. Specifically, FIGS. 11A and 11B show a method of coloring a plurality of patterns in input layout data including layout information but not coloring information. Hereinafter, a method of designing a layout of an integrated circuit is described as coloring a plurality of vias with reference to FIGS. 11A and 11B , but it will be understood as coloring patterns for forming a plurality of vias.

Before coloring a plurality of vias, an operation of merging vias connected to the same net may be performed according to an exemplary embodiment of the present disclosure. Accordingly, the number of vias may be reduced, and an operation of coloring the vias may be easily performed.

Referring to FIG. 11A , the layout 30 of the integrated circuit may include a plurality of standard cells 31 to 34 , and a plurality of vias 31_1 and 31_2 connected to pins of the plurality of standard cells 31 to 34 . , 32_1, 32_2, 33_1, 33_2, 34_1, 34_2). The vias 31_1 and 32_1 may be connected to the conductive line 39 , and thus may be connected to the same net. For example, when the conductive line 39 is a power line for supplying a power supply voltage to the standard cells 31 to 34, each of the standard cells 31 to 34 may be connected to the conductive line 39 through at least one via. have.

Referring to FIG. 11B , the merged vias 30_12 may be generated by merging the vias 31_1 and 32_1 of FIG. 11A connected to the same net. As described above, the merged vias 30_12 may be bar-type vias and may be connected to the conductors 39 . Accordingly, in the layout 30 of the integrated circuit, the number of vias subjected to the coloring operation may be reduced by one, and the operation of curling the vias may be easily performed.

12 is a flowchart illustrating a method of designing a layout of an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the embodiment shown in FIG. 12 is a flowchart illustrating a method of generating coloring information.

In step S120, an operation of receiving input layout data may be performed. In the embodiment shown in FIG. 12 , the input layout data may include arrangement information of a plurality of patterns, but may not include coloring information of the plurality of patterns.

In operation S140 , an operation of generating coloring information in which each of the plurality of patterns corresponds to one mask among the plurality of masks may be performed. Step S140 will be described in detail with reference to FIG. 14 . Then, in step S180, output layout data including the coloring information generated by step S140 may be generated.

13 is a flowchart illustrating an example of step S140 of FIG. 12 according to an exemplary embodiment of the present disclosure. As described above with reference to FIGS. 11A and 11B , before coloring a plurality of patterns, an operation of merging patterns connected to the same net may be performed.

Referring to FIG. 13 , in operation S142 , an operation of changing the arrangement information so that at least two patterns connected to the same net among the plurality of patterns are merged may be performed. For example, based on the arrangement information included in the input layout data, it is possible to extract pattern pairs spaced apart from each other by a predetermined distance or less from among a plurality of patterns formed in one layer, and among the extracted pattern pairs, to the same net. A pattern pair including connected patterns may be selected, and patterns of the selected pattern pair may be merged. The arrangement information of the input layout data may be changed so that the layout of the integrated circuit includes the merged pattern. As a result, the number of the plurality of patterns formed in one layer in the layout of the integrated circuit may be reduced.

In operation S144 , an operation of generating coloring information in which each of the plurality of patterns and the merged pattern corresponds to one of the plurality of masks may be performed. Since the coloring operation is performed on the reduced number of patterns in step S142, the time taken to generate the coloring information can be shortened.

14 is a block diagram illustrating a computer-readable storage medium 200 according to an exemplary embodiment of the present disclosure. Computer-readable storage medium 200 may include any storage medium that can be read by a computer while being used to provide instructions and/or data to a computer. For example, the computer-readable storage medium 200 may include a magnetic or optical medium such as a disk, tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, RAM, and the like. , ROM, volatile or non-volatile memory such as flash memory, non-volatile memory accessible through a USB interface, microelectromechanical systems (MEMS), and the like. The computer-readable storage medium may be inserted into, integrated into, or coupled to the computer through a communication medium such as a network and/or a wireless link. Referring to FIG. 14 , the computer-readable storage medium 200 may include a location and wiring program 220 , a coloring program 240 , a design rule 260 , and a data structure 280 .

The location and wiring program 220 may include a plurality of instructions for arranging standard cells included in the layout of the integrated circuit and connecting them through conductive wires. Also, the location and wiring program 220 may include a plurality of instructions for performing a method of designing a layout of an integrated circuit according to one of exemplary embodiments of the present disclosure.

The coloring program 240 may include a plurality of instructions for performing an operation of matching each of the plurality of patterns formed on one layer to one of the plurality of masks, that is, an operation of coloring the plurality of patterns. Also, the location and wiring program 220 may include a plurality of instructions for performing a method of designing a layout of an integrated circuit according to one of exemplary embodiments of the present disclosure.

According to an exemplary embodiment of the present disclosure, the computer-readable storage medium 200 is a location and wiring program ( 220) and a coloring program 240 may be stored. In the example of FIG. 14 , the location and wiring program 220 and the coloring program 240 are shown separately, but may be stored in the computer-readable storage medium 200 as one program.

The design rule 260 may include a plurality of values that the layout of the integrated circuit must comply with based on a semiconductor manufacturing process for manufacturing the integrated circuit. The location and wiring program 220 and the coloring program 240 may design the layout of the integrated circuit with reference to the numerical values included in the design rule 260 .

The data structure 280 may include a storage space for managing data generated while the location and wiring program 220 and the coloring program 240 are executed.

15 is a block diagram illustrating a computer system 300 according to an exemplary embodiment of the present disclosure. As shown in FIG. 15 , the computer system 300 may include a processor 320 , a memory 340 , and various peripheral devices 360 . The processor 320 may be connected to the memory 340 and peripheral devices 360 .

The processor 320 may be configured to execute instructions for performing at least one of the methods according to the exemplary embodiments of the present disclosure described above. For example, the processor 320 performs an operation of matching each of a plurality of patterns formed on one layer included in the layout of the integrated circuit to one of a plurality of masks, that is, an operation of coloring the plurality of patterns. A plurality of commands can be executed. That is, steps S20 , S40 , S60 and S80 of FIG. 1 and steps S120 , S140 , and S160 of FIG. 12 may be performed by the processor 320 .

In accordance with an exemplary embodiment of the present disclosure, the processor 320 may include any instruction set (eg, IA-32 (Intel Architecture-32), 64-bit extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM , IA-64, etc.). Further, computer system 300 may include one or more processors.

The processor 320 may be coupled to the memory 340 and peripheral devices 360 in any manner. For example, the processor 320 may be coupled to the memory 340 and/or peripheral devices 360 through various interconnections. In addition, one or more bridge chips may be used to connect these components while creating multiple connections between the processor 320 , memory 340 and peripherals 360 .

Memory 340 may include any type of memory system. For example, the memory 340 may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Mobile DRAM, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power DDR (LPDDR) SDRAM, GDDR (Graphic DDR) volatile memory such as SDRAM, Rambus Dynamic Random Access Memory (RDRAM) and/or non-volatile memory such as a Electrically Erasable Programmable Read-Only Memory, flash memory; Such as Phase Change Random Access Memory (PRAM), Resistance Random Access Memory (RRAM), Nano Floating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), etc. It may include a non-volatile memory (non-volatile memory) and the like. A memory controller may be included to interface to the memory 340 , and/or the processor 320 may include the memory controller. The memory 340 may store data processed by the processor 320 and instructions for performing at least a part of the method for designing a layout of an integrated circuit described above.

The memory 340 may store a layout of the integrated circuit, and may store a location and wiring program 220 , a coloring program 240 , a design rule 260 , and a data structure 280 . The processor 320 uses the location and wiring program 220 , the coloring program 240 , the design rule 260 , and the data structure 280 stored in the memory 340 , and uses the one included in the layout of the integrated circuit. A plurality of commands may be performed to correspond to each of the plurality of patterns formed on the layer to one of the plurality of masks, that is, to perform an operation of coloring the plurality of patterns. Accordingly, the computer system 300 may automatically design the layout of the integrated circuit by the processor 320 .

Peripheral devices 360 include any type of hardware device that may be included or coupled to computer system 300 , such as a storage device or input/output device (video hardware, audio hardware, user interface devices, networking hardware, etc.), etc. may include.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are only used for the purpose of explaining the technical idea of the present invention and not used to limit the meaning or the scope of the present invention described in the claims . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.

Claims (10)

A computer implemented method for designing a layout of an integrated circuit including a plurality of patterns formed in one layer, the method comprising:
receiving input layout data including arrangement information of the plurality of patterns and coloring information in which each of the plurality of patterns corresponds to one of the plurality of masks;
checking a design rule of the layer with respect to the plurality of patterns;
With respect to the first and second patterns that violate the design rule among the plurality of patterns, by extending at least one of the first pattern and a third pattern connected to the same net as the first pattern, the first pattern and the changing the arrangement information so that a third pattern is merged; and
and updating the coloring information so that a merged pattern from the first and third patterns corresponds to a mask corresponding to the third pattern. According to claim 1,
The first and second patterns correspond to the first mask,
The third pattern corresponds to a second mask different from the first mask,
The updating of the coloring information comprises updating the coloring information so that the merged pattern corresponds to the second mask. 3. The method of claim 2,
The step of checking the design rule comprises:
matching the first or second pattern to a mask different from the first mask among a plurality of masks; and
and checking the design rule against patterns adjacent to the first and second patterns, the first and second patterns. According to claim 1,
wherein the integrated circuit comprises a plurality of standard cells comprising at least one pin;
In the arrangement information of the input layout data, the first to third patterns are respectively arranged on pins included in different standard cells among the plurality of standard cells. . According to claim 1,
Each of the plurality of patterns is a pattern formed on the layer to form a via,
and the merged pattern is a pattern formed in the layer to form bar-type vias. According to claim 1,
Changing the arrangement information comprises:
selecting the first and third patterns commonly connected to a power net of the integrated circuit and corresponding to the same mask;
generating the merged pattern by extending each of the first and third patterns in the layer; and
and changing the layout information so that the layout includes a merged pattern. According to claim 1,
The design rule is
a first rule defining an interval between two patterns corresponding to the same mask among the plurality of patterns; and
a second rule defining an interval between two patterns corresponding to different masks of the plurality of patterns;
The computer implemented method for layout design of an integrated circuit, characterized in that the interval defined by the first rule is larger than the interval defined by the second rule. According to claim 1,
The computer implemented method for designing a layout of an integrated circuit further comprising generating output layout data including the changed layout information and the updated coloring information. A computer implemented method for designing a layout of an integrated circuit including a plurality of patterns formed in one layer, the method comprising:
receiving input layout data including arrangement information of the plurality of patterns;
generating coloring information in which each of the plurality of patterns corresponds to one of the plurality of masks; and
generating output layout data including the coloring information;
The generating of the coloring information may include: changing the arrangement information so that the at least two patterns are merged by extending at least one of the at least two patterns connected to the same net among the plurality of patterns; and
and generating the coloring information such that the plurality of patterns and a pattern merged from the at least two patterns correspond to one of the plurality of masks. How to implement a computer. 10. The method of claim 9,
Changing the arrangement information comprises:
selecting first and second patterns commonly connected to a power net of the integrated circuit;
generating a merged pattern by extending each of the first and second patterns in the layer; and
and changing the layout information so that the layout includes a merged pattern.

Images