TWM575585U - Automatic video detecting phase synchronization system - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N5/00—Details of television systems
- H04N5/04—Synchronising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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Abstract
本新型揭露一種視訊自動偵測相位同步系統，包括：一鎖相廻路單元，係接收一來源時脈訊號，並根據該來源時脈訊號產生一時脈讀取訊號；以及一調節訊號單元，係接收該時脈讀取訊號、一垂直同步訊號以及一資料啟能訊號，並根據該垂直同步訊號及該資料啟能訊號來同步每一張畫面之頻率，進而校正一輸出頻率之誤差。The present invention discloses a video auto-detection phase synchronization system, comprising: a phase-locked loop unit that receives a source clock signal and generates a clock read signal according to the source clock signal; and an adjustment signal unit. Receiving the clock read signal, a vertical sync signal, and a data enable signal, and synchronizing the frequency of each picture according to the vertical sync signal and the data enable signal, thereby correcting an error of an output frequency.
Description
本新型有關於一種視訊自動偵測相位同步系統，特別有關於一種校正輸出頻率誤差，進而同步每一張畫面之視訊自動偵測相位同步系統。The present invention relates to a video automatic detection phase synchronization system, and particularly relates to a video automatic detection phase synchronization system that corrects an output frequency error and synchronizes each picture.
傳統上，在HDMI傳輸資料時，會有輸入/輸出解析度不同的情況發生，因此需要做畫面的放大縮小，而為了滿足相同框率(Frame Rate)，故需在頻率上作調整。在頻率調整的過程中，可能會因為一些特殊的規格造成無法達到最精確的頻率，在長時間的累積誤差下就會造成畫面的錯誤，為此，必須利用自動偵測相位來同步電路，以避免此情況發生。在頻率轉換上通常都是使用鎖相迴路電路(PLL)來產生需要的輸出頻率，而在HDMI中須要求較高的精準度，否則就會造成框率(frame rate)不同而畫面有錯誤。Traditionally, when HDMI transmits data, there are cases where the input/output resolution is different. Therefore, it is necessary to enlarge and reduce the screen, and in order to satisfy the same frame rate, it is necessary to adjust the frequency. In the process of frequency adjustment, the most accurate frequency may not be reached due to some special specifications, and the screen error may be caused by the accumulated error for a long time. Therefore, the phase must be used to synchronize the circuit with the automatic detection phase. Avoid this happening. In frequency conversion, a phase-locked loop circuit (PLL) is usually used to generate the required output frequency, and higher precision is required in HDMI, otherwise the frame rate is different and the picture is wrong.
因此，如何有效地達成視訊自動偵測相位同步，便是各家廠商所欲研究的一項課題。Therefore, how to effectively achieve video auto-detection phase synchronization is a topic that various manufacturers want to study.
有鑑於此，本新型提供一種視訊自動偵測相位同步系統，藉以偵測相位，進而有效地調整水平同步訊號與垂直同步訊號，以校正輸出頻率誤差，進而使每一張畫面達到同步。In view of this, the present invention provides a video automatic detection phase synchronization system for detecting the phase, thereby effectively adjusting the horizontal synchronization signal and the vertical synchronization signal to correct the output frequency error, thereby synchronizing each picture.
本新型是藉由偵測相位的方式來同步每個畫面，故對於鎖相迴路電路產生出的頻率容差較高。The novel synchronizes each picture by detecting the phase, so the frequency tolerance generated by the phase-locked loop circuit is high.
本新型提供一種視訊自動偵測相位同步系統，包括：一鎖相廻路單元，係接收一來源時脈訊號，並根據該來源時脈訊號產生一時脈讀取訊號；以及一調節訊號單元，係接收該時脈讀取訊號、一垂直同步訊號以及一資料啟能訊號，並根據該垂直同步訊號及該資料啟能訊號來同步每一張畫面之頻率，進而校正一輸出頻率之誤差。The present invention provides a video auto-detection phase synchronization system, comprising: a phase-locked loop unit that receives a source clock signal and generates a clock read signal according to the source clock signal; and an adjustment signal unit. Receiving the clock read signal, a vertical sync signal, and a data enable signal, and synchronizing the frequency of each picture according to the vertical sync signal and the data enable signal, thereby correcting an error of an output frequency.
在一實施例中，該調節訊號單元更包括：一偵測相位單元，係接收該垂直同步訊號和該資料啟能訊號，並根據該垂直同步訊號與該資料啟能訊號來同步該每一畫面之起始點，以校正該每一張畫面的時間差，進而來同步該每一張畫面之頻率；一脈衝產生單元，係接收一重設訊號和該時脈讀取訊號，並根據該重設訊號及該時脈讀取訊號，進而校正該輸出頻率之誤差，並輸出一新水平同步訊號，一新垂直同步訊號以及一新資料啟能訊號；以及一緩衝單元，係接收該新水平同步訊號、該新垂直同步訊號、該新資料啟能訊號、該時脈寫入訊號、該時脈讀取訊號、一資料訊號，並根據該新垂直同步訊號、該新水平同步訊號及該新資料啟能訊號，產生一新資料訊號，其中，根據該新資料啟能訊號，得到一輸出格式，並將該輸出格式應用於該輸出頻率及該新資料訊號。In an embodiment, the adjustment signal unit further includes: a detection phase unit that receives the vertical synchronization signal and the data enable signal, and synchronizes each picture according to the vertical synchronization signal and the data enable signal. a starting point for correcting the time difference of each picture, thereby synchronizing the frequency of each picture; a pulse generating unit receiving a reset signal and the clock reading signal, and according to the reset signal And the clock reads the signal, thereby correcting the error of the output frequency, and outputting a new horizontal sync signal, a new vertical sync signal and a new data enable signal; and a buffer unit receiving the new horizontal sync signal, The new vertical sync signal, the new data enable signal, the clock write signal, the clock read signal, a data signal, and the new vertical sync signal, the new horizontal sync signal and the new data enable The signal generates a new data signal, wherein an output format is obtained according to the new data enable signal, and the output format is applied to the output frequency and the new data .
在一實施例中，該緩衝單元輸出該新水平同步訊號、該新垂直同步訊號、該新資料啟能訊號以及應用該輸出格式之該新資料訊號與該輸出頻率。In an embodiment, the buffer unit outputs the new horizontal sync signal, the new vertical sync signal, the new data enable signal, and the new data signal and the output frequency to which the output format is applied.
該水平同步訊號中每二個脈衝之間夾帶著一有效資料及一空白資料，且該水平同步訊號決定每一條線的起始位置，且該垂直同步訊號中每二個脈衝之間夾帶著一有效線及一空白線，且該垂直同步訊號決定該每一張畫面的起始位置，且該資料啟能訊號決定一第 一條有效線的位置。Each of the two horizontal pulses of the horizontal synchronization signal carries a valid data and a blank data, and the horizontal synchronization signal determines a starting position of each line, and each of the two vertical pulses of the vertical synchronization signal carries a An effective line and a blank line, and the vertical sync signal determines a starting position of each of the pictures, and the data enable signal determines a position of the first active line.
在一實施例中，該偵測相位電路應用該資料啟能訊號的脈衝來啟動該重設訊號，其中，該偵測相位電路在該資料啟能訊號的第一個的脈衝上升緣之時間，將會啟動該重設訊號，且當該資料啟能訊號的第二個的脈衝上升緣之時間，根據該鎖相迴路電路所輸出之該時脈讀取訊號，來調整該水平同步訊號之空白資料及該垂直同步訊號之空白線的時間，進而校正該輸出頻率的誤差，且該偵測相位電路在調整該水平同步訊號之該空白資料及該垂直同步訊號之該空白線的該時間之前，並先確認該資料啟能訊號的該第一個脈衝之高位準之前有該垂直同步訊號的脈衝，才可確保該資料訊號為第一條線。In one embodiment, the detecting phase circuit applies the pulse of the data enable signal to activate the reset signal, wherein the detecting phase circuit is at the rising edge of the first pulse of the data enable signal. The reset signal will be activated, and when the second pulse rising edge of the data enable signal is received, the horizontal sync signal blank is adjusted according to the clock read signal output by the phase locked loop circuit. The time of the data and the blank line of the vertical sync signal, thereby correcting the error of the output frequency, and the detecting phase circuit is before adjusting the blank data of the horizontal sync signal and the blank line of the vertical sync signal. And confirming that the vertical signal of the first pulse of the data enable signal has a pulse of the vertical synchronization signal before ensuring that the data signal is the first line.
以上之關於本新型內容之說明及以下之實施方式之說明用以示範與解釋本新型之精神與原理，並且提供本新型之專利申請範圍更進一步之解釋。The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the spirit and principles of the present invention and to provide a further explanation of the scope of the invention.
以下在實施方式中詳細敘述本新型之詳細特徵以及優點，其內容足以使任何熟習相關技藝者了解本新型之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本新型相關之目的及優點。以下之實施例進一步詳細說明本新型之觀點，但非以任何觀點限制本新型之範疇。The detailed features and advantages of the present invention are described in detail in the following detailed description of the embodiments of the present invention. Any related art and related art can easily understand the related purposes and advantages of the present invention. The following examples further illustrate the aspects of the present invention in detail, but do not limit the scope of the present invention in any way.
以下所列舉的各實施例中，將以相同的標號代表相同或相似的元件或構件。In the various embodiments listed below, the same or similar elements or members will be denoted by the same reference numerals.
圖1為本新型之實施例所揭露之視訊自動偵測相位同步系統示意圖。上述之視訊自動偵測相位同步系統包括：一鎖相廻路單元11以及一調節訊號單元12。鎖相廻路單元11，係接收一來源時脈訊號，並根據該來源時脈訊號產生一時脈讀取訊號。調節訊號單元12，耦接該鎖相廻路單元11，係接收該時脈讀取訊號、一垂直同步訊號以及一資料啟能訊號，並根據該垂直同步訊號及該資料啟能訊號來同步每一張畫面之頻率，進而校正一輸出頻率之誤差。FIG. 1 is a schematic diagram of a video automatic detection phase synchronization system according to an embodiment of the present invention. The above video automatic detection phase synchronization system comprises: a phase locked loop unit 11 and an adjustment signal unit 12. The phase-locked loop unit 11 receives a source clock signal and generates a clock read signal according to the source clock signal. The adjustment signal unit 12, coupled to the phase-locked loop unit 11, receives the clock read signal, a vertical sync signal, and a data enable signal, and synchronizes each of the vertical sync signals and the data enable signal according to the vertical sync signal and the data enable signal. The frequency of a picture, which in turn corrects the error of an output frequency.
上述之調節訊號單元12更包括：一偵測相位單元121，係接收該垂直同步訊號和該資料啟能訊號，並根據該垂直同步訊號與該資料啟能訊號來同步每一畫面之起始點，以校正該每一張畫面的時間差，進而來同步該每一張畫面之頻率；一脈衝產生單元122，係接收一重設訊號和該時脈讀取訊號，並根據該重設訊號及該時脈讀取訊號，進而校正該輸出頻率之誤差，並輸出一新水平同步訊號，一新垂直同步訊號以及一新資料啟能訊號；以及一緩衝單元123，係接收該新水平同步訊號、該新垂直同步訊號、該新資料啟能訊號、該時脈寫入訊號、該時脈讀取訊號、一資料訊號，並根據該新垂直同步訊號、該新水平同步訊號及該新資料啟能訊號，調節該資料訊號，以產生一新資料訊號，其中，根據該新資料啟能訊號，得到一輸出格式，並將該輸出格式應用於該輸出頻率及該新資料訊號。The adjustment signal unit 12 further includes: a detection phase unit 121 for receiving the vertical synchronization signal and the data enable signal, and synchronizing the starting point of each picture according to the vertical synchronization signal and the data enable signal. To correct the time difference of each picture, and then to synchronize the frequency of each picture; a pulse generating unit 122 receives a reset signal and the clock read signal, and according to the reset signal and the time The pulse reads the signal, and further corrects the error of the output frequency, and outputs a new horizontal sync signal, a new vertical sync signal and a new data enable signal; and a buffer unit 123 receives the new horizontal sync signal, the new a vertical sync signal, the new data enable signal, the clock write signal, the clock read signal, a data signal, and the enable signal according to the new vertical sync signal, the new horizontal sync signal and the new data. Adjusting the data signal to generate a new data signal, wherein an output format is obtained according to the new data enable signal, and the output format is applied to the output frequency And the new data signal.
此外，該緩衝單元123可直接輸出該新水平同步訊號、該新垂直同步訊號、該新資料啟能訊號以及應用該輸出格式之該新資料訊號與該輸出頻率。其中，該偵測相位單元121可根據該垂直同步訊號和該資料啟能訊號產生該重設訊號。In addition, the buffer unit 123 can directly output the new horizontal synchronization signal, the new vertical synchronization signal, the new data activation signal, and the new data signal and the output frequency to which the output format is applied. The detecting phase unit 121 can generate the reset signal according to the vertical sync signal and the data enable signal.
另外，在本實施例，該水平同步訊號中每二個脈衝之間夾帶著一有效資料及一空白資料，且該水平同步訊號決定每一條線的起始位置。該垂直同步訊號中每二個脈衝之間夾帶著一有效線及一空白線，且該垂直同步訊號決定該每一張畫面的起始位置。該資料啟能訊號決定一第一條有效線的位置。本新型之偵測相位單元121應用該資料啟能訊號脈衝來啟動該重設訊號，其中，該偵測相位電路121在該資料啟能訊號的第一個的脈衝上升緣之時間，將會啟動該重設訊號，且當該資料啟能訊號的第二個的脈衝上升緣之時間，根據該鎖相迴路單元11所輸出之該時脈讀取訊號，來調整該水平同步訊號之空白資料及該垂直同步訊號之空白線的時間，進而校正該輸出頻率的誤差。該偵測相位單元121在調整該水平同步訊號之該空白資料及該垂直同步訊號之該空白線的該時間之前，並先確認該資料啟能訊號的該第一個脈衝之高位準之前有該垂直同步訊號的脈衝，才可確保該資料訊號為第一條線。In addition, in this embodiment, a valid data and a blank data are sandwiched between every two pulses in the horizontal synchronization signal, and the horizontal synchronization signal determines the starting position of each line. An active line and a blank line are sandwiched between every two pulses in the vertical sync signal, and the vertical sync signal determines the starting position of each picture. The data enable signal determines the location of a first valid line. The detection phase unit 121 of the present invention applies the data enable signal pulse to activate the reset signal, wherein the detection phase circuit 121 will start at the time of the first rising edge of the data enable signal. The reset signal, and when the second pulse rising edge of the data enable signal, the blank data of the horizontal synchronization signal is adjusted according to the clock reading signal output by the phase locked loop unit 11 The time of the blank line of the vertical sync signal, thereby correcting the error of the output frequency. The detecting phase unit 121 determines the high level of the first pulse of the data enable signal before adjusting the blank data of the horizontal synchronization signal and the blank line of the vertical synchronization signal. The pulse of the vertical sync signal ensures that the data signal is the first line.
於本實施例，在經由HDMI畫面傳輸的過程中，會因為使用者的喜好或輸出螢幕的不同而作解析度(resolution)的變更，當解析度有變更，則需在電路中做縮放(scaler)後在將資料輸出到顯示的螢幕上。In this embodiment, in the process of transmitting via the HDMI screen, the resolution is changed due to the user's preference or the output screen. When the resolution is changed, the scaling is performed in the circuit (scaler) After the data is output to the displayed screen.
在解析度變更的過程中，因為需要滿足相同的框率，故像素頻率也會隨之變化，如下公式所示： ； In the process of resolution change, because the same frame rate needs to be met, the pixel frequency will also change, as shown in the following formula: ;
因為有限的有效位元數，故當輸入/輸出解析度在除不進的情況下會有四捨五入的運算，因而無法呈現出最精準的頻率。Because of the limited number of valid bits, when the input/output resolution is rounded off, there is a rounding operation, so the most accurate frequency cannot be presented.
在每個畫面的像素轉換過程中若有產生誤差，長時間累積下會導致畫面的錯誤，所以，本新型所設計電路可在每張畫面的起始點會經過偵測相位單元121來同步每張畫面以解決時間誤差的問題。If there is an error in the pixel conversion process of each picture, the accumulation of the picture will cause an error of the picture for a long time. Therefore, the circuit designed by the present invention can be synchronized by the detection phase unit 121 at the starting point of each picture. The picture is taken to solve the problem of time error.
在訊號縮放轉換的過程中，由HDMI來源來的輸入頻率(HDMI CLK)和訊號縮放器輸出頻率(CKLout)會不同，本新型是藉由鎖相廻路電路(Phase-Locked Loop，PLL)來產生相對應的輸出頻率。In the process of signal scaling conversion, the input frequency (HDMI CLK) and the signal scaler output frequency (CKLout) from the HDMI source will be different. The present invention is implemented by a phase-locked loop (PLL). Produce the corresponding output frequency.
例如，以720*480p(858*525) ＞＞ 640*480P(800*525)為例，HDMI source頻率為27.027MHz(框率為60Hz)，輸出頻率應為((800*525)/(858*525))*27.027MHz，800/858=0.932400無限偱環，故乘上27.027MHz所獲得25.2M亦是經過四捨五入後的值，如此一來就會造成頻率誤差。For example, taking 720*480p (858*525) >> 640*480P (800*525) as an example, the HDMI source frequency is 27.027MHz (frame rate is 60Hz), and the output frequency should be ((800*525)/(858 *525)) *27.027MHz, 800/858=0.932400 infinite loop, so the 25.2M obtained by multiplying 27.027MHz is also the value after rounding, which will cause frequency error.
本新型之調節訊號單元12是藉由不同的取樣率(sample rate)將原視訊資料作像素轉換，將增減完後的資料先存入緩衝單元123中，再藉由偵測相位單元121來決定何時輸出資料。本新型之像素轉換單元(未繪示)，以720*480p(858*525) ＞＞ 640*480P(800*525)為例，此畫面為解析度降低轉換，從720個有效像素變成640個有效像素，本實施例之像素轉換器123的轉換方式為每九個像素會少一個像素，以此類推，線的轉換亦是如此。當解析度是提高的轉換，則是找出最小的整數比然後做重複像素或線的方式轉換。The adjustment signal unit 12 of the present invention converts the original video data into pixels by using different sampling rates, and stores the increased and decreased data in the buffer unit 123 first, and then detects the phase unit 121. Decide when to export the data. The pixel conversion unit (not shown) of the present invention takes 720*480p (858*525) >> 640*480P (800*525) as an example. This picture is a resolution reduction conversion, from 720 effective pixels to 640. The effective pixel, the conversion mode of the pixel converter 123 of the present embodiment is one pixel less every nine pixels, and so on, and the conversion of the line is also the same. When the resolution is an improved conversion, it is to find the smallest integer ratio and then do the conversion of the repeated pixels or lines.
圖2係顯示本新型所應用的訊號波形圖。如圖2所示，本新型在介紹偵測相位的方式前，需要先介紹一些電路中用到的訊號，如資料啟能訊號、水平同步訊號、垂直同步訊號(水平同步訊號和垂直同步訊號為高脈衝或低脈衝並非固定，隨著不同的解析度會有不同，以下說明皆以高脈衝為例)。Fig. 2 is a diagram showing signal waveforms applied to the present invention. As shown in Figure 2, before introducing the method of detecting the phase, the present invention needs to introduce some signals used in the circuit, such as data enable signal, horizontal sync signal, and vertical sync signal (horizontal sync signal and vertical sync signal are High pulse or low pulse is not fixed. As different resolutions will be different, the following description takes high pulse as an example.
資料啟能訊號：當為高脈衝時，此段時間內傳輸的資料皆為視訊資料，反之為低脈衝時不為視訊資料，如圖2所示，當資料啟能訊號為高脈衝時，為有效視訊時脈，而資料啟能訊號所顯示高脈衝及低脈衝之組合為每條線的總時脈。Data enable signal: When it is high pulse, the data transmitted during this period is video data, otherwise it is not video data when it is low pulse, as shown in Figure 2, when the data enable signal is high pulse, The effective video clock, and the combination of the high pulse and the low pulse displayed by the data enable signal is the total clock of each line.
水平同步訊號，代表每條線的起始位置，每二個脈衝中間夾帶著有效資料(active data)及空白資料(blanking data)，如圖2所示，二個脈衝之間的低脈衝時間為空白資料，高脈衝時間為有效資料。The horizontal sync signal represents the starting position of each line. Each two pulses are sandwiched between active data and blanking data. As shown in Figure 2, the low pulse time between the two pulses is Blank data, high pulse time is valid data.
垂直同步訊號，代表每個畫面的起始位置，每二個脈衝中夾帶著有效線(active line)及空白線(blanking line)，如圖2所示，二個脈衝之間的低脈衝時間為空白線，高脈衝時間為有效線。The vertical sync signal represents the starting position of each picture. Each two pulses carry an active line and a blanking line. As shown in Figure 2, the low pulse time between the two pulses is Blank line, high pulse time is the effective line.
若有解析度為1920*1080為例，代表有效視訊的時脈等於1920，亦代表在資料啟動為高脈衝時間內總共取樣了1920次會有1920筆資料。有效線等於1080代表每張畫面由1080條有效線組成。If the resolution is 1920*1080, the clock representing the effective video is equal to 1920, which means that a total of 1920 samples will be collected during the high pulse time of the data. A valid line equal to 1080 means that each picture consists of 1080 active lines.
由於每張畫面的起始位置是由垂直同步訊號決定且第一條有效線的位置由資料啟能訊號決定，故本實施例在偵測相位時，會在第一個輸入的資料啟能訊號上升緣時重設，並在第二個資料啟能訊號上升緣時才設定，此時才開始視訊資料輸出，並且要確認第一個資料啟能訊號的高脈衝之前有垂直同步訊號的脈衝才能確保此資料啟能為第一條線，利用變更空白的時間來解決因為頻率轉換造成誤差所帶來的錯誤。Since the starting position of each picture is determined by the vertical sync signal and the position of the first active line is determined by the data enable signal, in this embodiment, when the phase is detected, the first input data enable signal is generated. Reset when rising edge, and set when the second data enable signal rises. At this time, the video data output is started, and it is necessary to confirm the pulse of the vertical sync signal before the high pulse of the first data enable signal. Make sure that this data is enabled as the first line, and use the time to change the blank to solve the error caused by the error caused by the frequency conversion.
圖3為本新型之實施例所揭露之視訊自動偵測相位同步方法之流程圖。如圖3所示，首先，應用一鎖相廻路單元11接收一來源時脈訊號，並根據該來源時脈訊號產生一時脈讀取訊號(s201)，接著，應用一調節訊號單元12接收該時脈讀取訊號、一垂直同步訊號以及一資料啟能訊號，並根據該垂直同步訊號及該資料啟能訊號來同步每一張畫面之頻率，進而校正一輸出頻率之誤差(s202)。FIG. 3 is a flowchart of a method for automatically detecting video phase synchronization according to an embodiment of the present invention. As shown in FIG. 3, first, a phase-locked loop unit 11 is used to receive a source clock signal, and a clock read signal is generated according to the source clock signal (s201). Then, an adjustment signal unit 12 is applied to receive the signal. The clock reading signal, a vertical synchronizing signal and a data enabling signal, and synchronizing the frequency of each picture according to the vertical synchronizing signal and the data enabling signal, thereby correcting an error of an output frequency (s202).
於本實施例，應用該調節訊號單元之步驟更包括：應用一偵測相位單元121接收該垂直同步訊號和該資料啟能訊號，並根據該垂直同步訊號與該資料啟能訊號來同步該每一畫面之起始點，以校正該每一張畫面的時間差，進而來同步該每一張畫面之頻率；應用一脈衝產生單元122接收一重設訊號和該時脈讀取訊號，並根據該重設訊號及該時脈讀取訊號，進而校正該輸出頻率之誤差，並輸出一新水平同步訊號，一新垂直同步訊號以及一新資料啟能訊號；以及應用一緩衝單元123，係接收該新水平同步訊號、該新垂直同步訊號、該新資料啟能訊號、該時脈寫入訊號、該時脈讀取訊號、一資料訊號，並根據該新垂直同步訊號、該新水平同步訊號及該新資料啟能訊號，調節該資料訊號，產生一新資料訊號，且根據該新資料啟能訊號，得到一輸出格式，並將該輸出格式應用於該輸出頻率及該新資料訊號。其中，該緩衝單元123可直接輸出該新水平同步訊號、該新垂直同步訊號、該新資料啟能訊號以及應用該輸出格式之該輸出頻率及該新資料訊號。In this embodiment, the step of applying the adjustment signal unit further includes: applying a detection phase unit 121 to receive the vertical synchronization signal and the data activation signal, and synchronizing the vertical synchronization signal with the data activation signal according to the vertical synchronization signal a starting point of a picture to correct the time difference of each picture, thereby synchronizing the frequency of each picture; applying a pulse generating unit 122 to receive a reset signal and the clock reading signal, and according to the weight Setting a signal and the clock to read the signal, thereby correcting the error of the output frequency, and outputting a new horizontal sync signal, a new vertical sync signal and a new data enable signal; and applying a buffer unit 123 to receive the new signal a horizontal sync signal, the new vertical sync signal, the new data enable signal, the clock write signal, the clock read signal, a data signal, and based on the new vertical sync signal, the new horizontal sync signal, and the The new data enable signal, adjust the data signal, generate a new data signal, and generate an output format based on the new data enable signal, and output the output grid Applied to the output frequency and the new data signal. The buffer unit 123 can directly output the new horizontal synchronization signal, the new vertical synchronization signal, the new data activation signal, and the output frequency and the new data signal to which the output format is applied.
於本實施例，該水平同步訊號中每二個脈衝之間夾帶著一有效資料及一空白資料，且該水平同步訊號決定每一條線的起始位置。該垂直同步訊號中每二個脈衝之間夾帶著一有效線及一空白線，且該垂直同步訊號決定該每一張畫面的起始位置。該資料啟能訊號決定一第一條有效線的位置。該偵測相位單元121應用該資料啟能訊號的脈衝來啟動該重設訊號，其中，該偵測相位電路121在該資料啟能訊號的的第一個的脈衝上升緣之時間，將會啟動該重設訊號，且當該資料啟能訊號的第二個的脈衝上升緣之時間，根據該鎖相迴路單元11所輸出之該時脈讀取訊號，來調整該水平同步訊號之空白資料及該垂直同步訊號之空白線的時間，進而校正該輸出頻率的誤差。該偵測相位單元121在調整該水平同步訊號之該空白資料及該垂直同步訊號之該空白線的該時間之前，並先確認該資料啟能訊號的該第一個脈衝之高位準之前有該垂直同步訊號的脈衝，才可確保該資料訊號為第一條線。In this embodiment, a valid data and a blank data are sandwiched between every two pulses in the horizontal synchronization signal, and the horizontal synchronization signal determines the starting position of each line. An active line and a blank line are sandwiched between every two pulses in the vertical sync signal, and the vertical sync signal determines the starting position of each picture. The data enable signal determines the location of a first valid line. The detecting phase unit 121 applies the pulse of the data enable signal to activate the reset signal, wherein the detecting phase circuit 121 starts at the rising edge of the first pulse of the data enable signal. The reset signal, and when the second pulse rising edge of the data enable signal, the blank data of the horizontal synchronization signal is adjusted according to the clock reading signal output by the phase locked loop unit 11 The time of the blank line of the vertical sync signal, thereby correcting the error of the output frequency. The detecting phase unit 121 determines the high level of the first pulse of the data enable signal before adjusting the blank data of the horizontal synchronization signal and the blank line of the vertical synchronization signal. The pulse of the vertical sync signal ensures that the data signal is the first line.
本新型提供一種視訊自動偵測相位同步系統，藉以偵測相位，進而有效地調整水平同步訊號與垂直同步訊號，以校正輸出頻率誤差，進而使每一張畫面達到同步。本新型更藉由偵測相位的方式來同步每個畫面，故對於鎖相迴路電路產生出的頻率容差較高。The present invention provides a video automatic detection phase synchronization system for detecting a phase, thereby effectively adjusting a horizontal synchronization signal and a vertical synchronization signal to correct an output frequency error, thereby synchronizing each picture. The novel also synchronizes each picture by detecting the phase, so the frequency tolerance generated by the phase-locked loop circuit is high.
雖然本新型以前述之實施例揭露如上，然其並非用以限定本新型。在不脫離本新型之精神和範圍內，所為之更動與潤飾，均屬本新型之專利保護範圍。關於本新型所界定之保護範圍請參考所附之申請專利範圍。Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the present invention. The changes and refinements of the present invention are within the scope of the patent protection of the present invention without departing from the spirit and scope of the present invention. Please refer to the attached patent application for the scope of protection defined by this new model.
11‧‧‧鎖相迴路單元11‧‧‧ phase-locked loop unit
12‧‧‧調節訊號單元 12‧‧‧Adjustment signal unit
121‧‧‧偵測相位單元 121‧‧‧Detecting phase unit
122‧‧‧脈衝產生單元 122‧‧‧pulse generating unit
123‧‧‧緩衝單元 123‧‧‧buffer unit
s201~s202‧‧‧步驟 S201~s202‧‧‧Steps
圖1為本新型之實施例所揭露之視訊自動偵測相位同步系統示意圖。 圖2係顯示本新型所應用的訊號波形圖。 圖3為本新型之實施例所揭露之視訊自動偵測相位同步方法之流程圖。FIG. 1 is a schematic diagram of a video automatic detection phase synchronization system according to an embodiment of the present invention. Fig. 2 is a diagram showing signal waveforms applied to the present invention. FIG. 3 is a flowchart of a method for automatically detecting video phase synchronization according to an embodiment of the present invention.
Claims (8)
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