CN107784992A - Display control apparatus and control method - Google Patents
Display control apparatus and control method Download PDFInfo
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- CN107784992A CN107784992A CN201610719717.0A CN201610719717A CN107784992A CN 107784992 A CN107784992 A CN 107784992A CN 201610719717 A CN201610719717 A CN 201610719717A CN 107784992 A CN107784992 A CN 107784992A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Synchronizing For Television (AREA)
Abstract
A kind of control device, include a detector, a frequency adjusted signal generator, a clock generator and an output timing generator.The detector compares the field reference signal of an input and the field reference signal of an output to determine a lead time signal.The frequency adjusted signal generator is according to the frequency adjusted signal of lead time signal output one.The clock generator is according to the frequency adjusted signal to export a clock.The clock generator produces the field sync signal of an output according to the clock.The clock generator adjusts the frequency of the clock according to the frequency adjusted signal.
Description
Technical field
The present invention is on semiconductor device, more precisely, the present invention is on a kind of display controller.
Background technology
Showing that film represents over the display needs to show the picture of multiple within a certain period of time.Display usually needs to connect
By the source of various films, but different film sources often has different sampling rate and resolution ratio.If input
Sampling rate excessively exports the speed of picture soon, and the buffer capacity of display controller can be inadequate, and picture data can be capped.
If the sampling rate that the sampling rate of output excessively inputs soon, then have picture data and repeatedly exported, cause picture mistake
Or the problem of having some setbacks.Therefore, display needs a display controller to solve different input/output screen speed and divide
Resolution will be smoothly same display plays the problem of.
The content of the invention
The present invention a purpose be to provide a kind of control device of display, the control device can automatically adjust output
The speed of picture, allow output and input picture rate synchronization.
Another object of the present invention is to provide a kind of control device of display, the control device can shorten input picture
Face and output picture synchronize the required time.
According to one embodiment of the invention, there is provided a kind of control device, for the synchronization of control interface.The control device includes
One detector, a frequency adjusted signal generator, a clock generator and an output timing generator.The detector receives one
The field reference signal of input and the field reference signal of an output.The detector compares the field reference signal of the input and this is defeated
The field reference signal gone out is to determine a lead time signal.The lead time signal represents the field reference signal of the input and is somebody's turn to do
Lead time between the field reference signal of output.The frequency adjusted signal generator receives the lead time signal.
The frequency adjusted signal generator is according to the frequency adjusted signal of lead time signal output one.The clock generator
According to the frequency adjusted signal to export a clock.The output timing generator receives the clock.Clock generator foundation should
Clock produces the field sync signal of an output and the line locking signal of an output.The frequency direct ratio of the field sync signal of the output
In the frequency of the field reference signal of the output.The clock generator adjusts the frequency of the clock according to the frequency adjusted signal, makes
Obtain the lead time and be reduced below a predetermined difference value.
According to another embodiment of the present invention, there is provided a kind of synchronous method of control interface.This method comprises the steps of.
First, it is determined that the lead time between the field reference signal of an input and the field reference signal of an output.Come again, judge that this is defeated
The field reference signal and the leading or backwardness of the field reference signal of the output entered.When the field reference signal of the output is relative to this
When the field reference signal of input is in a backward condition, the frequency of a clock is heightened.When the output field reference signal relative to
The field reference signal of the input be in a leading position state when, the frequency of the clock is turned down.Then, check whether the lead time is low
In a predetermined difference value.
According to another embodiment of the present invention, there is provided a kind of control device, for the synchronization of control interface.The control device bag
Containing a detector, a frequency adjusted signal generator, a clock generator and an output timing generator.The detector receives
The field reference signal of one input and the field reference signal of an output.The detector compares the field reference signal of the input and is somebody's turn to do
The field reference signal of output is to determine a lead time signal.The lead time signal represent the input field reference signal and
Lead time between the field reference signal of the output.
Brief description of the drawings
Fig. 1 represents an embodiment of a control device；
Fig. 2 represents a preposition processing mode of the signal of input detector；
Fig. 3 represents another preposition processing mode of the signal of input detector；
Fig. 4 represents the oscillogram of the field reference signal of input and the field reference signal of output；
Fig. 5 represents the preposition oscillogram before and after the processing of the signal of input detector；
Fig. 6 represents the oscillogram after the preposition processing of the signal of input detector；
Fig. 7 represents the oscillogram of the signal of input detector；
Fig. 8 represents the flow chart of the synchronous method of a control interface；And
Fig. 9 represents the more multi-step of the synchronous method of a control interface.
Symbol description
100 control devices
101 detectors
The field reference signal of 102 inputs
The field reference signal of 103 outputs
104 lead time representation signals
105 frequency adjusted signal generators
106 frequency adjusted signals
107 clock generators
108 clocks
109 clock generators
The field sync signal of 110 outputs
The line locking signal of 111 outputs
The data valid signal of 112 outputs
113 leading lagging signals
114 crystal oscillators
201 first frequency eliminators
202 second frequency eliminators
The field sync signal of 203 inputs
301 first pulse signal producers
302 second pulse signal producers
601 first pulses
602 second pulses
S801, S802, S803, S804, S901, S902, S903, S904 step
Embodiment
According to one embodiment of the invention, a kind of control device 100 synchronous for control interface is disclosed.Fig. 1 is refer to, should
Control device 100 includes a detector 101, a frequency adjusted signal generator 105, a clock generator 107 and an output
Clock generator 109.The detector 101 receives the field reference signal 103 that the field reference signal 102 and one of an input exports.
The detector 101 compares the field reference signal 102 of the input and the field reference signal 103 of the output to determine a leading backwardness
Signal 113.The leading lagging signal 113 indicates the field reference signal 103 of the output relative to the field reference signal 102 of the input
The state that is in a leading position or backward state.The frequency adjusted signal generator 105 receives the leading lagging signal 113.The frequency is adjusted
Entire signal generator 105 exports a frequency adjusted signal 106 according to the leading lagging signal 113.The foundation of clock generator 107
The frequency adjusted signal 106 is to export a clock 108.
In certain embodiments, the detector 101 compares the field reference signal 102 of the input and the field reference of the output
Signal 103 is to determine a lead time signal 104.The lead time signal 104 represent the input field reference signal 102 and
Lead time between the field reference signal 103 of the output.The frequency adjusted signal generator 105 also receives lead time letter
Numbers 104 and export the frequency adjusted signal 106 according to the leading lagging signal 113 and the lead time signal 104.
The output timing generator 109 receives the clock 108.The clock generator 109 is defeated according to the clock 108 generation one
The field sync signal 110 (output Vsync) gone out, the line locking signal 111 (outputHsync) of an output and an output
Data valid signal 112 (output DE).In certain embodiments, the field sync signal 110 of the output is used as through feedback and is somebody's turn to do
The field reference signal 103 of output.In certain embodiments, the frequency of the field reference signal 103 of the output is proportional to the output
The frequency of field sync signal 110.The clock generator 107 adjusts the frequency of the clock 108 according to the frequency adjusted signal 106,
So that the lead time is reduced below a predetermined difference value.
Fig. 4 is refer to, in the comparison C1 of first time, the field reference signal 103 of the output lags behind the field ginseng of the input
Signal 102 is examined, backward lead time is d1, therefore the control device 100 heightens clock 108, allows the field of the output with reference to letter
Numbers 103 can speed frequency.In secondary relatively C2, the field reference signal 103 of the output still lags behind the input
Field reference signal 102, but the lead time shortening fallen behind turns into d2, therefore the control device 100 continues to heighten clock 108.
In the comparison C3 of third time, the field reference signal 103 of the output has led over the field reference signal 102 of the input, therefore should
Control device 100 can turn down clock 108.
In comparison each time, the control device 100 all can review time gap whether be less than a predetermined difference value.If
Continuously in the output picture number of a predetermined number, the lead time is below a predetermined difference value, it is possible to is considered synchronous
Complete.Fig. 4 is refer to, in this embodiment, lead time during the 4th comparison C4 is already less than the predetermined difference value, simultaneously
In ensuing 5th C5, lead time is all continuously less than the predetermined difference value in the 6th C6 comparison.If setting continuous 3
Picture just represents less than the predetermined difference value to be synchronously completed, then the representative of this embodiment is in the 4th C4, the 5th C5, the 6th time
C6 has relatively completed picture synchronization afterwards.
In certain embodiments, if the field sync signal (input Vsync) 203 of input and the field sync signal of output
(output Vsync) 110 has close frequency, then the detector 101 can directly compare the field sync signal of the input
(input Vsync) the 203 and field sync signal (output Vsync) 110 of the output.In certain embodiments, if input
Field sync signal (input Vsync) 203 with output field sync signal (output Vsync) 110 frequency difference compared with
Greatly, then the field sync signal (inputVsync) 203 of the input is converted into the field reference signal 102 of the input, this is exported
Field sync signal (outputVsync) 110 be converted into the field reference signal 103 of the output, then the detector 101 compares again
The field reference signal 102 of the input and the field reference signal 103 of the output can allow the speed of picture synchronization to be accelerated.Below can
The speed for how accelerating picture synchronization is described in detail.
In certain embodiments, the detector 101 exports a leading lagging signal 113.The leading lagging signal 113 indicates
The field reference signal 103 of the output is in a leading position state or backward state relative to the field reference signal 102 of the input.The frequency
Adjust signal generator 105 and receive the leading lagging signal 113.In certain embodiments, when the field reference signal 103 of the output
When being in a backward condition relative to the field reference signal 102 of the input, the clock generator 107 adjusts the frequency of the clock 108
It is high.When the output field reference signal 103 relative to the field reference signal 102 of the input be in a leading position state when, the clock production
Raw device 107 turns down the frequency of the clock 108.
In certain embodiments, the frequency adjusted signal generator 105 is a proportional-plus-integral controller
(proportional–integral controller).In certain embodiments, the frequency adjusted signal generator 105 is one
Proportional-integral derivative controller (proportional-integral-derivative controller).In some realities
Apply in example, the field reference signal 103 of the output is derived from the same relative position of each output picture.In certain embodiments, should
Proportional (proportional term) in proportional-plus-integral controller or the proportional-integral derivative controller is
Number, the coefficient of integral term (integral term) and the coefficient of differential term (derivative term) are all to adjust
's.
In certain embodiments, the clock generator 107 adjusts the frequency of the clock 108 according to the frequency adjusted signal 106
Rate so that continuously in the output picture number of a predetermined number, the lead time signal 104 is all less than a predetermined difference value.
In some embodiments, the control device 100 further includes a crystal oscillator 114.The lead time signal 104 is quartz concussion
Concussion number of the device 114 among the field reference signal 103 of the output with the time difference of the field reference signal 102 of the input.
Fig. 2 is refer to, in certain embodiments, the control device 100 further includes one first frequency eliminator 201 and one second
Frequency eliminator 202.First frequency eliminator 201 receives the field sync signal 203 of an input.First frequency eliminator 201 is by the input
The value of field sync signal 203 divided by 1 first is to produce the field reference signal 102 of the input.It is defeated that second frequency eliminator 202 receives this
The field sync signal 110 gone out.Second frequency eliminator 202 is by the second value of field sync signal 110 divided by one of the output to produce this
The field reference signal 103 of output so that the field reference signal 102 of the input and the field reference signal 103 of the output have in fact
Identical frequency in matter.
Fig. 5 is refer to, in this embodiment, due to the field sync signal 203 of input and the field sync signal of output
110 ratio is different, can first distinguish frequency elimination, obtain more similar ratio, then be sent into the detector 101 and be compared.Such as
This, the input of different proportion and output frame frequency can also carry out picture synchronization.For example, the field sync signal 203 of the input
By turning into the field reference signal 102 of the input after frequency elimination, the field sync signal 110 of the output turns into afterwards by frequency elimination should
The field reference signal 103 of output.In this way, the field reference signal 102 of the input and the field reference signal of the output after frequency elimination
103 have close ratio or frequency, are easier to carry out the synchronization of picture.
In certain embodiments, the field reference signal 102 of the input is equal to the field sync signal 203 of the input.The control
Device 100 processed further includes one second frequency eliminator 202.Second frequency eliminator 202 is by the field sync signal 110 divided by 1 of the output
Two-value is to produce the field reference signal 103 of the output so that the field reference signal 102 of the input and the field of the output are with reference to letter
Numbers 103 have substantially the same frequency.
Fig. 3 and Fig. 6 is refer to, in certain embodiments, the control device 100 further includes the generation of one first pulse signal
The pulse signal producer 302 of device 301 and 1 second.First pulse signal producer 301 receives the field synchronization letter of an input
Numbers 203.First pulse generator 301 adds multiple first pulses 601 in the field sync signal 203 of the input and is somebody's turn to do with producing
The field reference signal 102 of input.Second pulse signal producer 302 receives the field sync signal 110 of the output.Second arteries and veins
Rush generator 302 and multiple second pulses 602 are added in the field sync signal 110 of the output to produce the field of the output with reference to letter
Numbers 103.
First pulse generator 301 is counted to produce those the first pulses 601 using an input clock.Second arteries and veins
Generator 302 is rushed using an output clock to count to produce those the second pulses 602.In certain embodiments, during the output
Clock is exactly the clock 108.When the number ratio between those first pulses 601 and those second pulses 602 with inputting originally
Field reference signal 102 and output field reference signal 103 between ratio phase meanwhile, it is capable to reach the effect of picture synchronization
Fruit；It is in other words, identical when the time difference between the time difference between adjacent first pulse 601 and adjacent second pulse 602,
Using the relativeness of the first pulse 601 and the second pulse 602 come the action that synchronizes.It refer to Fig. 7, this mode picture
Synchronously can be than very fast, but input picture and can not be fixed during the output each re-synchronization of the distance between picture, such as may be together
Step is in the part of time 604.Under this situation, the control device 100 needs enough storage area to carry out storage time
The data volume inputted between 603 to the time 604.
For example, when input sampling rate (frame rate) is 60Hz, level points (Htt) are 2200, vertical point
Number (Vtt) is 1125, is counted with input clock, and per second have a Htt*Vtt*frame_rate=148, during 500,000 inputs
The clock cycle.When output sampling rate (frame rate) is 120Hz, level points (Htt) are 4400, and vertical count (Vtt) is
2250, counted with output clock, it is per second to have Htt*Vtt*frame_rate=1,188,000,000 output clock cycle.
So input periodicity per second is 148,500,000 than upper output periodicity per second:1,188,000,000=1:8.So such as
Fruit is 1 than pulse number caused by upper output clock count using pulse number caused by input clock counting:8, it is new with these
Caused pulse come substitute the field sync signal 110 of original output and input field sync signal 203, can accelerate to lock
Speed.
According to another embodiment of the present invention, a kind of synchronous method of control interface is disclosed.It refer to Fig. 8, this method
Comprise the steps of.First, it is determined that the lead time between the field reference signal of an input and the field reference signal of an output
Or leading backward state (S801).Then, according to the leading backward state determine that the frequency of a clock is heightened or turned down
(S802).In certain embodiments, step S802 is further included：When the field reference signal of the output refers to relative to the field of the input
When signal is in a backward condition, the frequency of a clock is heightened.When the field reference signal of the output is joined relative to the field of the input
Examine signal be in a leading position state when, the frequency of the clock is turned down.Then, check continuously in the output picture of a predetermined number
In number, whether the lead time is reduced below a predetermined difference value (S803).
If for the result checked continuously in the output picture number of the predetermined number, it is predetermined that the lead time is less than one
Difference, then representative picture synchronously complete (S804).Persistently docked down after picture synchronization is completed there is still a need for returning to step S801
The picture come does same detecting and adjustment.If the result checked continuously in the output picture number of the predetermined number, is somebody's turn to do
Lead time is not less than a predetermined difference value continuously, then representative picture does not complete synchronously.Next there is still a need for returning to step
S801 persistently does same detecting and adjustment to follow-up picture.
Fig. 9 is refer to, in certain embodiments, this method is further included the field sync signal divided by one first value of an input
To produce the field reference signal (S901) of the input.In certain embodiments, this method is further included the field synchronization letter of the output
Number divided by a second value to produce the field reference signal (S902) of the output.In certain embodiments, this method is further included at this
Multiple first pulses are added in the field sync signal of input to produce the field reference signal (S903) of the input.In some embodiments
In, this method further includes adds multiple second pulses to produce the field reference signal of the output in the field sync signal of the output
(S904).In certain embodiments, this method further include using a crystal oscillator calculate the output field reference signal with
Concussion number among the time difference of the field reference signal of the input.Step in Fig. 8 and Fig. 9 can not have to according to fixed
Sequentially.Between some steps can mutual reversed order, as long as the effect of reaching is identical.
It the foregoing is only many embodiments of the present invention, it is impossible to limit the present invention's with the special way of a certain embodiment
Patent claim, claim of the invention are worked as the described word within invention claim and are defined.
Claims (20)
1. a kind of control device, for the synchronization of control interface, the control device includes：
One detector, receives the field reference signal of an input and the field reference signal of an output, the detector compare the input
Field reference signal and the output field reference signal to determine a leading lagging signal, the leading lagging signal indicates that this is defeated
The field reference signal gone out is in a leading position state or backward state relative to the field reference signal of the input；
One frequency adjusted signal generator, receive the leading lagging signal, the frequency adjusted signal generator according to this it is leading fall
The frequency adjusted signal of signal output one afterwards；
One clock generator, according to the frequency adjusted signal to export a clock；And
One output timing generator, the clock is received, and field sync signal and the output of an output are produced according to the clock
Line locking signal；
Wherein, the frequency of the field reference signal of the output is proportional to the frequency of the field sync signal of the output, the clock generator
The frequency of the clock is adjusted according to the frequency adjusted signal.
2. control device as claimed in claim 1, it is characterised in that the detector more exports a lead time signal, the time difference
The lead time being proportional to away from signal between the field reference signal of the input and the field reference signal of the output, frequency adjustment
Signal generator receives the lead time signal.
3. control device as claimed in claim 1, it is characterised in that the frequency adjusted signal generator is proportional, integral control
Device.
4. control device as claimed in claim 1, it is characterised in that the frequency adjusted signal generator is a proportional, integral-micro-
Sub-controller.
5. control device as claimed in claim 1, it is characterised in that the field reference signal of the output is derived from the same of each output picture
One relative position.
6. control device as claimed in claim 1, it is characterised in that when the field reference signal of the output is joined relative to the field of the input
When examining signal and being in a backward condition, the clock generator heightens the frequency of the clock, when the field reference signal of the output is relative
When the field reference signal of the input is in a leading position state, the clock generator turns down the frequency of the clock.
7. control device as claimed in claim 1, it is characterised in that when the clock generator adjusts this according to the frequency adjusted signal
The frequency of clock so that continuously in the output picture number of a predetermined number, the lead time signal typical value is reduced below
One predetermined difference value.
8. control device as claimed in claim 1, it is characterised in that further include a crystal oscillator, the lead time signal is this
Concussion number of the crystal oscillator among the field reference signal of the output with a time difference of the field reference signal of the input.
9. control device as claimed in claim 1, it is characterised in that one first frequency eliminator and one second frequency eliminator are further included, should
First frequency eliminator receives the field sync signal of an input, and the field sync signal of the input divided by one first are worth by first frequency eliminator
To produce the field reference signal of the input, second frequency eliminator receives the field sync signal of the output, and second frequency eliminator should
The field sync signal of output divided by a second value are to produce the field reference signal of the output so that the field reference signal of the input with
And the field reference signal of the output has substantially the same frequency.
10. control device as claimed in claim 1, it is characterised in that the field that the field reference signal of the input is equal to the input is same
Signal is walked, the control device further includes one second frequency eliminator, and second frequency eliminator is by the field sync signal of the output divided by one the
Two-value is to produce the field reference signal of the output so that the field reference signal of the input and the field reference signal of the output have
Substantially the same frequency.
11. control device as claimed in claim 1, it is characterised in that further include one first pulse signal producer and one second
Pulse signal producer, first pulse signal producer receive the field sync signal of an input, and first pulse generator exists
Multiple first pulses are added in the field sync signal of the input to produce the field reference signal of the input, second pulse signal production
Raw device receives the field sync signal of the output, and second pulse generator adds multiple second in the field sync signal of the output
Pulse is to produce the field reference signal of the output.
12. a kind of synchronous method of control interface, comprising：
Judge the field reference signal of an input and the leading of a field reference signal exported or fall behind；
When the field reference signal of the output is in a backward condition relative to the field reference signal of the input, by the frequency of a clock
Heighten；And
When the output field reference signal relative to the field reference signal of the input be in a leading position state when, by the frequency of the clock
Turn down.
13. such as the method for claim 12, it is characterised in that further include：
Judge the lead time between the field reference signal of the input and the field reference signal of the output；And
Check whether the lead time is less than a predetermined difference value.
14. such as the method for claim 12, it is characterised in that further include：
Check whether the lead time is reduced below a predetermined difference value continuously in the output picture number of a predetermined number.
15. such as the method for claim 12, it is characterised in that further include：
Using a crystal oscillator calculate a time difference of the field reference signal of field reference signal and the input of the output it
In concussion number.
16. such as the method for claim 12, it is characterised in that further include：
By the field sync signal of an input divided by one first value to produce the field reference signal of the input.
17. such as the method for claim 12, it is characterised in that further include：
By the field sync signal of an output divided by a second value to produce the field reference signal of the output.
18. such as the method for claim 12, it is characterised in that further include：
Multiple first pulses are added to produce the field reference signal of the input in the field sync signal of an input.
19. such as the method for claim 12, it is characterised in that further include：
Multiple second pulses are added to produce the field reference signal of the output in the field sync signal of an output.
20. a kind of control device, for the synchronization of control interface, the control device includes：
One detector, receives the field reference signal of an input and the field reference signal of an output, the detector compare the input
Field reference signal and the output field reference signal to determine a lead time signal, the lead time signal is proportional to this
Lead time between the field reference signal of input and the field reference signal of the output；
One frequency adjusted signal generator, the lead time signal is received, the frequency adjusted signal generator is according to the time difference
Away from the frequency adjusted signal of signal output one；
One clock generator, according to the frequency adjusted signal to export a clock；And
One output timing generator, the clock is received, and the field sync signal of an output is produced according to the clock；
Wherein, the field sync signal of the output is through feeding back the field reference signal as the output, and the clock generator is according to the frequency
Rate adjustment signal adjusts the frequency of the clock so that the lead time is reduced below a predetermined difference value.
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| CN112309311A (en) * | 2019-07-26 | 2021-02-02 | 西安诺瓦星云科技股份有限公司 | Display control method, device, display control card and computer readable medium |
| CN114710700A (en) * | 2022-03-24 | 2022-07-05 | 西安诺瓦星云科技股份有限公司 | Data display method, device and equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111277725A (en) * | 2018-12-04 | 2020-06-12 | 精拓科技股份有限公司 | Automatic video detection phase synchronization system and method |
| CN112309311A (en) * | 2019-07-26 | 2021-02-02 | 西安诺瓦星云科技股份有限公司 | Display control method, device, display control card and computer readable medium |
| CN114710700A (en) * | 2022-03-24 | 2022-07-05 | 西安诺瓦星云科技股份有限公司 | Data display method, device and equipment |
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