TWI839293B - Light-emitting device and manufacturing method thereof - Google Patents

Abstract

A light-emitting device, includes: a semiconductor stack, including a first semiconductor contact layer, an active layer and a second semiconductor contact layer sequentially laminated along a thickness direction; wherein, the first semiconductor contact layer includes a first conductivity dopant and a carbon dopant with a carbon concentration; the first semiconductor contact layer includes a first region and a second region along the thickness direction; and the carbon concentration in the first region is greater than the carbon concentration in the second region, and the carbon concentration has a first peak in the first region.

Description

Light emitting element and method for manufacturing the same

The present application relates to a light-emitting device and a manufacturing method thereof, and in particular to a light-emitting device with better semiconductor stack epitaxial quality and a manufacturing method thereof.

Solid-state semiconductor components such as light-emitting diodes (LEDs) have the advantages of low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed and good photoelectric properties, such as stable luminous wavelength. Therefore, LEDs are widely used in household appliances, equipment indicator lights, and optoelectronic products.

The present application discloses a light-emitting element, comprising: a semiconductor stack, comprising a first semiconductor contact layer, an active layer, and a second semiconductor contact layer stacked in sequence along a thickness direction; wherein the first semiconductor contact layer comprises a first type dopant and a carbon dopant having a carbon concentration; the first semiconductor contact layer comprises a first region and a second region along the thickness direction; and wherein the carbon concentration of the first region is greater than the carbon concentration of the second region, and the carbon concentration has a first peak located in the first region.

The following embodiments will be accompanied by drawings and descriptions. In the drawings or descriptions, similar or identical parts use the same reference numerals, and in the drawings, the shape or thickness of the components may be enlarged or reduced. It should be noted that the components not shown in the drawings or described in the description may be in forms known to those skilled in the art in the art.

In this application, unless otherwise specified, the general formula AlGaN represents Al _a Ga _(1-a) N, where 0≤a≤1; the general formula InGaN represents In _b Ga _(1–b) N, where 0≤b≤1; the general formula AlInGaN represents Al _c In _d Ga _{(1 - cd)} N, where 0≤c≤1, 0≤d≤1. Adjusting the content of the elements can achieve different purposes, such as but not limited to adjusting the energy level or adjusting the main emission wavelength of the light-emitting element.

The composition and doping of each layer included in the light-emitting device disclosed in this application can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS).

The thickness of each layer included in the light-emitting element disclosed in this application can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM), so as to match the depth position of each layer on the SIMS spectrum, for example.

FIG1 shows a cross-sectional view of a light-emitting device 1 according to the first embodiment of the present application. The light-emitting device 1 comprises a substrate 10 and a semiconductor stack 12 located on the substrate 10. The semiconductor stack 12 comprises a buffer structure 40, a first semiconductor contact layer 121, an active region 123, an electron blocking region 70 and a second semiconductor contact layer 122 in order from the substrate 10 upward, that is, in the thickness direction thereof. The first semiconductor contact layer 121 includes a first type dopant, and the second semiconductor contact layer 122 includes a second type dopant, wherein the first type dopant and the second type dopant make the first semiconductor contact layer 121 and the second semiconductor contact layer 122 have different conductivity types, electrical properties, polarities, or are used to provide electrons or holes respectively. In one embodiment, the first type dopant includes silicon, and the second type dopant includes magnesium. The first semiconductor contact layer 121 includes a surface 121u that is not covered by the active region 123 and the second semiconductor contact layer 122. The first electrode 20 is located on the surface 121u of the first semiconductor contact layer 121 and is electrically connected thereto, and the second electrode 30 is located on the second semiconductor contact layer 122 and is electrically connected thereto.

The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for epitaxial growth of gallium indium phosphide (AlGaInP), or a sapphire (Al ₂ O ₃ ) substrate, a gallium nitride (GaN) substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). In one embodiment, the substrate 10 may be a patterned substrate, that is, the substrate 10 has a patterned structure (not shown) on the surface where the semiconductor stack 12 is located. Light emitted from the semiconductor stack 12 can be refracted by the patterned structure of the substrate 10, thereby increasing the brightness of the light-emitting element. Alternatively, in another embodiment, the substrate 10 is a supporting substrate, including a conductive material, such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or alloys thereof, or a thermal conductive material, such as diamond, graphite, ceramic material, or aluminum nitride, or a light-transmitting material, such as glass or sapphire. The semiconductor stack originally grown on the growth substrate is transferred to the aforementioned supporting substrate, and then the growth substrate is selectively removed according to the needs of the application.

In any embodiment of the present application, the method for performing epitaxial growth includes but is not limited to metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), physical vapor deposition (PVD), and liquid-phase epitaxy (LPE). Preferably, the method for performing epitaxial growth includes MOCVD.

The wavelength of the light emitted by the light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 12. The material of the epitaxial stack includes III-V group semiconductor materials, such as AlInGaP series materials, InGaN series materials, AlGaN series materials or AlInGaN series materials. When the material of the active region 123 is AlInGaP series materials, red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the active region 123 is InGaN series materials, blue light with a wavelength between 400 nm and 490 nm, cyan light with a wavelength between 490 nm and 530 nm, or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the active region 123 is AlGaN series or AlInGaN series material, ultraviolet light with a wavelength between 400 nm and 250 nm can be emitted.

The buffer structure 40 can reduce the misalignment between the substrate 10 and the semiconductor stack 12 caused by lattice mismatch, thereby improving the epitaxial quality. The buffer structure 40 includes a single layer, or includes multiple layers (not shown). In one embodiment, the buffer structure 40 includes Al _i Ga _(1–i) N, where 0≤i≤1. In one embodiment, the material of the buffer structure 40 includes GaN. In another embodiment, the material of the buffer structure 40 includes AlN. The buffer structure 40 can be formed by MOCVD, MBE, HVPE or PVD. PVD includes sputtering or electron beam evaporation. When the buffer structure 40 includes multiple sublayers (not shown), the sublayers include the same material or different materials. In one embodiment, the buffer structure 40 includes two sublayers, wherein the growth method of the first sublayer is sputtering, and the growth method of the second sublayer is MOCVD. In one embodiment, the buffer structure 40 further includes a third sublayer. The growth method of the third sublayer is MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sublayers include the same material, such as AlN, or different materials, such as a combination of AlN, GaN and AlGaN. In other embodiments, PVD-aluminum nitride (PVD-AlN) is used as a buffer layer, and a target material used to form PVD-aluminum nitride is composed of aluminum nitride, or a target material composed of aluminum is used and aluminum nitride is reactively formed in a nitrogen source environment.

In one embodiment, the buffer structure 40 may be undoped (i.e., not intentionally doped). In another embodiment, the buffer structure 40 may include dopants such as silicon, carbon, hydrogen, oxygen, or a combination thereof, and the concentration of the dopant in the buffer structure 40 is not less than 1×10 ¹⁷ /cm ³ . In some embodiments, when the buffer structure 40 includes multiple layers and includes the first type dopant, the concentration of the first type dopant in a layer close to the first semiconductor contact layer 121 is greater than the concentration of the first type dopant in a layer far from the first semiconductor contact layer 121. For example, the concentration of the first type dopant in a layer close to the first semiconductor contact layer 121 is greater than 1×10 ¹⁸ /cm ³ , and the concentration of the first type dopant in a layer far from the first semiconductor contact layer 121 is less than 1×10 ¹⁷ /cm ³ .

The material of the first semiconductor contact layer 121 includes _{AlxInyGa (1 - xy)} N _, wherein 0≦x≦1, 0≦y≦1. The first semiconductor contact layer 121 and the buffer structure 40 may be the same or different materials, and have different doping concentrations. The first type dopant concentration of the first semiconductor contact layer 121 is greater than the first type dopant concentration of the buffer structure 40. The first type dopant concentration of the first semiconductor contact layer 121 is greater than 1×10 ¹⁸ /cm ³ , preferably greater than 1×10 ¹⁹ /cm ³ , and more preferably between 1×10 ¹⁹ /cm ³ and 5×10 ²² /cm ³ (both inclusive). In another embodiment, the first semiconductor contact layer 121 includes a dopant, such as carbon. The dopant source may be present in the epitaxial raw material itself or may be added during the epitaxial growth process. FIG2 is a schematic diagram showing the distribution of carbon concentration in the first semiconductor contact layer 121 using carbon as the dopant in one embodiment of the present application. The first semiconductor contact layer 121 includes a first region 121a and a second region 121b. In one embodiment, the first region 121a and the second region 121b include the same semiconductor material. From the carbon concentration distribution trend of FIG2 , the first region 121a and the second region 121b have different carbon concentrations. In one embodiment, the first semiconductor contact layer 121 includes a plurality of first regions 121a and second regions 121b that are overlapped with each other. The thickness of the second region 121b is greater than the thickness of the first region 121a. Preferably, the thickness of the second region 121b is greater than twice the thickness of the first region 121a. In one embodiment, the plurality of first regions 121a in the first semiconductor contact layer 121 have the same thickness, and/or the plurality of second regions 121b have the same thickness. In another embodiment, the plurality of first regions 121a have different thicknesses and/or the plurality of second regions 121b have different thicknesses. As shown in FIG. 2 , the carbon concentration of the first region 121a is greater than the carbon concentration of the second region 121b, and the carbon concentration of the first region 121a varies along the thickness direction (growth direction), for example, the carbon concentration increases first and then decreases. The carbon concentration of the first region 121a has a peak value C2, and the difference between the average carbon concentration C1 of the second region 121b and the peak carbon concentration of the first region 121a is greater than or equal to 1.0×10 ^{1 6} atoms/cm ³ . In one embodiment, the ratio of the peak carbon concentration C2 of the first region 121a to the average carbon concentration C1 of the second region 121b is greater than or equal to 1.1 and less than 6, preferably, between 1.2-3.0 (including the end values). In one embodiment, the peak carbon concentration C2 of the first region 121a is between 5.0×10 ¹⁶ and 1.6×10 ¹⁸ atoms/cm ³ (inclusive), and the average carbon concentration C1 of the second region 121b is between 7.0×10 ¹⁵ and 1.2×10 ¹⁸ atoms/cm ³ (inclusive).

The active region 123 is located between the first semiconductor contact layer 121 and the second semiconductor contact layer 122. Electrons and holes are combined in the active region 123 under the current drive, and the electrical energy is converted into light energy to emit light. The active region 123 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). In one embodiment, the active region 123 includes a multi-quantum well, which is composed of a plurality of well layers (not shown) and a plurality of barrier layers (not shown) overlapped with each other. The material of the active region 123 can be an i-type, p-type, or n-type semiconductor. The wavelength of light emitted by the semiconductor stack 12 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 12. In one embodiment, the semiconductor stack 12 may further include other layers between the first semiconductor contact layer 121 and the active region 123. For example, in order to reduce the lattice difference between the first semiconductor contact layer 121 and the active region 123 to reduce epitaxial defects, a stress release structure (not shown) can be formed between the first semiconductor contact layer 121 and the active region 123. The stress release layer is, for example, a superlattice structure, which is formed by overlapping two semiconductor layers composed of different materials, such as an indium gallium nitride layer (InGaN) and a gallium nitride (GaN) layer, or an aluminum gallium nitride layer (AlGaN) and a gallium nitride (GaN) layer. The stress release structure can also be composed of multiple semiconductor layers composed of different materials with the same effect, such as a multi-layer structure with a gradient composition of group III elements.

The electron blocking region 70 is located between the active region 123 and the second semiconductor contact layer 122. The electron blocking region 70 can block the electrons injected from the first semiconductor contact layer 121 into the active region 123 from flowing out into the second semiconductor contact layer 122 without being combined in the well layer (not shown) in the active region 123. The electron blocking region 70 has a higher energy gap than the barrier layer in the active region 123. The electron blocking region 70 may include a single layer, multiple sub-layers, or a plurality of alternating first sub-layers and second sub-layers. In one embodiment, a plurality of alternating first sub-layers and second sub-layers form a superlattice structure. In one embodiment, the electron blocking region 70 includes the second type dopant, and the doping concentration thereof is greater than 1×10 ¹⁷ /cm ³ and/or does not exceed 1×10 ²¹ /cm ³ .

The second semiconductor contact layer 122 is located on the electron blocking region 70. In some embodiments, the doping concentration of the second type dopant in the second semiconductor contact layer 122 is not less than 1×10 ¹⁸ /cm ³ , preferably, not less than 1×10 ¹⁹ /cm ³ , and more preferably, between 1×10 ¹⁹ /cm ³ and 1×10 ²¹ /cm ³ (including the end values). In one embodiment, the second semiconductor contact layer 122 comprises Al _x1 In _x2 Ga _(1–x1-x2) N, wherein 0≦x1≦1, 0≦x2≦1. In one embodiment, x2=0, 0＜x1≦0.1, and preferably, 0＜x1≦0.05, so as to improve the luminous efficiency. In another embodiment, the second semiconductor contact layer 122 includes GaN. The second semiconductor contact layer 122 has a thickness not exceeding 15 nm, and preferably, exceeds 3 nm. In one embodiment, the second semiconductor contact layer 122 further includes a first type dopant, such as Si, wherein the doping concentration of the second type dopant is greater than the doping concentration of the first type dopant. In some embodiments, the second semiconductor contact layer 122 includes a multi-layer structure, such as a superlattice structure. By adjusting the multi-layer structure, the doping concentration or material composition from the electron blocking region 70 to the outermost layer of the second semiconductor contact layer 122 is gradually adjusted, so that the epitaxial quality of the second semiconductor contact layer 122 is improved. In one embodiment, in addition to the electron blocking region 70, one or more other structures may be included between the active region 123 and the second semiconductor contact layer 122. For example, a diffusion prevention layer (not shown) located between the electron blocking region 70 and the active region 123 is used to prevent the second type dopant of the second semiconductor contact layer 122 or the electron blocking region 70 from diffusing into the active region 123, thereby preventing the epitaxial quality of the active region 123 from deteriorating or the efficiency from deteriorating.

FIG3A shows a method for growing a semiconductor stack 12 in an embodiment of the present application. More specifically, FIG3A is a temperature-time relationship diagram for forming a buffer structure 40 and a first semiconductor contact layer 121 in an embodiment of the present application. The first region 121a in the first semiconductor contact layer 121 is grown under a first growth condition, and the second region 121b is grown under a second growth condition. In one embodiment, the first growth condition and the second growth condition include different growth temperatures. Referring to FIG3A , first, the buffer structure 40 is grown at a temperature T2, and after the buffer structure 40 is formed, that is, in the period from time t1 to time t2, the second region 121b of the first semiconductor contact layer 121 is also grown at a temperature T2. In the time segment from t2 to t3, the first region 121a of the first semiconductor contact layer 121 is grown by adjusting the temperature while growing. When the time reaches t2 and the growth of the second region 121b is completed, the temperature starts to drop while the first region 121a is grown. When the temperature drops to T1, the temperature T1 is maintained for a time segment, that is, the first region 121a continues to grow from the time segment from t21 to t22. Then, in the time segment from t22 to t3, the temperature starts to rise from T1 to T2 while the first region 121a is grown. The first semiconductor contact layer 121 is a homogeneous material, that is, the first region 121a and the second region 121b contain semiconductor materials composed of elements in the same proportion. The temperature T2 is higher than the temperature T1. In one embodiment, the temperature T2 is between 900°C and 1200°C, and the temperature T1 is between 800°C and 1100°C. In one embodiment, the difference between T2 and T1 is greater than or equal to 30°C. In one embodiment, the difference between T2 and T1 is between 30°C and 100°C. When the difference between T2 and T1 is less than 30°C, the stress of the semiconductor stack cannot be effectively released. In another embodiment, the growth temperature of the buffer structure 40 may be different from the growth temperature of the second region 121b, but higher than the growth temperature of the first region 121a, such as the growth temperature T of the buffer structure 40, wherein T1＜T＜T2 or T1＜T2＜T, preferably, the temperature T is between 900°C and 1200°C. The above temperature ranges may include end values. The growth time of the second region 121b (the time period from time t1 to t2) is greater than or equal to the growth time of the first region 121a (the time period from time t2 to t3), and the thickness of the second region 121b formed at the same growth rate is greater than or equal to the thickness of the first region 121a. Preferably, the growth time of the second region 121b is greater than or equal to twice the growth time of the first region 121a, and the thickness of the second region 121b is greater than or equal to twice the thickness of the first region 121a. When the growth time of the second region 121b is less than the growth time of the first region 121a, or the thickness of the second region 121b is less than the thickness of the first region 121a, it is easy to cause poor quality of semiconductor epitaxy, thereby reducing the brightness of the light-emitting element 1.

As shown in FIG3A , the growth method of the first semiconductor contact layer 121 includes repeatedly growing the first region 121a and the second region 121b. However, the present embodiment is not limited thereto, and the growth method of the first semiconductor contact layer 121 may include only growing a first region 121a and a second region 121b. In another embodiment, when a plurality of first regions 121a and a second region 121b are arranged overlapping each other, the time for growing the plurality of first regions 121a may be different, and/or the time for growing the plurality of second regions 121b may be different. For example, the time segment length from t2 to t3 for growing the first first zone 121a may be different from the time segment length from t4 to t5 for growing the second first zone 121a, and/or the time segment length from t1 to t2 for growing the first second zone 121b may be different from the time segment length from t3 to t4 for growing the second second zone 121b. In another embodiment, taking the growth of the first first zone 121a as an example, the cooling time segment length from t2 to t21, the holding time segment length from t21 to t22, and the heating time segment length from t22 to t3 may be the same or different. In one embodiment, the cooling time segment length is equal to the heating time segment length and is greater than the holding time segment length. In one embodiment, the cooling time segment length is greater than the heating time segment length, and the heating time segment length is greater than the holding time segment length. In one embodiment, the heating time segment length is greater than the cooling time segment length, and the cooling time segment length is greater than the holding time segment length. The time and temperature adjustment method for growing the second first zone 121a can be the same or different from the method for growing the first first zone 121a. For example, the holding temperature for growing the second first zone 121a can be different from the holding temperature for growing the first first zone 121a.

FIG3B shows a semiconductor stacking growth method of another embodiment of the present application. Different from the method described in FIG3A, FIG3B shows that after the buffer structure 40 is formed, the first region 121a is first grown. The buffer structure 40 is grown at a temperature T2, and after the buffer structure 40 is formed, that is, starting from time t1, the temperature is lowered and the first region 121a is grown. When the temperature drops to T1, it is maintained for a time period, that is, the time period from time t11 to t12, and then the temperature is raised from T1 to T2, and the first region 121a of the first semiconductor contact layer 121 is grown from time t1 to t2. Next, the second region 121b of the first semiconductor contact layer 121 is grown at the temperature T2 for a time period from t2 to t3. Similar to the method described in FIG. 3A, the growth time of the second region 121b (a time period from t2 to t3) is greater than or equal to the growth time of the first region 121a (a time period from t1 to t2). As shown in FIG. 3B, the growth method of the first semiconductor contact layer 121 includes repeatedly implementing the growth of the first region 121a and the second region 121b. However, the present embodiment is not limited thereto, and the growth method of the first semiconductor contact layer 121 may include only growing a first region 121a and a second region 121b. In another embodiment, the time for repeating the growth of the first zone 121a may be different, and/or the time for repeating the growth of the second zone 121b may be different. For example, the time length from t1 to t2 may be different from the time length from t3 to t4, and/or the time length from t2 to t3 may be different from the time length from t4 to t5. In another embodiment, as in the aforementioned embodiment of FIG. 3A, taking the growth of a first zone 121a as an example, the lengths of the cooling time segment from t1 to t11, the temperature holding time segment from t11 to t12, and the heating time segment from t12 to t2 may be the same or different. The time and temperature adjustment method for growing one of the first zones 121a may be the same or different from the method for growing another of the first zones 121a.

In another embodiment (not shown), when growing the first region 121a in the first semiconductor contact layer 121, the growth is interrupted in the time period of temperature change (e.g., t2 to t21 and t22 to t3 in FIG. 3A , or t1 to t11 and t12 to t2 in FIG. 3B ). In this embodiment, for example, in the interrupted growth time period of t2 to t21 and/or t22 to t3 in FIG. 3A , no III-group or V-group reactant enters the reactor, and the first region 121a is not grown, or the residual III-group and V-group reactants in the reactor react to grow an intermediate layer, whose composition is different from that of the first region 121a. The growth time of the first zone 121a can be regarded as a temperature-maintaining time period, such as the time period from t21 to t22 in FIG. 3A , or the time period from t11 to t12 in FIG. 3B . The temperature of the reactor is set and maintained at the growth temperature T1 to grow the first zone 121a.

FIG4 shows a graph showing the relationship between the flow rate of the first type dopant and time when forming the buffer structure 40 and the first semiconductor contact layer 121 in one embodiment of the present application. In one embodiment, as shown in variation A of FIG4 , when growing the first region 121a and the second region 121b, the flow rate of the first type dopant introduced is substantially equal, and the doping source of the first type dopant is, for example, silane (SiH4). Thus, in the first semiconductor contact layer 121 formed by the growth method of this embodiment, the first region 121a and the second region 121b contain substantially the same first type dopant concentration.

In the growth method of FIG. 3A and FIG. 3B , the first type dopant flow rate may be different when growing the first region 121a and the second region 121b. Referring to variation B of FIG. 4 , the first type dopant flow rate when growing the first region 121a is lower than the first type dopant flow rate when growing the second region 121b, and higher than the first type dopant flow rate when growing the buffer structure 40. In this way, in the first semiconductor contact layer 121 formed by the growth method of this embodiment, the first type dopant concentration in the first region 121a is lower than the first type dopant concentration in the second region 121b. The first type dopant concentration of the first region 121a is greater than the first type dopant concentration of the buffer structure 40.

Referring to variation C of FIG. 4 , the first type dopant flow rate introduced when growing the first region 121a is higher than the first type dopant flow rate introduced when growing the second region 121b, and the first type dopant flow rate introduced when growing the second region 121b is higher than the first type dopant flow rate introduced when growing the buffer structure 40. Thus, in the first semiconductor contact layer 121 formed by the growth method of this embodiment, the first type dopant concentration in the first region 121a is higher than the first type dopant concentration in the second region 121b. The first type dopant concentration in the second region 121b is higher than the first type dopant concentration in the buffer structure 40. In variation B and variation C, the second region 121b and the first region 121a have different resistance values. By having different resistance values between the second region 121b and the first region 121a, the injected current can have better lateral current dispersion in the first semiconductor layer 121, thereby improving the anti-electrostatic discharge (ESD) damage capability of the light-emitting element 1 and improving the light-emitting efficiency of the light-emitting element 1. Generally speaking, a high-temperature or high-doping epitaxial process is more likely to generate stress, so in variation C, the second region 121b with a lower first-type dopant concentration is grown at a higher temperature to improve its epitaxial quality. The first region 121a with a higher first-type dopant concentration is grown at a lower temperature to reduce its stress. By using the second region 121b with high epitaxial quality and the first region 121a with high doping and low resistance, the semiconductor stack 12 can have better current spreading while taking epitaxial quality into consideration.

In the first type dopant flow and time relationship diagram shown in FIG4, the time t1, t2, t21 ... corresponds to the time t1, t2, t21 ... in FIG3A. In another embodiment, the lengths of the time segments from t2 to t21 in which the first type dopant flow gradually decreases in variation B, the time segment from t21 to t22 in which the first type dopant flow is maintained, and the time segment from t22 to t3 in which the first type dopant flow gradually increases can be the same or different. Conversely, the same is true in variation C. In one embodiment, the length of the time segment in which the flow gradually decreases is equal to the length of the time segment in which the flow gradually increases, and is greater than the length of the time segment in which the flow is maintained. In one embodiment, the length of the time segment of the flow rate gradually decreases is greater than the length of the time segment of the flow rate gradually increases, and the length of the time segment of the flow rate gradually increases is greater than the length of the time segment of the flow rate maintained. In one embodiment, the length of the time segment of the flow rate gradually increases is greater than the length of the time segment of the flow rate gradually decreases, and the length of the time segment of the flow rate gradually decreases is greater than the length of the time segment of the flow rate maintained. In one embodiment, the length of the time segment of the flow rate maintained is greater than the length of the time segment of the flow rate gradually decreases, and the length of the time segment of the flow rate gradually decreases is greater than the length of the time segment of the flow rate gradually increases. In one embodiment, the length of the time segment during which the flow is maintained is greater than the length of the time segment during which the flow is gradually increased, and the length of the time segment during which the flow is gradually increased is greater than the length of the time segment during which the flow is gradually decreased.

In another embodiment (not shown), there is no flow increase or decrease time segment, that is, in FIG4 variation B, before the first zone 121a is grown, the flow of the first type of dopant has been adjusted to a fixed flow, for example, to a fixed flow lower than the flow of the second zone 121b. In the time segment t2 to t3 and the time t4 to t5, the first type of dopant is maintained at a lower fixed flow; or in FIG4 variation C, the time t2 to t3 and the time t4 to t5, the first type of dopant is maintained at a higher flow than the flow of the second zone 121b.

In another embodiment (not shown), the flow rate of the first type dopant introduced into the second first zone 121a for growth may be the same as or different from the flow rate of the first type dopant introduced into the first first zone 121a for growth. Similarly, the flow rate of the first type dopant introduced into the second second zone 121b for growth may be the same as or different from the flow rate of the first type dopant introduced into the first second zone 121b for growth.

During the epitaxial growth process of the first semiconductor contact layer, it is usually in a high temperature and highly doped growth environment. Because during the high temperature and highly doped epitaxial growth process, the deformation of the substrate will increase and the accumulated stress will be generated in the semiconductor stack. The growth method of this embodiment uses different temperatures during the growth process of the first semiconductor contact layer to release the stress of the semiconductor stack and maintain the epitaxial quality. In addition, the buffer structure 40 is also grown at a high temperature. If the first semiconductor contact layer 121 is subsequently grown at a high temperature, the stress caused by the continuous high temperature in the semiconductor stack 12 will continue to accumulate, causing the epitaxial wafer to warp due to temperature stress, thereby deteriorating the epitaxial quality. Therefore, in this embodiment, in the middle stage of the semiconductor stack high temperature growth area, for example, after the buffer structure 40 is formed, when the first semiconductor contact layer 121 is grown, the growth temperature of the first area 121a and the second area 121b is changed by stepwise temperature rise and fall, so as to release the stress of the semiconductor stack and maintain the quality of the epitaxial layer grown next. The carbon concentration distribution diagram of the first semiconductor contact layer 121 formed by the growth method of this embodiment is shown in the aforementioned FIG2. In FIG1, the surface 121u of the first semiconductor contact layer 121 of the light-emitting element 1 that is exposed and electrically connected to the first electrode 20 is a surface exposed by the first region 121a or the second region 121b. The first region 121a and the second region 121b exist in the portion of the first semiconductor contact layer 121 between the first electrode 20 and the buffer structure 40.

In some embodiments, the first growth condition of the first region 121a and the second growth condition of the second region 121b may include different V-III group feed ratios, different epitaxial growth rates, and different growth pressures to adjust the carbon concentrations of the first region 121a and the second region 121b, so as to achieve a higher carbon concentration in the first region 121a, thereby reducing the surface linear epitaxial defects generated by the semiconductor device 1 during the epitaxial process and improving the epitaxial quality.

FIG5 shows a cross-sectional view of a light emitting device 2 according to a second embodiment of the present application. The difference between the light emitting device 2 and the light emitting device 1 is that the semiconductor stack 12 of the light emitting device 2 further includes an insertion layer 60 between the buffer structure 40 and the first semiconductor contact layer 121. In some embodiments, the insertion layer 60 has a modulation function and can serve as a modulation function between the first semiconductor contact layer 121 and the buffer structure 40. For example, due to the difference in materials between the first semiconductor contact layer 121 and the buffer structure 40, lattice mismatch or stress between material layers is caused, or due to the difference in growth temperature between the first semiconductor contact layer 121 and the buffer structure 40, epitaxial wafer warp problem is caused. By modulating the material of the insertion layer 60, modulating the dopant, modulating the structure, or modulating the epitaxial growth conditions, the adverse effects caused by the difference between the first semiconductor contact layer 121 and the buffer structure 40 can be reduced. The insertion layer 60 can reduce the defects of epitaxy caused by temperature or stress and improve the quality of epitaxy. By improving the quality of epitaxy, the leakage current (Ir) of the light-emitting element 2 is improved and the ESD capability is enhanced. In some embodiments, the insertion layer 60 includes AlInGaN series materials. In some embodiments, the insertion layer 60 includes GaN or _InGaN . In other embodiments, the insertion layer 60 includes _{Alz1Inz2Ga (1 - z1-z2)} N, where 0≦z2＜z1≦1, z1≧x. In some embodiments, the insertion layer 60 includes _{AlzGa (1-z)} N, where 0≦z≦1. In some embodiments, 0＜z≦0.1. In some embodiments, 0＜z≦0.05.

The insertion layer 60 may be doped or undoped (i.e., not intentionally doped). In some embodiments, the insertion layer 60 includes a first type dopant. In some embodiments, the doping concentration of the first type dopant in the insertion layer 60 is not equal to or equal to the doping concentration of the first type dopant in the first semiconductor contact layer 121. In some embodiments, the doping concentration of the first type dopant in the insertion layer 60 is less than or equal to the doping concentration of the first type dopant in the first semiconductor contact layer 121. In some embodiments, the doping concentration of the first type dopant in the insertion layer 60 is not greater than 3×10 ¹⁹ /cm ³ . In some embodiments, the doping concentration of the first type dopant in the insertion layer 60 is between 1×10 ¹⁸ /cm ³ and 2×10 ¹⁹ /cm ³ (including the end values). In some embodiments, the insertion layer 60 is undoped, and a two-dimensional electron gas (2DEG) is formed between the undoped insertion layer 60 and the buffer structure 40 thereunder, which can further enhance the current spreading effect of the device. In some embodiments, the insertion layer 60 contains carbon, and its carbon concentration is greater than the carbon concentration of the second region 121b or greater than or equal to the carbon concentration of the first region 121a. In one embodiment, the carbon concentration of the insertion layer 60 has a peak value C3, which is greater than or equal to the carbon concentration peak value C2 of the first region 121a. In one embodiment, the difference between the carbon concentration peak value C3 of the insertion layer 60 and the carbon concentration peak value C2 of the first region 121a is greater than or equal to 3×10 ¹⁶ atoms/cm ³ . In one embodiment, the ratio of the carbon concentration peak value C3 of the insertion layer 60 to the carbon concentration peak value C2 of the first region 121a is between 1 and 10, preferably, between 1.4 and 3.0 (including the end values).

In some embodiments, the thickness of the insertion layer 60 is smaller than the thickness of the buffer structure 40 and/or the first semiconductor layer 121. Preferably, it is between 1 nm and 200 nm (inclusive). In one embodiment, the thickness of the insertion layer 60 is smaller than the thickness of the second region 121 b. In one embodiment, the carbon concentration peak value C3 of the insertion layer 60 is greater than 1×10 ¹⁷ atoms/cm ³ , preferably, between 1×10 ¹⁷ atoms/cm ³ and 8×10 ¹⁸ atoms/cm ³ (inclusive).

FIG6A to FIG6C respectively show the semiconductor stacking growth method of the light-emitting element 2 according to different embodiments. More specifically, FIG6A to FIG6C respectively show the temperature and time relationship diagrams of forming the buffer structure 40, the insertion layer 60 and the first semiconductor contact layer 121 in different embodiments of the present application. The growth temperature of the insertion layer 60 is lower than the growth temperature of the buffer structure 40 and the second region 121b in the first semiconductor contact layer. Referring to FIG6A, first, the buffer structure 40 is grown at a temperature T2, and after the buffer structure 40 is formed, the insertion layer 60 is grown at a temperature T3 starting at time t1. Among them, the temperature T3 is less than the temperature T2. In one embodiment, the difference between T3 and T2 is greater than or equal to 30°C; preferably, the difference between T3 and T2 is greater than or equal to 50°C. In one embodiment, the difference between T3 and T2 is between 30°C and 200°C (inclusive). In one embodiment, temperature T3 is less than or equal to temperature T1. In one embodiment, while growing the insertion layer 60, temperature T3 is raised to T2. After the insertion layer 60 is formed, the second region 121b and the first region 121a of the first semiconductor contact layer 121 are then grown. That is, starting from time t2, the second region 121b of the first semiconductor contact layer 121 is grown at temperature T2. When the time reaches t3, the first region 121a of the first semiconductor contact layer 121 is grown from time t3 to t4. The temperature is first lowered and then, after the temperature drops from T2 to T1, the temperature is maintained for a time period, that is, from time t31 to t32, and then the temperature is raised from T1 to T2. The growth method of the first semiconductor contact layer 121 is the same as that of the light-emitting element 1 of the first embodiment, and will not be described in detail here.

Referring to FIG. 6B , the difference from the method shown in FIG. 6A is that after the buffer structure 40 is formed, starting from time t1, the temperature is lowered from temperature T2 to temperature T3 and the insertion layer 60 is grown at the same time. The relationship among the temperatures T1, T2 and T3 is the same as in the aforementioned embodiment and will not be described in detail. After the insertion layer 60 is formed, the first semiconductor contact layer 121 is grown. In one embodiment, before the first semiconductor contact layer 121 is grown, the reactor first interrupts the growth, and the temperature is raised from temperature T1 to temperature T2, and then starting from time t2, the second region 121b of the first semiconductor contact layer 121 is grown at temperature T2.

Referring to FIG. 6C , the difference from the method shown in FIG. 6A and FIG. 6B is that after the buffer structure 40 is formed, the insertion layer 60 is grown at a temperature maintained at T3 starting from time t1. The relationship among the temperatures T1, T2 and T3 is the same as in the aforementioned embodiment and will not be described in detail. After the insertion layer 60 is formed, the first semiconductor contact layer 121 is grown. In one embodiment, before the first semiconductor contact layer 121 is grown, the reactor first interrupts the growth and raises the temperature from temperature T3 to temperature T2, that is, starting from time t2, the second region 121b of the first semiconductor contact layer 121 is grown at temperature T2.

In the semiconductor stack growth method shown in FIG. 6A to FIG. 6C , after the insertion layer 60 is formed, the second region 121b of the first semiconductor contact layer 121 is subsequently grown; however, the present embodiment is not limited thereto, and after the insertion layer 60 is formed, the first region 121a of the first semiconductor contact layer 121 may be grown first, and then the second region 121b may be grown. The temperature increase and decrease method or the growth method of the first region 121a and the second region 121b are similar to those of the aforementioned embodiment and will not be described in detail. In the semiconductor stack 12 formed by the semiconductor stack growth method according to the present embodiment, as mentioned above, the carbon concentration of the insertion layer 60 has a peak value C3, which is greater than or equal to the carbon concentration peak value C2 of the first region 121a.

In the present application, after epitaxially growing the semiconductor stack 12, the light-emitting element 1 or 2 of any embodiment removes part of the semiconductor stack 12 by an etching process, so that the surface 121u of the first semiconductor contact layer 121 is exposed. A first electrode 20 is formed on the surface 121u to be electrically connected to the first semiconductor contact layer 121, and a second electrode 30 is formed on the second semiconductor contact layer 122 to be electrically connected thereto. The first electrode 20 and the second electrode 30 are used to connect to an external power source or other electronic components and conduct current therebetween. The materials of the first electrode 20 and the second electrode 30 include metal materials. The metal material includes chromium (Cr), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), nickel (Ni), rhodium (Rh), platinum (Pt), germanium-gold-nickel (GeAuNi), titanium (Ti), benzene-gold (BeAu), germanium-gold (GeAu), aluminum (Al), zinc-gold (ZnAu) or nickel (Ni). In some embodiments, the first electrode 20 and/or the second electrode 30 is a single layer, or a structure including multiple layers such as Ti/Au layer, Ti/Al layer, Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer, Ti/Al/Ti/Au layer, Cr/Ti/Al/Au layer, Cr/Al/Ti/Au layer, Cr/Al/Ti/Pt layer or Cr/Al/Cr/Ni/Au layer, or a combination thereof. In one embodiment, the light-emitting element 1 or 2 is further provided with a transparent conductive layer (not shown) between the second electrode 30 and the second semiconductor contact layer 122. The material of the transparent conductive layer includes a transparent conductive oxide or a light-transmitting thin metal, wherein the transparent conductive material is, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (Zn ₂ SnO ₄ , ZTO), gallium doped zinc oxide (GZO), tungsten doped indium oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO).

In another embodiment, the first electrode 20 and the second electrode 30 are respectively located on opposite sides of the substrate 10. In this case, the substrate 10 includes a conductive material.

FIG7 shows a light-emitting device package 100 according to an embodiment of the present application. As shown in FIG7 , the light-emitting device package 100 includes a main body 16 having a cavity 160, a first lead terminal 50a and a second lead terminal 50b disposed in the main body 16, a light-emitting device 1 or 2 according to any embodiment of the present application, a lead 14, and a packaging material 23. The cavity 160 may include an opening structure that is recessed from the top surface of the main body 16. In an embodiment, the side wall of the cavity 160 may include a reflective structure. The first lead terminal 50a is disposed in a first region of the bottom region of the cavity 160, and the second lead terminal 50b is disposed in a second region of the bottom region of the cavity 160. The first lead terminal 50a and the second lead terminal 50b are separated from each other in the cavity 160. The light-emitting element 1 or 2 is disposed on at least one of the first and second lead terminals 50a and 50b. For example, the light-emitting element 1 or 2 can be disposed on the first lead terminal 50a, and the first electrode 20 and the second electrode 30 (not shown) of the light-emitting element are electrically connected to the first and second lead terminals 50a and 50b respectively by the wire 14. The packaging material 23 is disposed in the cavity 160 of the main body 16 and covers the light-emitting element 1 or 2. The packaging material 23 includes, for example, silicone or epoxy resin, and its structure can be a single layer or multiple layers. In one embodiment, the packaging material 23 can further include a wavelength conversion material for changing the wavelength of light generated by the light-emitting element 1 or 2, such as fluorescent powder, and/or scattering material.

In another embodiment of the present application, the elements or structures in the above-mentioned embodiments may be changed or combined with each other.

It should be noted that the various embodiments listed in the present invention are only used to illustrate the present invention and are not used to limit the scope of the present invention. Any obvious modifications or changes made to the present invention by anyone do not deviate from the spirit and scope of the present invention. The same or similar components in different embodiments, or components with the same labels in different embodiments all have the same physical or chemical properties. In addition, the above-mentioned embodiments of the present invention can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. The connection relationship between a specific component and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of the scope of protection of the present invention as described below.

1, 2                 Light-emitting element 10                     Substrate 100                   Light-emitting element package 12                     Semiconductor stack 121                   First semiconductor contact layer 121a                 First region 121b                 Second region 121u                    Surface 122                     Second semiconductor contact layer 123                     Active region 14                     Wire 16                     Main body 160                     Cavity 20                     First electrode 30                     Second electrode 23                     Package material 40                     Buffer structure 50a, 50b         Wire terminal 60                     Insertion layer 70                     Electronic blocking area C1, C2            Concentration T1, T2, T3    Temperature

﹝Figure 1﹞shows a cross-sectional view of the light-emitting element 1 of the first embodiment of the present application. ﹝Figure 2﹞shows a schematic diagram of the distribution of carbon concentration in the light-emitting element 1 of the first embodiment of the present application. ﹝Figure 3A﹞shows a method for growing a semiconductor stack 12 of the first embodiment of the present application. ﹝Figure 3B﹞shows a method for growing a semiconductor stack 12 of another embodiment of the present application. ﹝Figure 4﹞shows a graph showing the relationship between the flow rate of the first type dopant and time in the method for growing a semiconductor stack 12 of the first embodiment of the present application. ﹝Figure 5﹞shows a cross-sectional view of the light-emitting element 2 of the second embodiment of the present application. ﹝Figures 6A to 6C respectively show semiconductor stacking growth methods of the light-emitting element 2 according to different embodiments. ﹝Figure 7﹞ shows a light-emitting element package 100 according to an embodiment of the present application.

121a                 Zone 1 121b                 Zone 2 C1, C2            Concentration

Claims (10)

A light-emitting element comprises: A semiconductor stack, comprising a first semiconductor contact layer, an active layer, and a second semiconductor contact layer stacked in sequence along a thickness direction; wherein the first semiconductor contact layer comprises a first type dopant and a carbon dopant having a carbon concentration; the first semiconductor contact layer comprises a first region and a second region along the thickness direction; and wherein the carbon concentration of the first region is greater than the carbon concentration of the second region, and the carbon concentration has a first peak located in the first region. A light-emitting element as claimed in claim 1, wherein the first semiconductor contact layer comprises a plurality of first regions and a plurality of second regions which are arranged overlapping with each other. A light-emitting element as claimed in claim 1, wherein the thickness of the second region is greater than the thickness of the first region. A light-emitting element as claimed in claim 3, wherein a thickness of the second region is greater than twice a thickness of the first region. The light-emitting device of claim 1, wherein a difference between the first peak and an average carbon concentration of the second region is greater than or equal to 1×10 ¹⁶ atoms/cm ³ , and/or a ratio of the first peak to the average carbon concentration of the second region is between 1.2 and 3.0. A light-emitting element as claimed in claim 1, wherein: the first semiconductor contact layer includes a surface not covered by the active layer and the second semiconductor contact layer; and the light-emitting element further includes a first electrode located on the surface and a second electrode electrically connected to the second semiconductor contact layer. A light-emitting element as claimed in claim 6, wherein the first semiconductor contact layer includes an upper portion and the surface is not covered by the upper portion. The light-emitting element of claim 1, wherein the semiconductor stack further comprises a buffer structure located under the first semiconductor contact layer, wherein the buffer structure comprises the first type dopant, and the first type dopant concentration of the buffer structure is less than the first type dopant concentration of the first semiconductor contact layer. The light-emitting element of claim 1, wherein the semiconductor stack further comprises a buffer structure located under the first semiconductor contact layer, wherein the first semiconductor contact layer comprises the same or different material as the buffer structure. A light-emitting element as claimed in claim 8 or 9, wherein the semiconductor stack further comprises an insertion layer located between the buffer structure and the first semiconductor contact layer, wherein the thickness of the insertion layer is less than the thickness of the second region, or the insertion layer comprises a carbon dopant having a carbon concentration, and the carbon concentration of the insertion layer has a second peak value greater than the first peak value.

Images