TWI824464B - Electronic device and a startup method for the electronic device - Google Patents

Abstract

An electronic device and a startup method for the electronic device are provided. The electronic device is awakened in a one-shot manner when a battery module is in the power-saving state. The electronic device includes a startup button, a controller, a battery control circuit, and a delay circuit. When the startup button is clicked, a voltage level of the startup signal is pulled down. The controller generates a control signal in response to the startup signal pulled down to a low voltage level. The battery control circuit provides an operating signal in response to the control signal, so that the battery module is awakened to provide a driving power. The delay circuit extends a time length of the startup signal at the low voltage level in response to the operating signal, so that a time point of a rising edge of the startup signal is later than a supply time point of the driving power.

Description

Electronic device and starting method for electronic device

The present invention relates to an electronic device and a starting method for the electronic device, and in particular to an electronic device and a starting method whose battery module is awakened by clicking when the battery module is in a power saving state.

A general electronic device will have a small battery installed on the motherboard. Small batteries are used to provide power for maintaining status information of the electronic device when the electronic device is in a sleep state or shutdown state. For example, the electronic device is a desktop computer or a notebook computer. A small battery provides the power needed by the basic input and output system (BIOS).

As the internal design of electronic devices needs to be streamlined, the current more advanced battery technology will use battery modules to replace small batteries to increase the flexibility of the internal design.

However, when the capacity of the battery module is lower than a preset value, it will enter a power saving state to ensure that the battery module can provide sufficient power to maintain status information of the electronic device. When the start button is pressed, the battery module is awakened so that the electronic device can start normal operation. It should be noted that it takes a first time for the battery module to wake up. It takes a second length of time for the battery module to provide driving power. In addition, it takes a third length of time for the internal controller of the electronic device to be awakened (or activated) after receiving the driving power. That is, in order for the electronic device to start normal operation, the pressing time of the start button must be greater than the sum of the first time length, the second time length, and the third time length. Such operations will affect the user's operating experience.

The present invention provides an electronic device and a starting method for the electronic device, which can wake up the electronic device with a single click when a battery module of the electronic device is in a power saving state.

The electronic device of the present invention is awakened by a single click when the battery module of the electronic device is in a power saving state. The electronic device includes a start button, controller, battery control circuit, and delay circuit. When the start button is clicked, the voltage level of the start signal is pulled down. The controller generates the control signal in response to the enable signal being pulled down to a low voltage level. The battery control circuit is coupled to the controller and the battery module. The battery control circuit responds to the control signal to provide an operating signal, so that the battery module responds to the operating signal to wake up from the power saving state and enter the discharge state to provide driving power for driving the electronic device. The delay circuit is coupled to the battery control circuit. The delay circuit responds to the operating signal to extend the time the start signal is at a low voltage level, so that the rising edge time point of the start signal lags behind the supply time point of the driving power.

The startup method for an electronic device of the present invention includes: generating a control signal in response to a startup signal that is pulled down to a low voltage level, wherein when the startup button is clicked, the voltage level of the startup signal is pulled down; Control the signal to provide the operating signal; cause the battery module of the electronic device to wake up from the power saving state and enter the discharge state in response to the operating signal to provide driving power for driving the electronic device; and respond to the operating signal to extend the startup signal The length of time at the low voltage level causes the rising edge of the start signal to lag behind the supply time of driving power.

Based on the above, the electronic device of the present invention generates a control signal in response to the activation signal generated by a single click operation, and provides an operation signal in response to the control signal. Therefore, the battery module is awakened to provide driving power. In addition, the present invention also responds to the operation signal to extend the time the start signal is at a low voltage level, so that the rising edge of the start signal lags behind the supply time point of the driving power. Therefore, the user does not need to extend the pressing time of the start button. In this way, the electronic device of the present invention can wake up the battery module and the electronic device with just a single click operation.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the invention.

Please refer to FIG. 1 , which is a schematic diagram of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 100 may be a desktop computer or a notebook computer. The electronic device 100 includes a start button PB, a controller 110, a battery control circuit 120, a battery module 130 and a delay circuit 140. In this embodiment, when the battery module 130 is in the power saving state, the electronic device 100 is awakened in a one-shot manner. When the start button PB is clicked, the voltage level of the start signal P_SW is pulled down to a low voltage level. When the start button PB is released, the voltage level of the start signal P_SW is raised back to the high voltage level. Therefore, the time period during which the activation signal P_SW is at the low voltage level during the click operation is less than or equal to 1 second. In this embodiment, the electronic device 100 can perform a wake-up operation while the activation signal P_SW is at a low voltage level. The controller 110 generates the control signal ALWON in response to the enable signal P_SW being pulled down to a low voltage level. For example, the controller 110 is triggered in response to the falling edge of the enable signal P_SW, thereby starting to generate the control signal ALWON. In this embodiment, the controller 110 may be implemented by an embedded controller (Embedded Controller, EC) in the electronic device 100 . In this embodiment, the start button PB can be any type of power-on key.

In this embodiment, the battery control circuit 120 is coupled to the controller 110 and the battery module 130 . The battery control circuit 120 provides the operating signal SYS_PRES in response to the control signal ALWON. The battery module 130 responds to the operation signal SYS_PRES and wakes up from the power saving state, thereby entering the discharge state. In the discharge state, the battery module 130 provides driving power PWR for driving the electronic device 100 . The delay circuit 140 is coupled to the battery control circuit 120 to receive the operation signal SYS_PRES. The delay circuit 140 responds to the operation signal SYS_PRES to extend the time period during which the start-up signal P_SW is at a low voltage level, so that the time point of the rising edge of the start-up signal P_SW lags behind the supply time point of the driving power PWR.

It is worth mentioning here that the delay circuit 140 of this embodiment responds to the operation signal SYS_PRES to extend the time period during which the startup signal P_SW is at a low voltage level, so that the rising edge of the startup signal P_SW lags behind the supply time point of the driving power PWR. . In this way, the user does not need to extend the pressing time of the start button PB (for example, more than 1.5 seconds), but only clicks the start button PB (for example, the pressing time is less than 1 second) to wake up the battery module 130 and electronic device 100.

Please refer to Figure 1 and Figure 2 at the same time. Figure 2 is a signal timing diagram based on Figure 1. In this embodiment, FIG. 2 shows the timing of the start signal P_SW, the timing of the control signal ALWON, the timing of the operation signal SYS_PRES, and the timing of the driving power PWR.

At time point t1, when the start button PB is clicked, the voltage level of the start signal P_SW begins to be pulled down to a low voltage level. The controller 110 is triggered to generate a high voltage level control signal ALWON. The battery control circuit 120 generates a high voltage level operating signal SYS_PRES. At time point t2, the high voltage level of the control signal ALWON is pulled down, so that the high voltage level of the operation signal SYS_PRES is also pulled down. In this embodiment, the high voltage level of the operation signal SYS_PRES is used to simulate that the battery module 130 is removed from the electronic device 100 . The low voltage level of the operation signal SYS_PRES is used to simulate that the battery module 130 is installed in the electronic device 100 . That is to say, at time point t2, the transition of the operation signal SYS_PRES will cause the battery module 130 to enter a situation in which the battery module 130 is removed from the electronic device 100 and then installed in the electronic device 100. Therefore, the battery module 130 is awakened at time point t2 and provides driving power PWR at time point t3. That is, time point t3 is the supply time point of driving power PWR.

In addition, the delay circuit 140 will respond to the operation signal SYS_PRES to extend the time period during which the enable signal P_SW is at the low voltage level, and change the waveform CV1 to the waveform CV2. As shown in waveform CV2, the time length of the low voltage level is substantially equal to the time length between time point t4 and time point t1. It should be noted that time point t4 is the starting time point of the rising edge of waveform CV2 and lags behind time point t3. That is to say, under the click operation of the start button PB, the delay circuit 140 extends the start-up effective time of the electronic device 100 (to the time length between time point t4 and time point t1) to trigger the controller 110, wake up The battery module 130 also allows the battery module 130 to provide driving power PWR.

Please refer to FIG. 1 and FIG. 3 at the same time. FIG. 3 is a method flow chart of a startup method according to an embodiment of the present invention. The startup method is suitable for the electronic device 100 . In this embodiment, the starting method includes steps S110 to S140. In step S110 , the electronic device 100 generates the control signal ALWON in response to the enable signal P_SW being pulled down to a low voltage level. In this embodiment, when the start button PB of the electronic device 100 is clicked, the voltage level of the start signal P_SW is pulled down to a low voltage level. Step S110 is executed by the controller 110, for example. In step S120, the electronic device 100 responds to the control signal ALWON to provide the operation signal SYS_PRES. Step S120 is executed by the battery control circuit 120, for example. In step S130 , the battery module 130 responds to the operation signal SYS_PRES and wakes up from the power saving state and enters the discharging state, thereby providing driving power PWR. In step S140 , the electronic device 100 responds to the operation signal SYS_PRES to extend the time period during which the startup signal P_SW is at the low voltage level, so that the rising edge of the startup signal P_SW lags behind the supply time point of the driving power PWR. Step S140 is performed by the delay circuit 140, for example.

The implementation details of the battery control circuit and the delay circuit will be described below in the first embodiment. Please refer to FIG. 1 , FIG. 4 and FIG. 5 at the same time. FIG. 4 is a schematic diagram of a battery control circuit according to a first embodiment of the present invention. FIG. 5 is a schematic diagram of a delay circuit according to the first embodiment of the present invention. In this embodiment, the battery control circuit 220 includes an AND gate AG, a control signal delay circuit 221 and a transition circuit 222. The first input terminal of the AND gate AG receives the reference voltage V1. The output terminal of the AND gate AG is used to provide the operating signal SYS_PRES. The control signal delay circuit 221 is coupled to the second input terminal of the AND gate AG. The control signal delay circuit 221 delays the control signal ALWON. The transition circuit 222 is coupled between the second input terminal of the AND gate AG and the output terminal of the AND gate AG. The transition circuit 222 pulls down the high voltage level of the second input terminal of the AND gate AG to a low voltage level at the transition time point. That is to say, the second input terminal of the AND gate AG will receive the delayed control signal ALWON. The high voltage level of the delayed control signal ALWON will be pulled down to the low voltage level at the transition time point. Therefore, the AND gate AG will pull down the high voltage level of the operation signal SYS_PRES to the low voltage level at the transition time point.

In this embodiment, the control signal delay circuit 221 includes resistors R11, R12 and a capacitor C11. The first terminal of the resistor R11 receives the control signal ALWON. The second terminal of the resistor R11 is coupled to the second input terminal of the AND gate AG. The resistor R12 is coupled between the second input terminal of the AND gate AG and the reference low voltage (eg, ground). The capacitor C11 is coupled between the second input terminal of the AND gate AG and the reference low voltage. The control signal delay circuit 221 provides the delayed control signal ALWON at the second input terminal of the AND gate AG.

In this embodiment, the transition circuit 222 includes resistors R15 and R16, a capacitor C13, a diode D and a transition transistor M1. The first terminal of the resistor R15 is coupled to the second input terminal of the AND gate AG. The first terminal of resistor R16 is coupled to the second terminal of resistor R15. Capacitor C13 is coupled between the second terminal of resistor R16 and the reference low voltage. The anode of the diode D is coupled to the output terminal of the AND gate AG, and the cathode of the diode D is coupled to the first terminal of the resistor R16. The first terminal of the transition transistor M1 is coupled to the second input terminal of the AND gate AG. The second terminal of the transition transistor M1 is coupled to the reference low voltage. The control terminal of the transition transistor M1 is coupled to the second terminal of the resistor R16. In this embodiment, diode D causes the output of AND gate AG to power resistor R16 and capacitor C13. Therefore, the switching transistor M1 is turned on to pull down the voltage value at the second input terminal of the AND gate AG. Next, the output of the AND gate AG is pulled down to a low voltage level. Therefore, the output of the AND gate AG will form a transient signal. In this embodiment, the diode D may be a Schottky diode.

In this embodiment, the delay circuit 240 includes a resistor R21, a capacitor C21 and a pull-down transistor M2. The first end of the resistor R21 is used to receive the operation signal SYS_PRES. Capacitor C21 is coupled between the second terminal of resistor R21 and the reference low voltage. The first terminal of the pull-down transistor M2 receives the enable signal P_SW. The second terminal of the pull-down transistor M2 is coupled to the low reference voltage. The control terminal of the pull-down transistor M2 is coupled to the second terminal of the resistor R21.

In this embodiment, the AND gate AG receives the power-saving state maintaining voltage SB as a voltage source. The power saving state maintaining voltage SB is the basic power used by the electronic device 100 to maintain status information of the electronic device 100 in the sleep state or shutdown state. In other words, the power saving state maintaining voltage SB is an independent power that replaces the conventional small battery. When the electronic device 100 is in the power saving state, the power saving state maintaining voltage SB is also maintained. Capacitor C12 is coupled between the power-saving state maintaining voltage SB and the reference low voltage. In this embodiment, the reference voltage V1 is a high voltage level. Therefore, when the delayed control signal ALWON is received, the output terminal of the AND gate AG will provide the high-voltage level operating signal SYS_PRES. The high voltage level of the operation signal SYS_PRES is used to simulate the removal of the battery module 130 from the electronic device 100 .

In addition, the pull-down transistor M2 of the delay circuit 240 will pull down the voltage level of the enable signal P_SW in response to the high-voltage level operation signal SYS_PRES. The time period during which the enable signal P_SW is at the low voltage level will be extended.

In this embodiment, when receiving the high-voltage level control signal ALWON, the transition circuit 222 charges the capacitor C13 through the high-voltage level control signal ALWON. The operation signal SYS_PRES output by the AND gate AG will start to charge the capacitor C21. The design of the control signal delay circuit 221, resistors R15, R16 and capacitor C13 will determine the timing of charging the capacitor C13 by the transition circuit 222. Therefore, the time point when the transition transistor M1 is turned on can be set at the transition time point (time point t2 shown in FIG. 2 ). When the transition transistor M1 is turned on at the transition time point, the voltage level of the second input terminal of the AND gate AG will be pulled down. Therefore, the delayed control signal ALWON located at the second input terminal of the AND gate AG will be transitioned from a high voltage level to a low voltage level (the control signal ALWON provided by the controller 110 is still at a high voltage level) . The operation signal SYS_PRES will be transitioned from a high voltage level to a low voltage level. The low voltage level of the operation signal SYS_PRES is used to simulate that the battery module 130 is installed in the electronic device 100 . Therefore, the battery module 130 will be awakened at the transition time point.

It should be mentioned here that the delay of time point t2 can further extend the time period during which the enable signal P_SW is at a low voltage level.

The delay circuit 240 can delay the conduction time of the pull-down transistor M2 through the resistor R21 and the capacitor C21 to further extend the time period during which the enable signal P_SW is at a low voltage level. Therefore, the rising edge time point of the start signal P_SW will be delayed after the supply time point of the driving power PWR.

In this embodiment, the battery control circuit 220 further includes a voltage dividing circuit 223 . The voltage dividing circuit 223 is coupled to the first input terminal of the AND gate AG. The voltage dividing circuit 223 performs a voltage dividing operation on the voltage value of the power-saving state maintaining voltage SB to provide a reference voltage V1. The voltage dividing circuit 223 includes resistors R13 and R14. The resistor R13 is coupled between the power-saving state maintaining voltage SB and the first input terminal of the AND gate AG. The resistor R14 is coupled between the first input terminal of the AND gate AG and the reference low voltage. The voltage dividing circuit 223 divides the power saving state maintaining voltage SB according to the resistance values of the resistors R13 and R14 to provide the reference voltage V1.

In this embodiment, the transition transistor M1 and the pull-down transistor M2 are respectively implemented by any form of N-type metal oxide semiconductor field effect transistor (MOSFET). The transition transistor M1 and the pull-down transistor M2 of the present invention can be implemented by any form of N-type transistor, and are not limited to this embodiment.

The implementation details of the battery control circuit will be described below in a second embodiment. Please refer to FIG. 6 , which is a schematic diagram of a battery control circuit according to a second embodiment of the present invention. In this embodiment, the battery control circuit 320 includes an AND gate AG, a control signal delay circuit 321, a transition circuit 322, a voltage dividing circuit 323 and a disabling circuit 324. The implementation details of the AND gate AG, the control signal delay circuit 321, the transition circuit 322 and the voltage dividing circuit 323 in this embodiment can be sufficiently taught from the embodiment associated with FIG. 4 and will not be repeated here. In this embodiment, the disabling circuit 324 is coupled to the second input terminal of the AND gate AG. After the driving power PWR is provided, the disabling circuit 324 pulls down and gates the voltage level of the second input terminal AG to disable the battery control circuit 320 . In this embodiment, the disabling circuit 324 detects the voltage value of the reference power PWR'. The reference power PWR' is generated based on the driving power PWR. That is to say, the reference power PWR' is generated only after the electronic device is driven by the driving power PWR.

When the disabling circuit 324 detects the reference power PWR' with a low voltage value, it means that the electronic device has not been driven by the driving power PWR. Therefore, the disabling circuit 324 does not pull down the voltage level of the second input terminal of the AND gate AG. On the other hand, when the disabling circuit 324 detects the high voltage value of the reference power PWR', it means that the battery module has been awakened and the electronic device has been driven by the driving power PWR. It can be seen from this that when the electronic device has been driven, the battery module does not need to be awakened again, and the time period during which the startup signal P_SW is at a low voltage level does not need to be extended. Therefore, the disabling circuit 324 will continue to pull down and gate the voltage level of the second input terminal AG, thereby disabling the transition of the operation signal SYS_PRES.

In this embodiment, the disabling circuit 324 includes resistors R18 and R19 and a transistor M3. A first terminal of resistor R18 receives reference power PWR'. The resistor R19 is coupled between the second terminal of the resistor R18 and the reference low voltage. The first terminal of the transistor M3 is coupled to the second input terminal of the AND gate AG. The second terminal of the transistor M3 is coupled to the reference low voltage. The control terminal of transistor M3 is coupled to the second terminal of resistor R18. The disabling circuit 324 divides the voltage value of the reference power PWR' through the resistors R18 and R19, thereby obtaining the divided voltage. Transistor M3 will be turned on or off according to the divided voltage.

In this embodiment, the transistor M3 is implemented by any form of N-type MOSFET. The transistor M3 of the present invention can be implemented by any form of N-type transistor, and is not limited to this embodiment.

In this embodiment, the battery control circuit 320 also includes a resistor R17. The resistor R17 is coupled between the output terminal of the AND gate AG and the reference low voltage.

The implementation details of the delay circuit will be described below in a third embodiment. FIG. 7 is a schematic diagram of a delay circuit and an operation control circuit according to an embodiment of the present invention. In this embodiment, the delay circuit 340 includes a resistor R21, a capacitor C21 and a pull-down transistor M2. The implementation details of the resistor R21, the capacitor C21, and the pull-down transistor M2 can be sufficiently taught from the embodiment associated with FIG. 5, so they are not repeated here. In this embodiment, the electronic device includes an operation control circuit 350 . The operation control circuit 350 receives the flip-up power-on setting signal SLID, and responds to the flip-up power-on setting signal SLID to allow the conduction operation of the pull-down transistor M2.

In this embodiment, the operation control circuit 350 includes a resistor R22 and transistors M4 and M5. The first terminal of the transistor M4 is coupled to the control terminal of the pull-down transistor M2. The second terminal of the transistor M4 is coupled to the low reference voltage. The control terminal of the transistor M4 is coupled to the first terminal of the transistor M5. The second terminal of the transistor M5 is coupled to the reference low voltage. The control terminal of transistor M4 receives the flip-up boot setting signal SLID. The first terminal of the resistor R22 receives the power saving state maintaining voltage SB. The second terminal of the resistor R22 is coupled to the control terminal of the transistor M4.

In this embodiment, the electronic device may be a notebook computer. If the electronic device is set to be turned on when the cover is opened, the voltage of the cover-opening setting signal SLID must be a high voltage level. Transistor M5 is turned on to pull down the voltage level at the control terminal of transistor M4, thereby causing transistor M4 to be turned off. Therefore, the turn-on operation of the pull-down transistor M2 is allowed. That is to say, the delay circuit 340 will respond to the flip-up boot setting signal SLID and the operation signal SYS_PRES to extend the time the startup signal P_SW is at the low voltage level, thereby delaying the time point of the rising edge of the startup signal P_SW. On the other hand, if the electronic device is set not to be powered on when the cover is opened, the voltage of the cover-opening setting signal SLID must be a low voltage level. Transistor M5 is turned off and transistor M4 is turned on. Therefore, the pull-down transistor M2 will continue to be turned off, thereby not delaying the rising edge of the enable signal P_SW.

In this embodiment, the transistors M4 and M5 are respectively implemented by any form of N-type MOSFET. The transistors M4 and M5 of the present invention can be implemented by any form of N-type transistor, and are not limited to this embodiment.

In summary, the electronic device responds to the activation signal generated by the click operation to generate the control signal and provides the operation signal accordingly. Based on the transition of the operating signal, the battery module is awakened to provide driving power. In addition, the electronic device also responds to the operation signal to extend the time the start signal is at a low voltage level, so that the rising edge of the start signal lags behind the supply time point of the driving power. Therefore, the user does not need to extend the pressing time of the start button. In this way, users can wake up the battery module and electronic device with just a single click. Such operations will affect the user's operating experience.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100: Electronic devices 110:Controller 120, 220, 320: battery control circuit 130:Battery module 140, 240, 340: Delay circuit 221: Control signal delay circuit 222: Transition circuit 223, 323: Voltage dividing circuit 324: Disabling circuit 350: Operation control circuit AG: and gate ALWON: control signal C11, C12, C13, C21, C22: capacitor CV1, CV2: waveform D: Diode M1: transition transistor M2: pull-down transistor M3, M4, M5: transistor P_SW: start signal PB: start button PWR: driving power PWR’: reference power R11, R12, R13, R14, R15, R16, R17, R18, R19, R21, R22: resistors S110, S120, S130, S140: steps SB: power saving state maintenance voltage SYS_PRES: operation signal SLID: Lift cover boot setting signal t: time t1, t2, t3, t4: time points V1: reference voltage

FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present invention. FIG. 2 is a signal timing diagram based on FIG. 1 . FIG. 3 is a method flow chart of a startup method according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a battery control circuit according to the first embodiment of the present invention. FIG. 5 is a schematic diagram of a delay circuit according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of a battery control circuit according to a second embodiment of the present invention. FIG. 7 is a schematic diagram of a delay circuit and an operation control circuit according to an embodiment of the present invention.

100: Electronic devices 110:Controller 120:Battery control circuit 130:Battery module 140: Delay circuit ALWON: control signal P_SW: start signal PB: start button PWR: driving power SYS_PRES: operation signal

Claims (12)

An electronic device that is awakened by clicking when a battery module of the electronic device is in a power-saving state, including: a start button that, when clicked, pulls down the voltage level of a start signal; a controller , configured to generate a control signal in response to the activation signal being pulled down to a low voltage level; a battery control circuit coupled to the controller and the battery module, configured to respond to the control signal to provide An operation signal causes the battery module to wake up from the power saving state and enter a discharge state in response to the operation signal to provide a driving power for driving the electronic device; and a delay circuit coupled to the The battery control circuit is configured to respond to the operation signal to extend the time the startup signal is at a low voltage level, so that the rising edge time point of the startup signal lags behind the supply time point of the driving power, wherein the battery control circuit The circuit includes: an AND gate, the first input end of the AND gate receives a reference voltage, and the output end of the AND gate is used to provide the operation signal; a control signal delay circuit coupled to the second input end of the AND gate , configured to delay the control signal and provide the delayed control signal to the second input terminal of the AND gate; and a transition circuit coupled between the second input terminal of the AND gate and the output of the AND gate between terminals, configured to pull down the high voltage level of the second input terminal of the AND gate to a low voltage level at a transition time point, The AND gate pulls down the high voltage level of the operation signal to a low voltage level at the transition time point. The electronic device of claim 1, wherein: the high voltage level of the operation signal is used to simulate that the battery module is removed from the electronic device, and the low voltage level of the operation signal is used to simulate the battery module. The group is loaded onto the electronic device. The electronic device of claim 1, wherein the transition circuit includes: a first resistor, a first end of the first resistor coupled to the second input end of the AND gate; a second resistor, The first terminal of the second resistor is coupled to the second terminal of the first resistor; a capacitor, the capacitor is coupled between the second terminal of the second resistor and a reference low voltage; a diode body, the anode of the diode is coupled to the output end of the AND gate, the cathode of the diode is coupled to the first end of the second resistor; and a transition transistor, the transition transistor The first terminal is coupled to the second input terminal of the AND gate, the second terminal of the transition transistor is coupled to the reference low voltage, and the control terminal of the transition transistor is coupled to the third terminal of the second resistor. Two ends. The electronic device of claim 1, wherein the battery control circuit further includes: a voltage dividing circuit coupled to the first input end of the AND gate and configured to control a power saving circuit. The voltage value of the electrical state maintenance voltage is subjected to a voltage dividing operation to provide the reference voltage. The electronic device of claim 1, wherein the battery control circuit further includes: a disabling circuit coupled to the second input end of the AND gate and configured to pull down the AND gate after the driving power is provided. The voltage level of the second input terminal is used to disable the battery control circuit. The electronic device of claim 1, wherein the delay circuit includes: a resistor, a first end of the resistor is used to receive the operation signal; a capacitor, the capacitor is coupled between the second end of the resistor and between a reference low voltage; and a pull-down transistor. The first terminal of the pull-down transistor receives the start signal. The second terminal of the pull-down transistor is coupled to the reference low voltage. The control terminal of the pull-down transistor is coupled to Connect to the second end of the resistor. The electronic device of claim 6, further comprising: an operation control circuit configured to receive a flip-on setting signal and respond to the high voltage level of the flip-up setting signal to allow the pull-down transistor to In the conduction operation, when the electronic device is set to be turned on when the cover is turned on, the voltage level of the cover turn-on setting signal is a high voltage level, and when the electronic device is set to be turned on and is not turned on, The voltage level of the cover boot setting signal is a low voltage level. A startup method for an electronic device, including: A control signal is generated by a battery control circuit in response to a start signal that is pulled down to a low voltage level, wherein when a start button is clicked, the voltage level of the start signal is pulled down; in response to the control signal To provide an operation signal; to cause a battery module of the electronic device to wake up from a power saving state and enter a discharge state in response to the operation signal, so as to provide a driving power for driving the electronic device; and to react to The operation signal is used to extend the length of time the start signal is at a low voltage level, so that the rising edge of the start signal lags behind the supply time point of the driving power. The battery control circuit includes: a AND gate, and a third gate of the AND gate. An input terminal receives a reference voltage, and the output terminal of the AND gate is used to provide the operation signal; a control signal delay circuit, coupled to the second input terminal of the AND gate, is configured to delay the control signal and provide the controlled signal. Delaying the control signal to the second input terminal of the AND gate; and a transition circuit coupled between the second input terminal of the AND gate and the output terminal of the AND gate, configured for a transition time point to pull down the high voltage level of the second input terminal of the AND gate to a low voltage level, wherein the AND gate pulls down the high voltage level of the operation signal to a low voltage level at the transition time point. The startup method as described in claim 8, wherein: the high voltage level of the operation signal is used to simulate the power of the battery module from the electronic device. is removed, and the low voltage level of the operation signal is used to simulate that the battery module is installed in the electronic device. The startup method as described in claim 8, wherein the step of providing the operation signal in response to the control signal includes: delaying the control signal; pulling the high voltage level of the delayed control signal to low at a transition time point voltage level; and pulling down the high voltage level of the operation signal to the low voltage level at the transition time point. The starting method as described in claim 8 further includes: after the driving power is provided, continuously pulling down the voltage level of the operation signal to disable the transition of the operation signal. According to the startup method of claim 8, the step of extending the time period during which the startup signal is at a low voltage level in response to the operation signal includes: receiving a flip boot setting signal, wherein when the electronic device is set to flip When the electronic device is turned on, the voltage level of the flip-up boot setting signal is a high voltage level. When the electronic device is set to flip the lid and is not turned on, the voltage level of the flip-up startup setting signal is low voltage. level; and responding to the high voltage level of the flip-open setting signal and the operation signal to extend the time period during which the startup signal is at the low voltage level.

Images