CN220173096U - Electronic equipment and power supply enabling loop - Google Patents
Electronic equipment and power supply enabling loop Download PDFInfo
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- CN220173096U CN220173096U CN202321655289.1U CN202321655289U CN220173096U CN 220173096 U CN220173096 U CN 220173096U CN 202321655289 U CN202321655289 U CN 202321655289U CN 220173096 U CN220173096 U CN 220173096U
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Abstract
The utility model provides electronic equipment and a power supply enabling loop, which are used for restarting the electronic equipment in a dormant state after power failure, wherein the delay loop is used for delaying until a power supply enabling signal appears when receiving a first power supply, so that the first power supply can enable a power supply chip, and the problem that the electronic equipment cannot restart after being forced to be shut down in an energy-saving mode is solved.
Description
Technical Field
The present utility model relates to the field of electronic power, and in particular, to an electronic device and a power supply enabling circuit.
Background
In the intel low power platform, a single triode is used in the prior art to realize the control of the EN signal (as shown in fig. 1), under the condition that the 5vsb_ctrl# signal is briefly pulled high when the system is in the S5 state (i.e., the off state), and then is always in the low state, so that the EN is in the high state to generate 3 and 5VSB voltages. If the system enters the power saving mode (EUP mode), the 5vsb_ctrl# signal is pulled high, high. After forced shutdown in the state of the energy-saving mode, a phenomenon that restarting is impossible occurs.
In view of this, the present utility model has been proposed.
Disclosure of Invention
The utility model discloses electronic equipment and a power supply enabling loop, and aims to solve the problem that the electronic equipment cannot be restarted after being forced to be shut down in an energy-saving mode.
A first embodiment of the present utility model provides a power supply enable loop comprising: a delay loop, a signal output loop, a signal receiving loop, and a switching loop;
the input end of the delay loop is used for being connected with a first power supply, the output end of the delay loop is electrically connected with the control end of the switch loop, the first input end of the switch loop is electrically connected with the first power supply, the second input end of the switch loop is electrically connected with a second power supply, the output end of the switch loop is electrically connected with the enabling end of the power supply chip through the signal output loop, the first input end of the signal receiving loop is used for receiving a power supply enabling signal, the second input end of the signal receiving loop is electrically connected with the first power supply, and the output end of the signal receiving loop is electrically connected with the output end of the switch loop;
the delay loop is configured to delay until the power supply enabling signal appears when a first power supply is received, and then control the switch loop to be conducted, so that the first power supply can enable the power supply chip.
Preferably, the delay loop comprises: a first resistor and a first capacitor;
the first power supply is electrically connected with the control end of the switch loop through the first resistor, and the first resistor is grounded through the first capacitor.
Preferably, the switching circuit includes: the second resistor, the third resistor, the fourth resistor, the first MOS tube and the second MOS tube;
the output end of the delay loop is electrically connected with the G electrode of the first MOS tube, the S electrode of the first MOS tube is grounded, the second power supply is electrically connected with the D electrode of the first MOS tube through the second resistor, the D electrode of the first MOS tube is grounded through the third resistor, the D electrode of the first MOS tube is electrically connected with the G electrode of the second MOS tube, the first power supply is electrically connected with the D electrode of the second MOS tube through the fourth resistor, the S electrode of the second MOS tube is grounded, and the D electrode of the second MOS tube is electrically connected with the enabling end of the power supply chip through the signal output loop.
Preferably, the signal receiving circuit includes: the fifth resistor, the sixth resistor and the third MOS tube;
the first power supply is electrically connected with the first end of the sixth resistor through the fifth resistor, the sending end of the power supply enabling signal is electrically connected with the first end of the sixth resistor, the second end of the sixth resistor is electrically connected with the G electrode of the third MOS tube, the S electrode of the third MOS tube is grounded, and the D electrode of the third MOS tube is electrically connected with the D electrode of the second MOS tube.
Preferably, the power supply enable signal can pull the first power supply low, so that the third MOS transistor is turned off when the power supply enable signal occurs.
A second embodiment of the present utility model provides an electronic apparatus including: the power supply system comprises a first power supply, a second power supply, a power supply chip and a power supply enabling loop, wherein the first power supply is electrically connected with an input end of the delay loop, a second input end of the signal receiving loop and a first input end of the switching loop, the second power supply is electrically connected with a second input end of the switching loop, and an output end of the switching loop is electrically connected with an enabling end of the power supply chip through the signal output loop.
Preferably, the power supply chip is of a model RT6576D.
Preferably, the second power supply is capable of being powered up before the first power supply when the electronic device is powered up.
According to the electronic equipment and the power supply enabling loop provided by the utility model, when the electronic equipment in the dormant state is restarted after power is off, the delay loop delays until the power supply enabling signal appears when receiving the first power supply, so that the first power supply can enable the power supply chip, and the problem that the electronic equipment cannot be restarted after being forced to be turned off in an energy-saving mode is solved.
Drawings
FIG. 1 is a schematic diagram of a prior art power supply enabling circuit;
fig. 2 is a schematic diagram of a power supply enabling circuit according to the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model. Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model.
Specific embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.
The utility model discloses electronic equipment and a power supply enabling loop, and aims to solve the problem that the electronic equipment cannot be restarted after being forced to be shut down in an energy-saving mode.
Referring to fig. 2, a first embodiment of the present utility model provides a power supply enabling loop, including: a delay circuit 1, a signal output circuit 3, a signal receiving circuit 4, and a switching circuit 2;
the input end of the delay loop is used for being connected with a first power supply, the output end of the delay loop is electrically connected with the control end of the switch loop 2, the first input end of the switch loop 2 is electrically connected with the first power supply, the second input end of the switch loop 2 is electrically connected with a second power supply, the output end of the switch loop 2 is electrically connected with the enabling end of the power supply chip through the signal output loop 3, the first input end of the signal receiving loop 4 is used for receiving a power supply enabling signal, the second input end of the signal receiving loop 4 is electrically connected with the first power supply, and the output end of the signal receiving loop 4 is electrically connected with the output end of the switch loop 2;
the delay loop 1 is configured to control the switch loop 2 to be turned on after the power supply enable signal appears when a first power supply is received, so that the first power supply can enable the power supply chip, wherein the timing sequence of the second power supply VDC is greater than the timing sequence of the first power supply 3vsb_io, and the timing sequence of the first power supply is greater than the timing sequence of the power supply enable signal 5vsb_ctrl.
The inventors found that: after the special condition is powered off in the working environment, the machine body is powered off due to the power off, the standby energy is accessed, and the automatic restarting can be realized within 10 ms. However, if the machine body is in the energy-saving mode, when the standby energy is switched by power failure, the machine body has a high probability of being incapable of realizing automatic restarting. In detail, please refer to fig. 1, in which the 5vsb_ctrl signal is high, the 3vsb_io signal is pulled low through the MOS transistor, so that the EN of the 3/5V power chip is low, and there is no 3/5V power, and although the 5vsb_ctrl signal will become low, the restart signal will not restart after missing, and the power can only be turned off, and the power can be restarted.
In this embodiment, after the electronic device in the sleep state is restarted after being powered off, the first power supply at the first input end of the switch loop 2 is grounded by the first power supply, so that the power supply chip cannot be enabled by the first power supply at the later time, then the power supply enabling signal appears, the first power supply at the second input end of the signal receiving loop 4 is pulled down, then the first power supply of the delay loop reaches the control end of the switch loop 2, so that the second power supply is grounded, and at this time, the first power supply at the first input end of the switch loop 2 enables the power supply chip, thereby solving the problem that the electronic device cannot be restarted after being forced to be powered off in the energy-saving mode.
In one possible embodiment of the utility model, the delay loop 1 comprises: a first resistor R1 and a first capacitor C1;
the first power supply is electrically connected with the control end of the switch loop 2 through the first resistor R1, and the first resistor R1 is grounded through the first capacitor C1.
It should be noted that, when the first power supply occurs, the first resistor R1 and the first capacitor C1 may delay the occurrence of the first power supply to the control terminal of the switching loop 2 until the power supply enable signal occurs, where the delay time may be set based on the parameters of the first resistor R1 and the first capacitor C1.
In one possible embodiment of the utility model, the switching circuit 2 comprises: the second resistor R2, the third resistor R3, the fourth resistor R4, the first MOS tube Q1 and the second MOS tube Q2;
the output end of the delay loop is electrically connected with the G electrode of the first MOS tube Q1, the S electrode of the first MOS tube Q1 is grounded, the second power supply is electrically connected with the D electrode of the first MOS tube Q1 through the second resistor R2, the D electrode of the first MOS tube Q1 is grounded through the third resistor R3, the D electrode of the first MOS tube Q1 is electrically connected with the G electrode of the second MOS tube Q2, the first power supply is electrically connected with the D electrode of the second MOS tube Q2 through the fourth resistor R4, the S electrode of the second MOS tube Q2 is grounded, and the D electrode of the second MOS tube Q2 is electrically connected with the enabling end of the power supply chip through the signal output loop 3.
It should be noted that, in this embodiment, when the restart signal of the electronic device occurs, the timing sequence of the second power supply is before the first power supply, specifically, when the restart signal occurs, the second power supply may open the second MOS transistor Q2, after the first power supply occurs and after the delay of the delay circuit, the first MOS transistor Q1 is opened, at this time, the second power supply is grounded, the second MOS transistor Q2 is turned off, at this time, the first power supply above the second MOS transistor Q2 is no longer grounded.
In one possible embodiment of the utility model, the signal receiving circuit 4 comprises: a fifth resistor R5, a sixth resistor R6 and a third MOS transistor Q3;
the first power supply is electrically connected with the first end of the sixth resistor R6 through the fifth resistor R5, the transmitting end of the power supply enabling signal is electrically connected with the first end of the sixth resistor R6, the second end of the sixth resistor R6 is electrically connected with the G pole of the third MOS transistor Q3, the S pole of the third MOS transistor Q3 is grounded, and the D pole of the third MOS transistor Q3 is electrically connected with the D pole of the second MOS transistor Q2.
It should be noted that, in this embodiment, the power supply enable signal appears after the first power supply, which can pull the first power supply low, so that the third MOS transistor Q3 is turned off when the power supply enable signal appears, at this time, the second MOS transistor Q2 and the third MOS transistor Q3 are both turned off, and the first power supply is output to the power supply chip, so that the power supply chip can be turned on.
The operation of the present utility model is briefly described below, please refer to fig. 2:
after the power-off restarting, VDC is the first, 3VSB_IO and 5VSB_CTRL appear before and after (interval is very small, opportunity appears at the same time), 3VSB_IO is high level, 5VSB_CTRL is low, the second MOS transistor Q2 is always opened by the second power VDC to pull down the uppermost first power supply 3VSB_IO, the lower 5VSB_CTRL and 3VSB_IO keep a smooth switch from on to off through control, at the moment, the left 3VSB_IO can only pull down VDC by delaying to open Q1, and Q2 is closed, at the moment, both Q3 and Q2 are closed, so that EN of the 3/5V chip is high, and 3/5V power is obtained.
A second embodiment of the present utility model provides an electronic apparatus including: the power supply enabling circuit comprises a first power supply, a second power supply, a power supply chip and any one of the above, wherein the first power supply is electrically connected with the input end of the delay circuit, the second input end of the signal receiving circuit 4 and the first input end of the switch circuit 2, the second power supply is electrically connected with the second input end of the switch circuit 2, and the output end of the switch circuit 2 is electrically connected with the enabling end of the power supply chip through the signal output circuit 3.
In one possible embodiment of the present utility model, the power supply chip is of the model RT6576D.
In one possible embodiment of the utility model, the second power supply is capable of powering up before the first power supply when the electronic device is powered up.
Based on the electronic equipment and the power supply enabling loop provided by the utility model, when the electronic equipment in the dormant state is restarted after power failure, the delay loop 1 delays until the power supply enabling signal appears when receiving the first power supply, and then the switch loop 2 is controlled to be conducted, so that the first power supply can enable the power supply chip, and the problem that the electronic equipment cannot be restarted after being forced to be powered off in an energy-saving mode is solved.
The above is only a preferred embodiment of the present utility model, and the protection scope of the present utility model is not limited to the above examples, and all technical solutions belonging to the concept of the present utility model belong to the protection scope of the present utility model.
Claims (8)
1. A power supply enabling loop, comprising: a delay loop, a signal output loop, a signal receiving loop, and a switching loop;
the input end of the delay loop is used for being connected with a first power supply, the output end of the delay loop is electrically connected with the control end of the switch loop, the first input end of the switch loop is electrically connected with the first power supply, the second input end of the switch loop is electrically connected with a second power supply, the output end of the switch loop is electrically connected with the enabling end of the power supply chip through the signal output loop, the first input end of the signal receiving loop is used for receiving a power supply enabling signal, the second input end of the signal receiving loop is electrically connected with the first power supply, and the output end of the signal receiving loop is electrically connected with the output end of the switch loop;
the delay loop is configured to delay until the power supply enabling signal appears when a first power supply is received, and then control the switch loop to be conducted, so that the first power supply can enable the power supply chip.
2. A power enable loop according to claim 1, wherein said delay loop comprises: a first resistor and a first capacitor;
the first power supply is electrically connected with the control end of the switch loop through the first resistor, and the first resistor is grounded through the first capacitor.
3. A power supply enabling circuit according to claim 1, characterized in that said switching circuit comprises: the second resistor, the third resistor, the fourth resistor, the first MOS tube and the second MOS tube;
the output end of the delay loop is electrically connected with the G electrode of the first MOS tube, the S electrode of the first MOS tube is grounded, the second power supply is electrically connected with the D electrode of the first MOS tube through the second resistor, the D electrode of the first MOS tube is grounded through the third resistor, the D electrode of the first MOS tube is electrically connected with the G electrode of the second MOS tube, the first power supply is electrically connected with the D electrode of the second MOS tube through the fourth resistor, the S electrode of the second MOS tube is grounded, and the D electrode of the second MOS tube is electrically connected with the enabling end of the power supply chip through the signal output loop.
4. A power enabling circuit according to claim 3 wherein said signal receiving circuit comprises: the fifth resistor, the sixth resistor and the third MOS tube;
the first power supply is electrically connected with the first end of the sixth resistor through the fifth resistor, the sending end of the power supply enabling signal is electrically connected with the first end of the sixth resistor, the second end of the sixth resistor is electrically connected with the G electrode of the third MOS tube, the S electrode of the third MOS tube is grounded, and the D electrode of the third MOS tube is electrically connected with the D electrode of the second MOS tube.
5. The power enable circuit of claim 4, wherein the power enable signal is capable of pulling the first power supply low such that the third MOS transistor is turned off when the power enable signal is present.
6. An electronic device, comprising: a first power supply, a second power supply, a power supply chip and a power supply enabling circuit according to any one of claims 1 to 5, wherein the first power supply is electrically connected with the input end of the delay circuit, the second input end of the signal receiving circuit and the first input end of the switch circuit, the second power supply is electrically connected with the second input end of the switch circuit, and the output end of the switch circuit is electrically connected with the enabling end of the power supply chip through the signal output circuit.
7. An electronic device as claimed in claim 6, wherein the power supply chip is of the type RT6576D.
8. An electronic device as recited in claim 6, wherein the second power source is capable of powering up before the first power source when the electronic device is powered up.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321655289.1U CN220173096U (en) | 2023-06-27 | 2023-06-27 | Electronic equipment and power supply enabling loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321655289.1U CN220173096U (en) | 2023-06-27 | 2023-06-27 | Electronic equipment and power supply enabling loop |
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| Publication Number | Publication Date |
|---|---|
| CN220173096U true CN220173096U (en) | 2023-12-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202321655289.1U Active CN220173096U (en) | 2023-06-27 | 2023-06-27 | Electronic equipment and power supply enabling loop |
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| CN (1) | CN220173096U (en) |
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- 2023-06-27 CN CN202321655289.1U patent/CN220173096U/en active Active
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