TWI820994B - Instruction compression method, instruction decompression method and process compression method - Google Patents

Abstract

An instruction compression method, an instruction decompression method, and a process compression method are provided. The process compression method is used for compressing a process that includes a jump instruction. The process compression method includes the following steps: dividing the process into multiple blocks according to a position of the jump instruction in the process and a destination of the jump instruction; recording a jump relationship between these blocks; performing instruction compression on these blocks; updating a jump address of the jump instruction according to the jump relationship; determining multiple groups according to the sizes of the blocks and the jump relationship; and determining whether the jump instruction is a first type jump instruction or a second type jump instruction according to the relationship between the jump instruction and the groups.

Description

Instruction compression method, instruction decompression method and process compression method

The present invention relates to instruction compression and instruction decompression, and in particular to instruction compression and instruction decompression related to jump instructions (also known as branch instructions).

Generally speaking, a process (eg, image processing process, startup process, etc.) usually contains at least one jump instruction. However, the existing platform cannot turn on variable-length instruction compression at the same time when processing jump logic, resulting in the instruction register requiring larger space, the number of long jump instructions increasing, and the flow of processes increasing. Execution efficiency decreases. Therefore, an instruction compression method, an instruction decompression method and a process compression method are needed to reduce the space required for the instruction register and reduce the number of long jump instructions.

In view of the deficiencies of the prior art, one purpose of the present invention is to provide an instruction compression method, an instruction decompression method and a process compression method to improve the deficiencies of the prior art.

An embodiment of the present invention provides an instruction decompression method, which is applied to a hardware circuit. The hardware circuit decompresses an instruction and executes the instruction. The instruction includes a header, and the header includes A reference value. The method includes: when the reference value of the instruction is a default value, reading a first parameter of the instruction to obtain a number of different parameters; and, using a plurality of second parameters of the instruction. The parameters set a plurality of corresponding parameters of the hardware circuit, and the number of the second parameters is equal to the number of the different parameters.

Another embodiment of the present invention provides an instruction compression method for compressing an instruction to generate a compressed instruction. The instruction includes a header and a plurality of parameters. The header includes a reference value. The method includes: comparing The instruction is compared with a previous instruction to find a plurality of different parameters in the instruction that are different from the previous instruction; the reference value of the compressed instruction is set to a default value; the compressed instruction is A target parameter of is set to the number of the different parameters; and other parameters of the compressed instruction are set to the different parameters.

Another embodiment of the present invention provides a process compression method for compressing a process. The process includes a jump instruction. The method includes: according to a position of the jump instruction in the process and a destination of the jump instruction, Divide the process into a plurality of blocks; record a jump relationship between the blocks; perform instruction compression on the blocks; recalculate a jump address of the jump instruction based on the jump relationship; based on the blocks The size of the jump instruction and the jump relationship determine a plurality of groups; and the jump instruction is determined to be a first type of jump instruction or a second type of jump instruction based on the relationship between the jump instruction and the groups.

The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art. Therefore, compared with the prior art, the present invention can reduce the space required for the instruction register and/or reduce the number of long jump instructions. .

The features, implementation and effects of the present invention are described in detail below with reference to the drawings and examples.

100:Intelligent processor

110:Decoder

112:Memory

114: Instruction prefetch circuit

116: Instruction distribution circuit

118:Jump logic circuit

120: Direct memory access (DMA)

130:Vector circuit

140:Convolution circuit

122,132,142: Instruction decompression circuit

124,134,144: Calculation circuit

310:Process

INST1~INST15,INST_k-1,INST_k,INST_y: instructions

320: Jump relationship between blocks

BB: block boundary

BLK1, BLK2, BLK3, BLK4: blocks

INST_k',INST_z: compressed instructions

HD: header

InstFlag: flag

HDLen: reference value

P1,P2,P3,P4,P5,Pn,P1',P2',P3',P4',P5': parameters

Nd: number of different parameters

SR: threshold

GB: group boundary

GRP1, GRP2, GRP3: group

INST_n: jump instruction

REGP: register group

REG1, REG2, REG3, REG4, REG5: temporary register

210,S220,S230,S240,S250,S260,S510,S520,S530,S540,S550,S610,S620,S630,S640,S650,S660,S670,S680,S810,S820,S830,S840,S850,S8 60, step

Figure 1 is a functional block diagram of an embodiment of an intelligent processor of the present invention; Figure 2 is a flow chart of an embodiment of a process compression method of the present invention; Figure 3 shows a process containing multiple instructions and the blocks of the process The jump relationship between blocks; Figure 4 is a schematic diagram of the jump relationship between blocks; Figure 5 is the details of an embodiment of step S210 in Figure 2; Figure 6 is a flow chart of an embodiment of the instruction compression method of the present invention; Figure 7 is a schematic diagram of the instruction structure before compression and the instruction structure after compression; Figures 8 and 9 are details of an embodiment of step S250 in Figure 2; Figures 10A and 10B are the present invention's division of multiple blocks of the process into A schematic diagram of an embodiment of multiple groups; Figure 11 is a detail of an embodiment of step S260 in Figure 2; Figure 12 is a schematic diagram of another embodiment of dividing groups according to the present invention; Figure 13 is an instruction decompression of the present invention A flow chart of an embodiment of a method; Figure 14 is a schematic diagram of the hardware circuit of the present invention executing uncompressed instructions; and Figure 15 is a schematic diagram of the hardware circuit of the present invention executing compressed instructions.

The technical terms used in the following description refer to the idioms in the technical field. If some terms are explained or defined in this specification, the explanation or definition of these terms shall prevail.

The disclosure of the present invention includes an instruction compression method, an instruction decompression method and a process compression method. Since some components included in the smart processor of the present invention may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention. . In addition, part or all of the processes of the command compression method, command decompression method and process compression method of the present invention may be in the form of software and/or firmware.

Figure 1 is a functional block diagram of an embodiment of an intelligent processor (Intelligent Processing Unit, IPU) of the present invention. The intelligent processor 100 includes a decoder 110, a direct memory access (DMA) 120, a vector circuit 130 and a convolution circuit 140. Direct memory access 120, vector circuit 130 and convolution circuit 140 each include instruction decompression circuits 122, 132, 142 and calculation circuits 124, 134, 144. Instruction decompression circuits 122, 132 and 142 are used to decompress instructions (the details of the decompression instructions will be described later in conjunction with Figure 13), and calculation circuits 124, 134 and 144 execute direct memory access 120 and vector circuit 130 respectively. and the main functions of the convolution circuit 140. Since those skilled in the art know the main functions of the direct memory access 120, the vector circuit 130 and the convolution circuit 140, they will not be described in detail.

The decoder 110 includes a memory 112 (eg, Static Random Access Memory (SRAM)), an instruction prefetch circuit 114, an instruction delivery circuit 116, and a jump logic circuit 118. The memory 112 can store instructions to be executed by the intelligent processor 100 . The instruction prefetch circuit 114 is used to obtain the instruction from the memory 112, and then the instruction distribution circuit 116 distributes the instruction to the corresponding hardware circuit (ie, direct memory storage) according to the instruction's flag InstFlag (please refer to FIG. 7). Take 120, vector circuit 130 or convolution circuit 140). The jump logic circuit 118 is used to determine whether the instruction is a jump instruction and/or the type of jump instruction (long jump instruction or short jump instruction). When a jump instruction is encountered, jump The logic circuit 118 determines the destination of the jump instruction, and then the instruction prefetch circuit 114 obtains the next instruction based on the destination.

In some embodiments, if the difference between the destination of a jump instruction (i.e., the address of the target instruction in the memory 112) and the address of the jump instruction itself in the memory 112 is less than a threshold (e.g., the address of the target instruction in the memory 112 The size of the instruction temporary storage area), then the jump instruction is a short jump instruction; otherwise, the jump instruction is a long jump instruction. In other words, the jump range of a short jump instruction is smaller than the jump range of a long jump instruction. When the decoder 110 processes the long jump instruction, the direct memory access 120 is required to obtain more information from the external memory of the intelligent processor 100 (for example, dynamic random access memory (DRAM), not shown). instructions, while short jump instructions do not; therefore, long jump instructions are more time-consuming and consume system resources than short jump instructions.

Figure 2 is a flow chart of one embodiment of the process compression method of the present invention. In some embodiments, the steps of FIG. 2 are performed by a development tool (eg, a general-purpose computer) during the development phase of the intelligent processor 100 . The process compression method in Figure 2 can be used to compress a certain process (for example, image processing process, startup process, etc.), and the process contains multiple instructions (for example, the process 310 in Figure 3 includes 15 instructions including instructions INST1 ~ instructions INST15. These instructions are variable-length instructions, and at least one of them is a jump instruction, as shown in Figure 3 below). Figure 2 contains the following steps.

Step S210: According to the position of the jump instruction in a process (for example, the address of the jump instruction in the memory 112) and the destination of the jump instruction (for example, the address of the destination in the memory 112), the process is divided into Multiple blocks. More specifically, step S210 scans instructions in a process and sets block boundaries BB to divide the process into multiple blocks. The details of step S210 will be described in detail below with reference to FIG. 5 . In the example of Figure 3, the process 310 is divided into 4 blocks (blocks BLK1~Block BLK4 respectively include instructions INST1~Instruction INST5, instructions INST6~Instructions INST8, instructions INST9~Instructions INST11 and instructions INST12~Instructions INST15. Instructions INST5 and INST11 are jump instructions, and their destinations are INST9 and INST11 respectively. Instruction INST6).

Step S220: Record the jump relationship between blocks. Please refer to Figure 3. After step S210, the jump relationship 320 between blocks can be obtained: the target block of block BLK1 is block BLK3 (because block BLK3 contains the destination of instruction INST5 (ie, instruction INST9)); area The source block of block BLK2 is block BLK3 (because block BLK2 contains the destination of instruction INST11 (i.e., instruction INST6)); and the source and target blocks of block BLK3 are block BLK1 and block BLK2 respectively. . Please refer to Figure 4. Figure 4 is a schematic diagram of the jump relationship between blocks, which corresponds to the jump relationship 320 between blocks in Figure 3; in other words, the jump relationship between blocks can also be represented or recorded graphically.

Step S230: Perform instruction compression on these blocks block by block to obtain multiple compressed blocks. This step will be detailed below in conjunction with Figure 6.

Step S240: Recalculate the jump address (jump address, that is, the destination address of the jump instruction) according to the jump relationship between blocks. Because the block has been compressed in step S230, the destination address of the jump instruction after compression is no longer the original address, so the jump address must be recalculated or updated. For example, please refer to Figure 3. Since almost every block becomes smaller after compression, the positions of instructions INST9 and INST6 change, so the addresses of the destinations of instructions INST5 and INST11 must be updated or adjusted accordingly.

Step S250: Determine the group according to the block size and jump relationship. The purpose of this step is to divide multiple blocks into multiple groups. The details of step S250 will be explained below with reference to Figures 8 to 9 .

Step S260: Determine whether the jump instruction is a first type of jump instruction (for example, a short jump instruction) or a second type of jump instruction (for example, a long jump instruction) according to the relationship between the jump instruction and the group. By dividing blocks into multiple groups, the present invention can more accurately divide short jump instructions and long jump instructions to avoid errors during the execution process. Step S260 will be explained below with reference to FIG. 11 .

Figure 5 is the details of step S210, including steps S510 to S550. Please refer to both Figure 3 and Figure 4 for the following description.

Step S510: Read an instruction.

Step S520: Determine whether the instruction is a jump instruction or the destination of a jump instruction. If not, perform step S510 to read the next instruction; if yes, perform step S530.

Step S530: Set the block boundary BB to determine the block. More specifically, if the instruction is a jump instruction, step S530 sets the block boundary BB after the instruction (for example, between instructions INST5 and INST6 and between instructions INST11 and INST12 in Figure 3); if the instruction is the destination of the jump instruction, then step S530 sets the block boundary BB before the instruction (for example, between instructions INST5 and INST6 and between instructions INST8 and INST9 in Figure 3).

Step S540: Determine whether there are still instructions to be processed in the process. If yes, step S510 is executed to read the next instruction; if not, step S550 is executed.

Step S550: Set the block boundary BB and then end.

Taking Figure 3 as an example, the method of Figure 5 will divide the process 310 at the instruction INST5 (ie, set the block boundary BB) to generate the block BLK1. Similarly, since instructions INST9 and Instruction INST11 is the destination and jump instruction respectively, so the block boundary BB will be set before instruction INST9 and after instruction INST11, so block BLK2 and block BLK3 are generated respectively. At the end of the process 310, the block boundary BB will also be set to generate block BLK4.

Figure 6 is a flow chart of an embodiment of the instruction compression method of the present invention. FIG. 7 is a schematic diagram of the instruction structure before compression and the instruction structure after compression. As shown in Figure 7, instructions INST_k-1 and instructions INST_k are uncompressed instructions (both are consecutive instructions, and instruction INST_k-1 precedes instruction INST_k). Instructions INST_k-1, instructions INST_k and compressed instructions INST_k' all include header HD and at least one parameter (for example, instructions INST_k-1 and instructions INST_k each include n parameters P1 (or P1') ~ Pn, and after compression The instruction INST_k' contains 1 parameter P1'). In some embodiments, the size of the header HD and each parameter is one word. The header HD contains the flag InstFlag and the reference value HDLen. The flag InstFlag records the hardware circuit to which the instruction belongs. For uncompressed instructions, the reference value HDLen records the number of parameters (for example, the reference value HDLen of instructions INST_k-1 and INST_k is n); for the compressed instruction INST_k', the reference value HDLen is the default value (e.g. 0). The compression method in Figure 6 is based on blocks and includes the following steps.

Step S610: Read an instruction of a block.

Step S620: Determine whether the instruction is the first instruction of the block. If yes, step S610 is executed to read the next instruction of the block; if not, step S630 is executed. The first instruction of a block is not compressed (because there are no previous instructions to refer to).

Step S630: Compare the instruction with the previous instruction to find out the different parameters in the instruction that are different from the previous instruction. Taking Figure 7 as an example, because the parameters P2~parameters Pn of the instruction INST_k-1 are respectively equal to the parameters P2~parameters Pn of the instruction INST_k, and only the parameter P1 is not equal to the parameter P1', so the step The dissimilar parameter found in step S630 is parameter P1'.

Step S640: Set the reference value HDLen of the header HD of the compressed instruction to a default value in order to mark the compressed instruction.

Step S650: Set the first parameter of the compressed instruction to the number of different parameters Nd. Taking Figure 7 as an example, because the number Nd of different parameters between instructions INST_k-1 and INST_k is 1, this step sets the first parameter of the compressed instruction INST_k' to 1 (that is, "Len=1 ”).

Step S660: Set other parameters of the compressed instruction to the different parameters. In this step, the second to xth (x=1+Nd) parameters of the compressed instruction INST_k' are set to the different parameters obtained in step S630. Taking Figure 7 as an example, because the only different parameter between instruction INST_k-1 and instruction INST_k is parameter P1' (that is, the number of different parameters Nd is 1), so this step will compress the second parameter of instruction INST_k'. The parameter is set to parameter P1'. After step S660 is completed, the compressed instruction INST_k' can be obtained.

Step S670: Determine whether there are any instructions to be processed in the block. If yes, step S610 is executed to read the next instruction of the block; if not, the method of FIG. 6 ends (step S680).

FIG. 8 and FIG. 9 are details of an embodiment of step S250 in FIG. 2 . Step S250 includes two main steps: first determine the group according to the block size (Fig. 8), and then adjust the group according to the jump relationship (Fig. 9). Please refer to FIG. 10A and FIG. 10B together for the following description. FIG. 10A and FIG. 10B are schematic diagrams of an embodiment of dividing multiple blocks of the process into multiple groups according to the present invention, corresponding to the process 310 of FIG. 3 . Figure 8 contains the following steps.

Step S810: Select a block and update the size of the current group according to the size of the block. size. The size of a group is the sum of the sizes of all the blocks it contains. This step updates the current group size by adding the current group size to the block size. Taking FIG. 10A as an example, assuming that the current group only contains block BLK1, the selected block is block BLK2, and the updated size of the current group is the sum of the size of block BLK1 and the size of block BLK2.

Step S820: Determine whether the size of the current group is greater than the threshold. In some embodiments, the threshold may be the size of the instruction buffer area of the memory 112 . If the determination result in step S820 is no, step S830 is executed; otherwise, step S840 and step S850 are executed.

Step S830: Set the block as part of the current group. The negative result of step S820 means that adding the selected block to the current group will not make the current group too large (greater than the threshold), so step S830 sets the block as part of the current group. Following the above example, assuming that the sum of the sizes of block BLK1 and block BLK2 does not exceed the threshold SR, block BLK2 is set to the same group as block BLK1 in this step.

Step S840: Set the block as part of a new group. The judgment result in step S820 is that adding the selected block to the current group will make the current group too large (greater than the threshold), so step S840 determines the current group (ie, sets the group boundary GB), and then adds the selected block to the current group. The block is set as part of the new group (the new group only contains this block at this time). Taking Figure 10A as an example, when the selected block is block BLK3, in step S840, the group boundary GB will be set first (ie, group GRP1 is determined), and then group GRP2 is established (at this time, group GRP2 only contains Block BLK3 and not yet finalized).

Step S850: Set the size of the new group to the size of the block. Following the above example, because group GRP2 only contains block BLK3 at this time, the size of the new group is equal to the size of block BLK3. It should be noted that the new group becomes the new group in the next round (ie, when step S810 is executed again). The current group for the round.

Step S860: Determine whether there are still blocks to be processed. If yes, perform step S810 to select the next block; if not, perform step S870.

Step S870: Set the group boundary, and then end. Taking FIG. 10A as an example, when the selected block is block BLK4, the determination in step S860 is no, and then step S870 sets the group boundary GB after block BLK4 to determine group GRP2.

Please refer to Figure 10A. After the method in Figure 8 is completed, the four blocks in Figure 4 are divided into two groups. However, because there is a destination of a jump instruction in the middle of group GRP1 (i.e., between the first block and the last block of a group) (i.e., the destination of instruction INST11 is block BLK2), this will cause A jump error occurred during execution of the process, so the group must be further adjusted according to the method in Figure 9. Figure 9 contains the following steps.

Step S910: Select a group.

Step S920: Select a block of the group.

Step S930: Determine whether the following conditions are true: the block is not the first block of the group, and the block is the destination of jump instructions of other groups. Taking FIG. 10A as an example, if step S910 and step S920 select group GRP1 and block BLK1 respectively, the judgment result of step S830 is no (because block BLK1 is the first block of group GRP1); if step S910 and step S920 respectively select group GRP1 and block BLK2, then the judgment result of step S830 is yes (because block BLK2 is not the first block of group GRP1 and is the destination of instruction INST11).

Step S940: Determine whether the group still has blocks to be processed. If yes, perform step S920 to select the next block of the group; otherwise, perform step S960.

Step S950: Set the group boundary GB, that is, divide the current group into two groups group. Taking FIG. 10A and FIG. 10B as an example, step S950 sets the group boundary GB before the block BLK2 (ie, the destination of the instruction INST11), so that the original group GRP1 becomes the group GRP1 and the group GRP3.

Step S960: Determine whether there are still groups to be processed. If yes, step S910 is executed to select the next group; if no, the method of FIG. 9 ends (step S970).

Figure 11 is the details of an embodiment of step S260 in Figure 2, including the following steps.

Step S1110: Select a jump instruction. Taking Figure 10B as an example, this step will select instruction INST5 or instruction INST11.

Step S1120: Determine whether the destination of the jump instruction is within the group to which the jump instruction belongs. Taking FIG. 10B as an example, for instruction INST5, because its destination (block BLK3) is not in the group to which instruction INST5 belongs (ie, group GRP1), the judgment result in step S1120 is no. Similarly, for the instruction INST11, the judgment result of step S1120 is also no.

Step S1130: Set the jump instruction as a long jump instruction.

Step S1140: Set the jump instruction as a short jump instruction.

Step S1150: Determine whether there are still jump instructions. If yes, step S1110 is executed to select the next jump instruction; if not, the method of FIG. 11 is ended (step S1160).

In the example of FIG. 10B , instructions INST5 and INST11 are both inter-group jump instructions (long jump instructions). Please refer to FIG. 12 , which is a schematic diagram of another embodiment of dividing groups according to the present invention. As shown in Figure 12, group GRP1 includes block BLK1, block BLK2, and block BLK3, while group GRP2 only includes block BLK4. Since the jump instruction INST_n is in group GRP1 and its destination (block BLK3) is also in group GRP1, the jump instruction INST_n is an intra-group jump instruction; therefore, the jump instruction INST_n will be used in the method of Figure 11 Judged as short jump Transfer command (ie, step S1120 determines yes).

Figure 13 is a flow chart of one embodiment of the instruction decompression method of the present invention. FIG. 13 illustrates the instruction decompression circuit (ie, instruction decompression circuit 122, instruction decompression circuit 132, or instruction decompression circuit) of the hardware circuit (ie, direct memory access 120, vector circuit 130, or convolution circuit 140) of FIG. 1 Compression circuit 142) is executed, and Figure 13 contains the following steps.

Step S1310: Read or receive an instruction, for example, read an instruction from the memory, or receive an instruction distributed by the instruction distribution circuit 116.

Step S1320: Determine whether the reference value HDLen of the header HD of the instruction is a default value. If not (representing that the instruction is not a compressed instruction), then step S1330 is executed; if yes (representing that the instruction is a compressed instruction), then step S1340 and step S1350 are executed.

Step S1330: Use all parameters of the instruction to set corresponding parameters of the hardware circuit (for example, set the temporary value of the register). Please refer to FIG. 14 , which is a schematic diagram of the hardware circuit of the present invention executing uncompressed instructions. Assume that before executing the uncompressed instruction INST_y (including 5 parameters P1', P2', P3', P4' and P5'), the register group REGP of the hardware circuit stores P1, P2, P3, P4 and The five parameters including P5 (the temporary values of register REG1, register REG2, register REG3, register REG4 and register REG5 respectively) are temporarily stored after the hardware circuit executes the instruction INST_y. The register group REGP stores the five parameters of the instruction INST_y (as shown in the register group REGP on the right side of Figure 14). That is to say, the purpose of step S1330 is to set the parameters of the hardware circuit with the parameters of the instruction INST_y. After the parameter setting of the hardware circuit is completed, the hardware circuit (more specifically, the calculation circuit of the hardware circuit) can execute the instruction (step S1360).

Step S1340: Read the first parameter of the instruction to obtain the number of different parameters Nd. Please refer to FIG. 15 , which is a schematic diagram of the hardware circuit of the present invention executing compression instructions. The fingers in Figure 15 Let INST_z be a compressed instruction, and its number of distinct parameters Nd is 2 (ie, "Len=2").

Step S1350: Use the second to Nd+1th parameters of the instruction to set the corresponding parameters of the hardware circuit (for example, set the temporary value of the register). In the example of Figure 15, the instruction decompression circuit obtains the parameters P1' and parameter P2' of the compressed instruction INST_z according to the number of different parameters Nd, and then sets the register REG1 and the temporary register respectively with the parameter P1' and the parameter P2'. Register REG2. The purpose of step S1350 is to set the parameters of the hardware circuit using the parameters of the compressed instruction INST_z. After the parameter setting of the hardware circuit is completed, the hardware circuit can execute the instruction (step S1360).

In summary, the present invention reduces the space required for the instruction register (ie, reduces the size of the memory 112) by compressing instructions to save costs. In addition, because the instructions are compressed, the present invention can also reduce the number of long jump instructions to improve the execution efficiency of the process.

Although the foregoing embodiments take variable-length instructions and intelligent processors as examples, this is not a limitation of the present invention. Those skilled in the art can appropriately apply the present invention to other types of command and control circuits based on the disclosure of the present invention.

Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the patent protection scope of the present invention must be determined by the patent application scope of this specification.

S210, S220, S230, S240, S250, S260: steps

Claims (18)

An instruction decompression method is applied to a hardware circuit. The hardware circuit decompresses an instruction and executes the instruction. The instruction includes a header, and the header includes a reference value. The method includes: when the instruction is When the reference value is a default value, read a first parameter of the instruction to obtain a number of different parameters; and use a plurality of second parameters of the instruction to set a plurality of corresponding parameters of the hardware circuit, The number of the second parameters is equal to the number of the different parameters. The method of claim 1 further includes: when the reference value of the instruction is not the default value, setting the corresponding parameters of the hardware circuit with all parameters of the instruction. The method of claim 1, wherein the hardware circuit includes a plurality of temporary registers, and the corresponding parameters are temporary values of the temporary registers. Such as the method of claim 1, wherein when the number of different parameters is N, the second parameters are the second parameter to the N+1th parameter of the instruction. Such as the method of claim 1, wherein the instruction is a variable length instruction. An instruction compression method is used to compress an instruction to generate a compressed instruction. The instruction includes a header and a plurality of parameters. The header includes a reference value. The method includes: comparing the instruction with a previous instruction, To find a plurality of distinct parameters in this command that are different from the previous command; The reference value of the compressed instruction is set to a default value; a target parameter of the compressed instruction is set to the number of different parameters; and other parameters of the compressed instruction are set to these different parameters. Such as the method of claim 6, wherein the method is applied to a hardware circuit, the hardware circuit executes a process, the instruction and the previous instruction are consecutive instructions of the process, and the instruction is later than the previous instruction . Such as the method of claim 7, wherein the process includes a plurality of blocks, each block includes a plurality of instructions, the instruction and the previous instruction belong to the same target block in the blocks, and the instruction is not the The first instruction of the target block. Such as the method of claim 6, wherein the target parameter is the first parameter of the compressed instruction. Such as the method of claim 6, wherein the instruction is a variable length instruction. A process compression method used to compress a process, the process includes a jump instruction, the method includes: (A) according to a position of the jump instruction in the process and a destination of the jump instruction, dividing the process into A plurality of blocks; (B) record a jump relationship between the blocks; (C) perform instruction compression on these blocks; (D) recalculate a jump address of the jump instruction based on the jump relationship; ( E) Determine a plurality of groups based on the sizes of the blocks and the jump relationship; and (F) Determine whether the jump instruction is a first type of jump instruction or a second type of jump instruction based on the relationship between the jump instruction and the groups. For example, the method of claim 11, wherein the process further includes a plurality of instructions, and the step (A) includes: reading one of the instructions; and when the read instruction is the jump instruction or the jump instruction For this destination, set a block boundary. The method of claim 12, wherein the instructions are a plurality of variable length instructions. Such as the method of claim 11, wherein the step (E) includes: selecting a block from the blocks; updating the size of a current group according to the size of the block; when the size of the current group is greater than When the threshold is reached, the block is set as part of a new group; and when the size of the current group is not greater than the threshold, the block is set as part of the current group. The method of claim 14, wherein the step (E) further includes: when the size of the current group is greater than the threshold, setting the size of the new group to the size of the block. The method of claim 14, wherein the jump instruction is a first jump instruction, the destination is a first destination, and the step (E) further includes: selecting a first group; Selecting a target block of the first group; and when the target block is not the first block of the first group, and the target block is a second jump instruction of a second group For the second destination, set a group boundary. Such as the method of claim 11, wherein the step (F) includes: selecting the jump instruction; when the destination of the jump instruction is located in a target group to which the jump instruction belongs, setting the jump instruction to a Short jump instructions. Such as the method of claim 17, wherein the step (F) further includes: when the destination of the jump instruction is not located in the target group, setting the jump instruction to a long jump instruction; wherein, the short jump instruction The jump range of the jump instruction is smaller than the jump range of the long jump instruction.