JP2002108958A - System and method for designing circuit and computer readable recording medium stored with circuit design program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately determine the system for mounting a function block in a short time. SOLUTION: This system is provided with: an algorithm/architecture database 132 storing the combination of algorithm and architecture for providing each of function modules and the result of evaluating the performance of the combination; a combination generating part 113 for generating all the possible combination of algorithm and architecture for providing each of function modules while referring to the information stored in the algorithm/architecture database 132; a performance evaluating part 115 for evaluating the performance of the combination generated by the combination generating part 113 on the basis of limit conditions, an evaluation function and an operating scenario; and a candidate database 135 for storing the combination of algorithm and architecture equal to or higher than a prescribed evaluation value while referring to the evaluation result of the performance evaluating part 115.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit design system, a circuit design method, and a computer-readable recording medium storing a circuit design program for determining a mounting method of a plurality of functional blocks in a circuit to be designed. The present invention relates to a technology that enables a mounting method of a functional block to be determined in a short time and with high accuracy.

[0002]

2. Description of the Related Art Conventionally, in a circuit design process of a digital system such as a system LSI, a mounting method (specification) of each functional block is performed at a functional level with respect to each mounting method, and based on a result of the simulation. It was determined by estimating the performance of each implementation method.

[0003]

However, when the mounting method is determined by such a method, an enormous amount of time is required to complete the function level simulation when the number of mounting method candidates increases. In addition, it is very difficult to consider all combinations of the mounting methods, so that it is difficult to accurately determine the mounting method of each functional block.

The present invention has been made to solve such a technical problem, and an object of the present invention is to provide a technique which enables a mounting method of a functional block to be determined in a short time and with high accuracy. It is in.

[0005]

A feature of a circuit design system according to the present invention is a circuit design system for determining a mounting method of a plurality of functional blocks in a circuit to be designed,
An algorithm architecture database that stores combinations of algorithms and architectures that implement each function module and the results of evaluating the performance of the combination, and an algorithm that implements each function module by referring to the information stored in the algorithm architecture database A combination generation unit that generates all possible combinations of software and architecture, a performance evaluation unit that evaluates the performance of the combination generated by the combination generation unit based on constraints, evaluation functions, and operation scenarios, and an evaluation of the performance evaluation unit Referencing the result, a candidate database for storing a combination of an algorithm and an architecture having a predetermined evaluation value or more is provided.

According to this system, a good combination of an algorithm and an architecture for realizing the system can be selected at a high speed without performing a functional-level simulation.

A feature of the circuit design method according to the present invention is a circuit design method for determining a mounting method of a plurality of functional blocks in a circuit to be designed, and a combination of an algorithm and an architecture for realizing each functional module and a performance of the combination. Generating all possible combinations of algorithms and architectures for realizing each functional module using the result of evaluating
Evaluating the performance of the generated combination based on the evaluation function and the operation scenario; and extracting a combination of an algorithm and an architecture having a predetermined evaluation value or more by using the performance evaluation result. is there.

According to this method, a good combination of an algorithm and an architecture for realizing a system can be selected at a high speed without performing a functional-level simulation.

A feature of a computer-readable recording medium storing a circuit design program according to the present invention is a computer-readable recording medium storing a circuit design program for determining a mounting method of a plurality of functional blocks in a circuit to be designed. A process for generating all possible combinations of algorithms and architectures for realizing each functional module, using the results of evaluating the combinations of algorithms and architectures for realizing each functional module and the performance of the combinations; Based on an evaluation function and an operation scenario, a process of evaluating the performance of the generated combination and a process of extracting a combination of an algorithm and an architecture having a predetermined evaluation value or more by using the performance evaluation result, Let the computer execute these processes Lies in the fact.

According to this recording medium, a good combination of an algorithm and an architecture for realizing a system can be selected at a high speed without performing a simulation at a functional level.

Here, it is desirable to execute a function level simulation for a combination of an algorithm and an architecture having a predetermined evaluation value or more, using a function model and a test vector relating to the combination of the algorithm and the architecture.

[0012] Thereby, the best one can be selected with high accuracy by functional level simulation from a plurality of combinations stored in the candidate database.

In addition, a resource sharing relationship between functional modules is added to the operation scenario by adding a directed branch so that a loop does not exist, with the resource sharing relationship between functional modules as an execution order. It is desirable that the operation order can be expressed without contradiction.

This makes it possible to reflect the resource sharing relationship between the functional modules in the operation scenario expressing the operation of the system.

The shortest execution time of the operation scenario is as follows:
For the operation scenario, the execution time of the combination at the node representing the functional module is added as a weight,
The longest path from the node representing the start of the process to the node representing the end may be obtained as the shortest execution time of the operation scenario.

Thus, in the operation scenario, the shortest execution time of the processing can be obtained by loading the execution time of the functional module as the weight of the node and obtaining the longest path.

Further, the execution order and the execution time of an arbitrary degree of parallelism are determined by performing a topological sort on a partially ordered graph expressing an operation scenario, and the order of execution among the functional modules is determined. It is better to estimate by assigning function modules to threads.

Thus, the operation scenario is topologically sorted, and each functional module is assigned to a thread, so that the execution order and execution time of an arbitrary degree of parallelism can be estimated.

Furthermore, the maximum value, the minimum value, and the average value of the power consumption of the system during the execution of the operation scenario are determined in advance according to the execution order of the functional modules by the hardware for mounting the functional modules. It is desirable to accumulate the power consumption during the execution, and when the hardware is not being executed, obtain the power consumption by estimating the power consumption of the hardware in a halt state estimated in advance.

As a result, the maximum value, the minimum value, and the average value of the power consumption of the system executing the operation scenario can be obtained.

The maximum value, the minimum value, and the average value of the bus access of the system executing the operation scenario are determined in advance according to the execution order of the function modules. It is good to obtain it by accumulating the bus access during execution of.

Thus, it is possible to estimate the bus access frequency for obtaining the maximum value, the minimum value, and the average value of the bus access of the system executing the operation scenario.

Further, the area of the LSI necessary for realizing the system may be obtained by estimating the maximum value of the hardware resources required simultaneously according to the determined execution order of the functional modules.

Thus, the LS required for realizing the system
The area of I can be estimated.

Furthermore, means for generating all system architectures, which are possible hardware configurations for combinations included in the candidate database, and storing the generated system architecture in the system architecture database, and sharing operation scenarios in accordance with the combination of the separation candidate database. An operation scenario update unit that reflects the relationship may be provided, and the updated operation scenario may be evaluated for all system architectures included in the system architecture database.

As a result, all possible system architectures can be generated for combinations of algorithms and architectures for realizing the system, and the performance of them can be estimated.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a circuit design system according to an embodiment of the present invention will be described below in detail with reference to FIGS.

<< Circuit Design System >> First, a configuration of a circuit design system according to an embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 1, the circuit design system according to the first embodiment of the present invention includes a circuit design device 110, and the circuit design device 110 includes an input / output interface 11
1. Framework creation unit 112, combination creation unit 1
13, a function level simulation unit 114, a performance evaluation unit 115, and a control unit 116.

The input / output interface 111 has a role of controlling information input / output processing between the user and the system. Specifically, the input / output interface 111 uses, for example, a graphical user interface (GUI) or the like. This enables interactive circuit design processing.

The framework creating unit 112 creates a framework for the candidate creation processing and the cut-off determination processing.

The combination generation unit 113 stores a combination of an algorithm and an architecture for implementing each function module in the algorithm / architecture database 1.
32 is selected from the combinations stored in the table 32.

The function level simulation unit 114
A function level simulation is performed on the combination selected by the combination generation unit 113.

The performance evaluation unit 115 evaluates a combination of an algorithm and an architecture for implementing a function module and a function level simulation result using the constraint function / evaluation function and the operation scenario.

The control unit 116 controls the performance evaluation process and the operation of each component in the apparatus.

The circuit design device 110 includes the input unit 12
0, output unit 121, functional block diagram database 13
0, function model database 131, algorithm / architecture database 132, operation scenario database 133, constraint / evaluation function database 13
4. It is electrically connected to the candidate database 135, the test vector database 136, the evaluation result database 137, and the hardware / software specification database 138, and is configured to be able to read and write data stored in each database.

The input section 120 has a role of inputting various information and control parameters relating to the circuit design processing, and includes, for example, a keyboard, a mouse, a light pen, and the like.

The output section 121 has a role of outputting various information and error information relating to the circuit design processing, and corresponds to, for example, a printer or a display device.

The function block diagram database 130 stores a plurality of pieces of function module information relating to a circuit to be designed.

The function model database 131 stores a function model corresponding to an algorithm and an architecture assigned to each function module.

The algorithm / architecture database 132 stores a combination of an algorithm and an architecture for implementing a functional module.

The operation scenario database 133 stores operation scenarios of circuits and functional modules to be designed. Here, the “operation scenario” expresses the operation of a circuit to be designed, and the relationship between data / control transfer between functional modules is described as a directed branch with functional modules as nodes. It is represented by a partial order graph (details are described later).

Restriction condition / evaluation function database 134
Stores the constraint condition / evaluation function used for the performance evaluation process.

The candidate database 135 stores a candidate for a combination of an algorithm and an architecture for realizing the function module generated by the combination generation unit 113.

The test vector database 136 stores test vectors used in the function level simulation.

The evaluation result database 137 stores the results of the performance evaluation processing by the performance evaluation unit 115.

The hardware / software specification database 138 stores a combination of an algorithm and an architecture for realizing the function module determined by the separation determination processing.

The circuit design apparatus includes so-called general-purpose machines, workstations, PCs, NCs (Network Computing).
er) and the like, for example, have an overview like the configuration shown in FIG.
And an optical disk drive 74. And
By inserting a floppy disk 73 into the floppy disk drive 72 and an optical disk 75 into the optical disk drive 74 and performing a predetermined read operation, the programs stored in these recording media are installed in the computer system. be able to.
Further, by connecting a predetermined drive device, for example, installation and reading / writing of data can be executed using a ROM 77 serving as a memory device and a cartridge 78 serving as a magnetic tape device.

<< Operation of Circuit Design System ~ Circuit Design Method ~ >> Next, a circuit design method according to an embodiment of the present invention will be described with reference to FIGS.

The circuit design method according to the embodiment of the present invention
As shown in FIG. 2, the processing is roughly divided into two processes.

The first process, the candidate creation process (S20)
In 1), the combination generation unit 113 stores a combination of an algorithm and an architecture for implementing each function module stored in the function block diagram database 130 in the algorithm / architecture database 1.
Then, the performance evaluation unit 115 selects the combination of the constraint function / evaluation function stored in the constraint condition / evaluation function database 134 and the operation stored in the operation scenario database 133. Evaluate each selected combination using a scenario. Since the generation and evaluation of this combination are performed based on static data described in advance in the algorithm architecture database 132, there is a possibility that an error may be included in the dynamic behavior. Therefore, in the circuit design processing according to the embodiment of the present invention, a plurality of solutions are obtained in consideration of the error in advance, and the plurality of solutions are written in the candidate database 135.

[0052] The second process, which is a decision-making process (S
In 202), the function level simulation unit 1
14 performs a function level simulation for all combinations stored in the candidate database 135, and evaluates the function level simulation results using the same constraint function / evaluation function used in the candidate creation processing. Then, based on the evaluation result, the best combination is output as hardware / software specifications and stored in the hardware / software specification database 138. At the time of the decision-making process, a function model corresponding to an algorithm and an architecture assigned to each function module is selected from the function model database 131 to create a simulation model. Also, test vectors required for the simulation are prepared in the test vector database 136 in advance.

When the above-described candidate creation processing and division determination processing are completed, an actual circuit is manufactured with reference to the hardware / software specifications determined by these processing (S203). Hereinafter, each of the above-described candidate creation processing and the cut-off determination processing will be described in more detail.

<Candidate Creation Processing> The candidate creation processing according to the embodiment of the present invention is executed by the following processing steps as shown in FIG.

(1) The framework creation unit 112 refers to the functional block diagram database 130 and the algorithm / architecture database 132 to create a framework for generating a combination of an algorithm and an architecture assigned to a functional module. (S301).

(2) Based on the framework created by the framework creating unit 112, the combination creating unit 113 creates all possible combinations of algorithms and architectures for functional modules (S302).

(3) The performance evaluation unit 115 uses the constraint / evaluation function stored in the constraint / evaluation function database 134 in accordance with the operation scenario stored in the operation scenario database 133 to generate the combination generation unit 113 Statically evaluates the performance of the combination generated by (3). The details of the performance evaluation method will be described later.

(4) The control unit 115 performs the performance evaluation unit 115
Is compared with the combination stored in the candidate database 135, and a predetermined number (e.g., 1) from a predetermined best value (evaluation value) is stored in the candidate database 135.
The combination information stored in the candidate database 135 is updated so that a good combination of (0 to 100) is held (S304).

By repeating the processes (3) and (4) until the evaluation of all the combinations generated by the combination generation unit 113 is completed, a predetermined number of statics are stored in the candidate database 135. Combinations that are deemed good in evaluation will always be retained.

<Division Determination Processing> The division determination processing according to the embodiment of the present invention is executed by the following processing steps as shown in FIG.

(1) The framework creation unit 112 refers to information stored in the function block diagram database 130, the function model database 131, and the algorithm / architecture database 132, and combines the assignment of the function model to the function module. Is generated, and a framework for a functional-level simulation model is created (S401).

(2) The combination generating unit 113 generates all possible combinations stored in the candidate database 135 based on the framework created by the framework creating unit 112 (S402).

(3) Function level simulation section 11
4 executes a function level simulation for the combination of the function module and the function model generated by the combination generation unit 113 (S403). The function level simulation is performed using a test vector prepared in advance in the test vector database 136.

(4) The performance evaluation unit 115 evaluates the function level simulation result using the constraint condition / evaluation function stored in the constraint condition / evaluation function database 134, and stores the evaluation result in the evaluation result database 137. (S404).

(5) This series of processing is repeated until all combinations stored in the candidate database 135 are evaluated, and S403 and S404 are repeated.
The evaluation result of the result of performing the function level simulation for all the combinations stored in 35 is stored in the evaluation result database 137 (S40).
5).

(6) Finally, the best combination is determined by comparing the evaluation results stored in the evaluation result database 137 by the comprehensive evaluation process, and then the best combination is output as hardware / software specifications. Hardware / Software Specification Database 13
8 (S406).

[Performance Evaluation Processing] The performance evaluation processing based on the operation scenario will be described below with reference to FIGS.

(1) The control unit 116 updates the operation scenario for resource sharing and the like according to the combination stored in the candidate database 135, and stores the update result in the operation scenario database 132 (S50).
1).

(2) The control unit 116 evaluates the update result based on the evaluation function and the constraint, and stores the evaluation result in the evaluation result database 137 (S50).
2).

After performing the processes (1) and (2) for all operation scenarios, comprehensive evaluation is performed using the evaluation result database 137 (S504). As a result, a combination of a certain candidate for all operation scenarios is evaluated.

In the processing shown in FIG. 5, a plurality of operation scenarios are evaluated, but only one system architecture is evaluated. If you extend this to multiple system architectures,
The processing is performed according to the flowchart shown in FIG.

In the processing shown in FIG. 6, the operation scenario update processing (S601), the performance evaluation processing (S602), the judgment processing (S604), and the comprehensive evaluation processing (S605) are respectively the processing (S501) shown in FIG. (S50
2), (S503) and (S504). However, unlike the performance evaluation processing (S502) in FIG. 5, the performance evaluation processing (S602) determines that all system architectures have been evaluated in order to perform processing with reference to a system architecture database (not shown). (S603) is added. Here, the system architecture database is a database in which the combinations stored in the candidate database 135 are analyzed in advance, and possible system architecture structures are converted into a database.

As described above, according to the performance evaluation processing shown in FIGS. 5 and 6 according to the embodiment of the present invention, the static performance evaluation based on the operation scenario and the dynamic performance based on the simulation of the function level are performed. Since the evaluations are performed in combination, it is possible to search for a wide solution space in a short time and with the same accuracy as compared with the case of performance evaluation using only dynamic performance evaluation based on the function level simulation.

-Performance Evaluation Method Based on Operational Scenario- Next, a specific performance evaluation method based on an operation scenario will be described. Here, for a certain combination of an algorithm and an architecture for realizing the system, the area and the energy required for processing are automatically determined when the combination is determined. Therefore, a method for evaluating the processing time, the maximum value of the power consumption, and the bus access frequency will be described below.

[Operation Scenario and Processing Time] FIG. 8A shows an example of an operation scenario, and the operation scenario is expressed by a partial order graph. Here, the partially ordered graph is formed of directed branches connecting the contacts and having no loop. Also, in FIG. 8A, S and E
Respectively represent the starting point and the ending point of the partially ordered graph, and correspond to the beginning and the end of the processing, respectively. Furthermore, the contact points in the graph represent each function of the system, and the directed branches represent the causal relationship between the functions. For example, contact 3 in the graph is connected to four contacts 1, 2, 9, and 5 by four branches. here,
The branch coming out of the contacts 4 and 5 is connected to the contact 3.
This indicates that the processing represented by the contact 3 can be executed after the processing of the contact 1 and the contact 2 is completed. Also, the contacts 9 and 5 to which the branches coming out of the contact 3 are connected represent processes that must be executed after the contact 3.

Here, consider a situation in which the processes represented by the contact points D and B share certain resources and cannot be executed in parallel. Now, assuming that there is no direct causal relationship between the two processes, there is no branch between the two points in the graph representing the operating scenario. However, because of the resource sharing relationship, it is necessary to order the two processes. Therefore, a solution to such a situation is shown in FIG. In the partial order graph shown in FIG. 8B, a branch is added between the contact point D and the contact point B. The branches allow the order of the process represented by the two contacts. It is necessary to attach this branch so that a loop cannot be formed.

Next, FIG. 9A shows an example of a sequence in which all the processes are sequentially executed for the operation scenarios shown in FIGS. 8A and 8B. In order to obtain such a sequence from the operation scenario, for example, a topological sort may be performed. Note that there may be a plurality of this sequence for the operation scenario. The process represented by a contact point having no direct causal relationship in the graph can be performed in parallel as long as there is no resource sharing relationship as shown in FIG. Here, for the sake of simplicity, FIGS. 9B and 10 show examples of parallel processing when it is assumed that the time required for all the processing is equal.

FIG. 9 (b) shows the operation scenario of FIGS. 8 (a) and 8 (b) as two threads of parallel processing. FIG.
In the operation scenario 2 shown in (b), the processing of the contact point B is later than the processing of the contact point D due to the branch indicating the resource sharing. For some operating scenarios, the shortest execution time is
The longest path length can be obtained by assuming that the contact point of the graph has the processing time as a weight. This is clear from the definition of the graph. At this time, the obtained degree of parallelism is the maximum (significant) degree of parallelism. Assuming that the time required for all the processes is equal, FIG.
In the operation scenario of (b), three threads have the maximum degree of parallelism, and the number of steps in that case is 6 and 7, respectively.
This is shown in FIG. Operation scenario 2 shown in FIG.
It can be seen that the execution position of the process B is shifted behind the operation scenario 1 due to the resource sharing of the process D and the process B.

The examples shown in FIGS. 9 and 10 are based on the process that almost all processes can be executed irrespective of hardware. However, actually, the processes that can be executed are determined for each hardware in many cases. . In this case, the processing is executed sequentially as shown in FIG.
The pipeline is executed as shown in FIG. FIG. 11 (a)
In FIG. 11A, the processing from processing A to processing Z is sequentially executed, and the total processing time is calculated as shown in FIG.
Length. In FIG. 11B, these processes are executed in a pipeline, but the time interval of the stage requires the most time among the processes.

Here, if there is a combination of processes that cannot be executed in parallel because resources are shared as in FIG. 8B, the execution method is as shown in FIG. In FIG. 12, it is assumed that the process C and the process E share resources. This indicates that the time interval of each stage needs to be longer than at least the sum of the processing times of the processing C and the processing E.

The operation scenario and the method of estimating the processing time using the operation scenario have been described with reference to FIGS. 8 to 12. If it is assumed that the processing time of each module is constant based on these descriptions, For example, it is apparent that the maximum parallelism, the minimum processing time, the time intervals of the stages of the pipeline, the order of processing, and the like can be obtained even when resources are shared between modules by using the operation scenario.

Next, a method of obtaining the average value of the power consumption will be described.

When the hardware and software for mounting each functional module are determined, the power consumption can also be determined. Now, it is assumed that the power consumption of the thirteen functional modules executed in the operation scenario of FIG. 8A is represented as shown in FIG. In FIG. 13, the power consumption of each functional module is represented by the length in the Y-axis direction, and the processing time is represented by the length in the X-axis direction.

Here, when the processing proceeds in the order as shown in FIG. 14A, the power consumption changes as shown in FIG. 14B. In the processing order of FIG. 14A, the execution timings of the processes 4, 6, 7, 9, and C can be shifted, and the ranges thereof are 4, 6, 7, C, and 9 respectively.
Can be represented by Therefore, the power consumption when the processing order of FIG. 14A is changed to that of FIG.
(B). In FIG. 15A, the execution start of the processes 4, 6, 7, and 9 is delayed. The maximum value b of the power consumption shown in FIG. 15B is lower than the power consumption a shown in FIG.

As described above, according to the above method, if the hardware and software which are the implementations of the respective function modules are determined and the execution order is determined by the operation scenario, the maximum value of the power consumption can be estimated. If there is a degree of freedom in the execution order, the maximum value of power consumption can be minimized.

Next, a description will be given of a method of estimating the bus access frequency when the mounting of the functional module and the type of the bus are determined.

Now, the system architecture is shown in FIG.
It is assumed that the format is as shown in (a) and (b). FIG.
(A) shows CPU and memory (Mem) on one global bus,
This is a form in which dedicated hardware (HW) is connected, and is the simplest system architecture. In FIG. 16B, a CPU and a memory are connected to a global bus, and separately from this, dedicated hardware and a memory are connected to a local bus. The two buses are connected via a DMA controller (DMAC).

In the system architecture shown in FIG. 16A, it is assumed that the bus access frequency of each functional module is expressed as shown in FIG. In FIG. 17A, it is assumed that 13 functional modules access the global bus at a frequency corresponding to the length in the Y-axis direction based on the operation scenario of FIG. 8A. FIGS. 17 (b) and 17 (c) show the arrangement in accordance with the execution order shown in FIGS. 14 (a) and 15 (a). According to this figure, FIG.
In the execution order shown in (c), the maximum value of the bus access frequency is lower, and accordingly, the bus bandwidth may be narrower.

On the other hand, in the system architecture shown in FIG. 16B, it is assumed that the bus access frequency of each functional module is expressed as shown in FIG. FIG. 18 (a)
Here, it is assumed that thirteen functional modules access the bus at a frequency corresponding to the length in the Y-axis direction based on the operation scenario of FIG. In this bus access, it is assumed that the hatched portion is the bus access for the local bus, and the blank portion above is the bus access for the global bus. FIGS. 18 (b) and 18 (c) show this in a state divided into a global bus and a local bus.

FIG. 19 shows the bus accesses shown in these two figures arranged in accordance with the execution order shown in FIG. 14 (a). FIG. 20 shows an arrangement according to FIG. 15 (a). 19 (a) and 20 (a) show bus access of the global bus, and FIGS. 19 (b) and 20 (b) show bus access of the local bus. 17B and FIG. 17C, when the bus is divided into the global bus and the local bus, the maximum value of the bus access frequency is reduced. The values in FIGS. 20 (a) and (b) arranged according to the execution order are shown in FIGS. 19 (a) and (b) arranged according to FIG. 14 (a).
It turns out that it is smaller than.

As described above, according to the above method, the hardware, software, and system architecture, which are the implementations of the respective functional modules, are determined, and if the execution order is determined by the operation scenario, the maximum value of the bus access frequency is estimated. If the execution order has a degree of freedom, the maximum value of the bus access frequency can be minimized.

As described above, according to the performance evaluation processing according to the embodiment of the present invention, the processing time, the maximum value of the power consumption, and the bus access frequency can be easily obtained based on the operation scenario.

<< Computer-readable recording medium storing circuit design program >> The circuit design method according to the embodiment of the present invention may be programmed and stored in a computer-readable recording medium. Then, when performing the circuit design processing, the recording medium is read into a computer system, the program is stored in a storage unit such as a memory in the computer system, and the circuit design program is executed by an arithmetic unit, thereby realizing the present invention. A circuit design device and a method thereof can be realized. Here, the recording medium is
For example, a computer-readable recording medium capable of recording a program such as a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape is included.

[0094] "Experimental Example" below, circuit design method according to an embodiment of the present invention, in particular for further understanding of the performance evaluation process will be described results of performance evaluation tests for the MPEG encoder shown in FIG. 2 ¹ .

The encoder to be evaluated for performance is shown in FIG.
As shown in FIG. 1, a pre-processing module 211 for converting image data and holding the converted data in a frame buffer, a frame buffer 2 for holding a frame currently being processed
12. A motion estimation module 213 that obtains a motion vector by correlating between the currently processed frame and the immediately preceding frame, and a motion compensation module 214 that performs motion compensation on the immediately preceding frame according to the motion vector. A frame buffer 215 for holding the previous frame, a module (−) for taking a difference between the current frame and the previous frame, a DCT operation module 216 for performing a DCT operation on a difference output of the frame, a DCT operation result IDCT operation module 217 that performs inverse operation on IDCT
A module (+) for taking the sum of the calculation result and the immediately preceding frame and storing the sum in a frame buffer, an entropy coding module 218 for entropy coding the DCT calculation result, and multiplexing the motion vector and the coded image information. A multiplexing module 219 for converting the multiplexed information into a bit string, and an output buffer 221 for outputting the bit string converted information at a predetermined timing.

In this experiment, it is assumed that the encoder shown in FIG. 21 operates according to the operation scenario shown in FIG. In this operation scenario, it is assumed that the operations for taking the difference and the sum of the frames are included in the DCT operation and the IDCT operation, respectively. Here, FIG. 23 shows an arrangement in which the modules are arranged based on the longest path from the start point to the end point of the operation scenario shown in FIG. As can be seen from this figure, there is a certain degree of freedom in the execution timing of the IDCT processing, and the IDCT processing may be performed from the entropy encoding to the multiplexing. Therefore, in the following, FIG.
As shown in FIG. 4, the performance evaluation is performed assuming that the IDCT processing is performed between the DCT operation and the entropy coding.

First, an algorithm architecture database for performing performance evaluation will be described. The architecture assumed in this database is one in which a CPU, a memory, and a hardware module are connected to one bus as shown in FIG. 25A, or one as shown in FIG. CPU and hardware modules are connected to a local bus and a global bus, respectively. In the following description, performance evaluation is performed on the architecture shown in FIG. 25A, but it is needless to say that performance evaluation can be performed on the architecture shown in FIG. 25B by the same method. In the following description of performance evaluation, performance evaluation is performed for the parts except for the preprocessing, and the frame buffer is assumed to require the same amount of hardware regardless of the configuration. Note that it has been removed from

FIGS. 26 and 27 show the contents of the algorithm architecture database.
(B) shows, for each module of the MPEG encoder, the hardware for realizing it, the area required for each software, the processing time represented by the number of clocks, the power consumption per clock, the required memory capacity, and the number of bus accesses FIG. 27 (c) summarizes the area, the maximum clock frequency, the power consumption per clock in idle mode, and the power consumption per clock in active mode for each hardware.

For the motion estimation module shown in FIG. 26A, three hardware modules Me1, Me2, and Me3 can be used, and the evaluation values of those modules are listed in the table. Here, values required for the memory required by the module are divided into a ROM and a RAM. The ROM is further divided into an instruction portion and a data portion, and the RAM is divided into global data and local data. Also, the number of bus accesses is divided into cases where global access is required and cases where local access is sufficient.

It is shown that the compensation module shown in FIG. 26B can be implemented by two hardware modules Mc1 and Mc2, an algorithm executed on the CPU1 or CPU2, and Mc3. Here, in the case of the algorithm executed on the CPU, the area does not include the size of the CPU.

FIG. 26C shows a table for modules for performing DCT and IDCT processing. It can be seen that three types of hardware modules DCT1 to DCT3 or three types of algorithms can be implemented by executing them on the CPU1 or CPU2.

FIG. 26D shows a table of modules for performing the entropy encoding process. It can be seen that two types of hardware modules Code1, Code2 or algorithm Code3 can be implemented by executing them on CPU1 or CPU2.

FIG. 27A shows a table for modules for performing multiplexing processing. Two types of hardware modules Mux1, Mux2 or algorithm Mux3
It can be seen that the implementation can be performed by executing on the PU1 or the CPU2.

FIG. 27B shows a table for modules for performing bit string conversion processing. Two types of hardware modules Bit1, Bit2 or algorithm Bit
3 can be implemented by executing it on the CPU 1 or the CPU 2.

FIG. 27 (c) shows a table summarizing the performances of the hardware memories appearing in the tables of FIGS. 26 to 27 (b). This table summarizes the area of the CPU module that does not appear in FIG. 26 to FIG. 27B, the power consumption of each hardware at idle, the area of the memory, and the power consumption. Note that the area of the memory is a value per byte, and the power consumption is a value per byte when idle, and a value when one byte is accessed once when active. 26 and 27, it is assumed that the bus width is 16 bits and two bytes are accessed at a time.

Referring to the operation scenario shown in FIG. 24, FIG.
The procedure for evaluating the area, the number of processing clocks, the power consumption, and the number of bus accesses in the case of the architecture shown in FIG. 5B based on the algorithms and the architecture database shown in FIGS.

First, an algorithm and an architecture for mounting each module are determined. In the processing flow according to the embodiment of the present invention, the combination of the module, the algorithm, and the architecture is determined by the combination generation processing, and as a result, it is assumed that the combination shown in FIG. 28 is determined. FIG. 28 shows FIG.
7 (b) is a collection of data determined to be used for mounting.

According to the table shown in FIG. 28, the motion estimation
3. Mc2 for motion compensation, D for DCT processing and IDCT processing
CT, entropy coding is Code2, multiplexing is Mu
It can be seen that x3 is executed on the CPU1 and B3 bit string conversion is executed on the CPU1. Also, the CPU 1 which is not included in the item of the algorithm executed on the CPU
The area etc. is added by providing a program item for controlling the entire sequence. Since this table follows the operation scenario shown in FIG. 24, the DCT operation and the IDCT operation can be performed sequentially. Therefore, since static resources for these two modules can be shared, IDCT is set to 0 for area and bus access.

FIG. 29 (a) shows the hardware used in FIG. 28 extracted from FIG. 27 (c). Here, it is assumed that the RAM uses mem2 and the ROM uses rom2. The maximum clock frequency of this MPEG encoder is controlled by DCT1 and is 90 MHz.
It can be seen that it is.

Since the sum of the areas in FIG. 28 does not include the amount related to the memory, FIG. 29B shows the calculated area required for the memory. In FIG. 29A, first, the capacities of the ROM and the RAM are 820, 256, and 5, respectively.
The total area is obtained based on the area per byte in FIG. 29A, as the sum of 760 and 2312.

Next, a method for obtaining power consumption will be described.

Since the power consumption is different between the case where the module is in the idle state and the case where the module is in the active state, it is determined separately for each. First, an example obtained for the memory is shown in FIG. FIG. 30A shows an instruction,
For each memory of data, the capacity and the number of accesses are summarized, and the power consumption at the time of idle and the power consumption at the time of active are obtained and summed. Here, the memory is in an idle state when no access is made, and 1
Assuming one clock is needed per access,
The power consumption is obtained by multiplying the value obtained by subtracting the number of accesses from the total number of execution clocks by the capacity and the power consumption at idle per one access and one byte. The power consumption in the active state is obtained by multiplying the number of accesses by the power consumption in the active state per capacity, one access, and one byte. FIG. 30A shows the sum of the power consumption of the ROM and the RAM when they are idle and when they are active. In FIG. 30 (a), access for ROM and RAM, and access for data and instruction are distinguished. For instruction access, all access is for ROM, and for data access, ROM and RA are based on capacity.
M is apportioned.

Next, FIG. 30B shows a method for obtaining the power consumption of hardware other than the memory.

As in the case of the memory, the number of active clocks for each hardware is obtained, and the value obtained by subtracting the value from the total number of execution clocks and the power consumption per clock at the time of idling is calculated as the consumption at the time of idling. This is power, and the active power consumption is obtained by multiplying the number of active clocks by the power consumption per clock in active mode. The sum of these two is the power consumption for each hardware module, and the sum of them is the power consumption of the hardware modules other than the memory.

The sum of the power consumption of the memory obtained in FIG. 30A and the power consumption of hardware modules other than the memory obtained in FIG. 30B is the total power consumption.

As described above, FIG. 22 to FIG.
According to the performance evaluation processing of the MPEG encoder of FIG. 21 using the system, the target system (FIG. 21), the operation scenario (FIG. 22), the system architecture (FIG. 25), the algorithm, and the architecture database (FIGS. 26 and 27)
However, items necessary for system evaluation, such as area, processing time, maximum value of power consumption, and bus access frequency, can be obtained without a simulation by the same method even if the numbers are different.

<< Effects Obtained from the Circuit Design System and the Method According to the Embodiment of the Present Invention >> According to the circuit design method according to the embodiment of the present invention, the combination of each functional module and the algorithm architecture is determined in advance by static estimation. Because of the narrowing down, the algorithm architecture can be allocated to the functional modules that require an enormous amount of time only by the function level simulation.

In the past, a simulation model was created by generating all combinations from a functional block diagram and a functional model, and a simulation was performed. Therefore, the number of combinations became enormous, and practical time was reduced. Although it was practically impossible to evaluate all combinations within the above, according to the circuit design method according to the embodiment of the present invention, first, the number of combinations was statically evaluated using an operation scenario. Because of the limitation, the search range of the solution is wider than that of the conventional example, and the simulation of the function level is performed for determining the combination, so that the same evaluation accuracy as that of the conventional example can be obtained.

[0119]

According to the circuit design system, the circuit design method, and the computer-readable recording medium storing the circuit design program of the present invention, the mounting method of the functional blocks can be determined in a short time and with high accuracy.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration of a circuit design system according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a circuit design method according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating a candidate creation method according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating a separation determination method according to the embodiment of the present invention.

FIG. 5 is a flowchart illustrating a performance evaluation method according to the embodiment of the present invention.

FIG. 6 is a flowchart illustrating a modified example of the performance evaluation method according to the embodiment of the present invention.

FIG. 7 is a schematic diagram showing an overview of a circuit design system according to an embodiment of the present invention.

FIG. 8 is a schematic diagram showing an operation scenario.

FIG. 9 is a schematic diagram for explaining an operation of executing an operation scenario.

FIG. 10 is a schematic diagram for explaining an operation of executing an operation scenario.

FIG. 11 is a schematic diagram showing a lapse of time when an operation scenario is sequentially executed and a pipeline is executed.

FIG. 12 is a schematic diagram showing a lapse of time when an operation scenario is pipeline-executed when resources are shared.

FIG. 13 is a schematic diagram showing a process execution time and power consumption.

FIG. 14 is a schematic diagram showing an example of transition of three parallel execution timings and power consumption.

FIG. 15 is a schematic diagram showing an example of transition of three parallel execution timings and power consumption.

FIG. 16 is a schematic diagram showing a configuration of a system architecture.

FIG. 17 is a schematic diagram showing bus access frequency and transition of bus access.

FIG. 18 is a schematic diagram showing a bus access frequency.

FIG. 19 is a schematic diagram showing transition of bus access.

FIG. 20 is a schematic diagram showing transition of bus access.

FIG. 21 is a block diagram illustrating a configuration of an MPEG encoder.

FIG. 22 is a diagram illustrating an operation scenario of MPEG encoding.

FIG. 23 is a diagram illustrating execution timing of MPEG encoding.

FIG. 24 is a diagram illustrating execution timing of MPEG encoding.

FIG. 25 is a schematic diagram showing a system architecture of an MPEG encoder.

FIG. 26 is a diagram showing an algorithm for realizing a module and its performance.

FIG. 27 is a diagram showing an algorithm for realizing a module and its performance.

FIG. 28 is a diagram illustrating assignment of hardware and algorithms to each module.

FIG. 29 is a diagram illustrating allocated hardware performance and required memory area.

FIG. 30 is a diagram illustrating power consumption of a memory and power consumption of each hardware.

[Explanation of symbols]

 70 Computer System 71 Display 72 Floppy Disk Drive 73 Floppy Disk 74 Optical Disk Drive 75 Optical Disk 76 Keyboard 77 ROM 78 Cartridge 100 Circuit Design System 110 Circuit Design Device 111 Input / Output Interface 112 Framework Creation Unit 113 Combination Generation Unit 114 Function Level Simulation Unit 115 Performance Evaluation Unit 116 Control Unit 120 Input Unit 121 Output Unit 130 Function Block Diagram Database 131 Function Model Database 132 Algorithm Architecture Database 133 Operation Scenario Database 134 Constraint Condition / Evaluation Function Database 135 Candidate Database 136 Test Vector Database 137 Evaluation Result Database 138 hard Ware / Software Specification Database

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/82 T

Claims (6)

[Claims] 1. A circuit design system for determining a mounting method of a plurality of functional blocks in a circuit to be designed, comprising: a combination of an algorithm and an architecture for realizing each function module; and an algorithm storing results of evaluating the performance of the combination. An architecture database, a combination generation unit that generates all possible combinations of an algorithm and an architecture that realizes each functional module with reference to information stored in the algorithm / architecture database, a constraint condition, an evaluation function, A performance evaluation unit that evaluates the performance of the combination generated by the combination generation unit based on the operation scenario; and stores a combination of an algorithm and an architecture having a predetermined evaluation value or more with reference to the evaluation result of the performance evaluation unit. Weather Circuit design system, characterized by comprising a database. 2. A function model database storing function models related to a combination of an algorithm and an architecture stored in the candidate database; a test vector database storing test vectors used for function level simulation; 2. A function level simulation unit for executing a function level simulation for a combination of an algorithm and an architecture stored in the candidate database with reference to information stored in a test vector database. The circuit design system according to 1. 3. A circuit design method for determining a mounting method of a plurality of function blocks in a circuit to be designed, the method being a combination of an algorithm and an architecture for realizing each function module and a result of evaluating the performance of the combination. Generating all possible combinations of algorithms and architectures for realizing each functional module; evaluating the performance of the generated combinations based on constraints, evaluation functions and operation scenarios; and performance evaluation results. And extracting a combination of an algorithm and an architecture having a predetermined evaluation value or more using a predetermined evaluation value. 4. The method according to claim 1, further comprising the step of executing a function level simulation for a combination of the algorithm and the architecture having a predetermined evaluation value or more by using a function model and a test vector relating to the combination of the algorithm and the architecture. Item 3. The circuit design method according to Item 3. 5. A computer-readable recording medium storing a circuit design program for determining a mounting method of a plurality of functional blocks in a circuit to be designed, comprising: a combination of an algorithm and an architecture for realizing each functional module; The process of generating all possible combinations of algorithms and architectures that realize each functional module using the results of performance evaluation, and the performance of the generated combinations based on constraints, evaluation functions, and operation scenarios A circuit design program characterized by including a process of evaluating, and a process of extracting a combination of an algorithm and an architecture having a predetermined evaluation value or more using a performance evaluation result, and causing a computer to execute these processes. Stored computer-readable records Medium. 6. A process for executing a function level simulation for a combination of an algorithm and an architecture having a predetermined evaluation value or more using a functional model and a test vector relating to a combination of an algorithm and an architecture, and executing this process on a computer. A computer-readable recording medium storing the circuit design program according to claim 5.