TWI809730B - Appratus and method for performing multiple tests on a device under test - Google Patents

Abstract

An apparatus and a method for performing multiple tests on a device under test (DUT) are provided. The apparatus includes at least one non-transitory computer-readable medium having stored thereon computer-executable instructions and at least one processor coupled to the at least one non-transitory computer-readable medium. The computer-executable instructions are executable by the at least one processor and cause the apparatus to perform operations of inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

Description

Multiple test device and test method for component to be tested

This application claims priority to US Patent Application Nos. 17/546,475 and 17/546,318 (ie, the priority date is "December 9, 2021"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a multiple testing device and a testing method thereof, in particular to a multiple testing device and a testing method of a device under test (DUT).

After the fabrication of a semiconductor, integrated or electronic component, analyzes or tests may be performed to verify its functionality. The purpose of the analysis is to determine the performance of the semiconductor device under different test patterns and conditions (eg, voltage, current, bit rate, and temperature). For example, this analysis can be used to determine the limits that semiconductor components can withstand under different input signals.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

An embodiment of the present disclosure provides a method for multiple testing of a device under test (DUT), including: inputting a plurality of test patterns into a test device, and continuously executing the plurality of test patterns on the DUT. For each of the test patterns, and corresponding to each of the plurality of test patterns, a corresponding result of the DUT is obtained.

Another embodiment of the present disclosure provides a device for multiple testing DUT, including: at least one non-transitory computer-readable medium storing a computer-executable instruction thereon; and at least one processor associated with the at least one non-transitory computer The readable medium is coupled, wherein the computer-executable instructions are executable by the at least one processor and cause the device to input a plurality of test patterns in a test device; each of the plurality of test patterns is continuously executed on the DUT one; and corresponding to each of the plurality of test patterns, obtaining a corresponding result of the DUT.

Another embodiment of the present disclosure provides a non-transitory computer-readable medium storing computer-executable instructions executed on a computer system for executing a test method to automatically perform multiple tests on a DUT, wherein the The test method includes: inputting a plurality of test patterns in a test device; continuously executing each of the plurality of test patterns on the DUT; and corresponding to each of the plurality of test patterns, obtaining the DUT a corresponding result.

In this disclosure, a test method for executing multiple test patterns and conditions on a DUT is provided. Two or more test patterns can be input at the same time, and are automatically executed sequentially on the DUT. In other words, the two or more test patterns can be executed on the DUT without interruption. In addition, test setup time can be shortened since repeated input of test patterns is not required.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference signs may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference signs.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the original element can be directly connected or coupled to the other element or to other intervening elements.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections, but these elements, components, regions, layers or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms unless the context specifically dictates otherwise. It should be further understood that when the words "comprise" and "comprising" are used in this specification, they point out the existence of said features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

It should be noted that "about" the amount of an ingredient, component, or reactant employed to modify the present disclosure refers to variations in numerical quantities that may occur, for example, by typical measurements and liquid handler. In addition, inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used in making compositions or performing methods may produce variations. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Shmoo testing is one of the tests that can be used for semiconductor component analysis or automatic test equipment (ATE). Shmoo testing includes a visual representation (eg, a Shmoo diagram) of a series of results for a semiconductor device. In Shmoo testing, each corresponding result performed on a semiconductor component can result in a pass-fail result or a numerical result (eg, fail count or bit error rate). In current practice, each test pattern and condition is entered and executed sequentially. Therefore, the generation of Shmoo diagrams is quite time-consuming.

FIG. 1 is a schematic diagram illustrating a testing device for a semiconductor device according to some embodiments of the present disclosure. The testing device 10 can be used for failure analysis of a semiconductor device, an integrated device or an electronic device. In some embodiments, the test device 10 can be used for automatic testing of a device under test (DUT) 20 . In some embodiments, the test device 10 may be or include an automatic test equipment (ATE) (eg, Advantest Memory Tester). The testing device 10 can be configured to perform a test on a device under test (eg, a semiconductor device) 20 .

Referring to FIG. 1 , the test apparatus 10 may include a test device 110 , a control device 120 , a computing device 130 and a test load board 140 . In some embodiments, the test device 110 , the control device 120 , the computing device 130 and the test carrier board 140 are electrically connected to each other. For example, the testing device 110 can be electrically connected with the control device 120 . The test equipment 110 can be electrically connected to the test carrier board 140 . The control device 120 can be electrically connected with the computing device 130 .

The test equipment 110 includes one or more modules for testing a semiconductor device, an integrated device and an electronic device. As shown in FIG. 1 , the test equipment 110 includes a direct current (DC) module 111 , a digital module 112 , a precision measurement unit (precision measurement unit, PMU) 113 , and a relay board 114 . The control device 120 can transmit instructions (or commands) to corresponding modules of the test device 110 according to the type (or content) of the commands (or commands).

The DC module 111 can be used to test a DC parameter of semiconductor components, integrated components or electronic components. In one embodiment, the DC module 111 can provide a DC current to a semiconductor component, integrated component or electronic component to be tested. In another embodiment, the DC module 111 can provide a voltage to the semiconductor component, integrated component or electronic component to be tested.

The digital module 112 can be used to test a function of semiconductor components, integrated components or electronic components. In some embodiments, the digital module 112 can be used to provide various signals to the DUT 20 . In some embodiments, the digital module 112 can be used to provide a baseband signal or a radio frequency signal to the DUT 20 .

In some embodiments, the digital module 112 can provide signals with different switching frequencies to the DUT 20 . In some embodiments, the digital module 112 can control a rising edge and a falling edge of the signal provided to the DUT 20 . In some embodiments, the digital module 112 can provide a synchronous or an asynchronous signal to the DUT 20 .

The PMU 113 can be used to test a DC parameter of semiconductor components, integrated components or electronic components. The PMU 113 can provide DC parameters with high accuracy. In some embodiments, PMU 113 may provide a DC parameter with a small magnitude. In some embodiments, the PMU 113 can provide an accurate low DC current. In some embodiments, PMU 113 may provide an accurate voltage with a small magnitude.

The relay panel 114 may provide an electrical connection to the test equipment 110 . In some embodiments, if the number of conductive contacts (pins) of the DUT 20 exceeds the number of test channels that the test equipment 110 can provide, some of the pins can be connected to the same channel through the relay pad 114 . Relay pad 114 may be used to connect different pins to specific test channels of test equipment 110 .

The control device 120 includes a processor 121 , a memory 122 and one or more input and output (I/O) ports 123 .

Processor 121 may include, but is not limited to, for example, a microprocessor, a central processing unit (CPU), an application specific instruction set processor (ASIP), a machine control unit (MCU), a graphics processing unit (GPU) , a physical processing unit (PPU), a digital signal processor (DSP), an image processor, a co-processor, a storage controller, a floating point unit, a network processor, a multi-core processor, a front-end processor and the like.

The memory 122 can be a non-transitory computer readable memory storing a computer executable instruction. In some embodiments, the memory 122 may include, but is not limited to, a random access memory (RAM), such as a static RAM (SRAM) or a dynamic RAM (DRAM). In some embodiments, memory 122 may include a read only memory (ROM). Memory 122 may include a cache (not shown) for storing recently accessed data so that future requests for the data can be serviced more quickly. The data stored in the cache may include the results of earlier calculations by the processor 121 . The data stored in cache memory may include copies of the data stored in memory 122 .

In some embodiments, the processor 121 can be electrically connected to the memory 122 . The processor 121 can be electrically connected to the I/O port 123 . The memory 122 can be electrically connected to the I/O port 123 .

The control device 120 may receive a test profile from the computing device 130 . The control device 120 can generate an instruction and a command according to the test data received from the computing device 130 . The instructions and the commands generated by the control device 120 may be stored in the memory 122 . The test instruction and the command generated by the control device 120 can be transmitted to the test device 110 through the I/O port 123 .

The I/O port 123 can be any computer port capable of sending and receiving data. I/O ports 123 may include, but are not limited to, a Universal Serial Bus (USB) port, an IEEE 1394 port (also known as a FireWire port), a PS/2 port (also known as a mini-DIN port), a serial port ( Also known as RS-232 or communications (COM) port), a parallel port (also known as a printer connection (LPT) port), a small computer system interface (SCSI) port, a 1/8-inch audio mini-jack , an RG-6 coaxial port, or a musical instrument digital interface (MIDI) port.

Computing device 130 includes processor 131 and memory 132 .

Processor 131 may include, but is not limited to, for example, a microprocessor, a central processing unit (CPU), an application specific instruction set processor (ASIP), a machine control unit (MCU), a graphics processing unit (GPU) , a physical processing unit (PPU), a digital signal processor (DSP), an image processor, a co-processor, a storage controller, a floating point unit, a network processor, a multi-core processor, a front-end processor and the like. The processor 131 can be electrically connected with the memory 132 .

The memory 132 can be a non-transitory computer readable memory storing a computer executable instruction. The memory 132 may include, but is not limited to, a random access memory (RAM), such as a static RAM (SRAM) or a dynamic RAM (DRAM). In some embodiments, memory 132 may include a read only memory (ROM). Memory 132 may include a cache memory (not shown) for storing recently accessed data so that future requests for the data can be satisfied more quickly. The data stored in the cache memory may include earlier calculation results of the processor 131 . The data stored in cache memory may include copies of the data stored in memory 132 .

A device under test (DUT) 20 may be mounted on the test carrier 140 . One or more conductive or physical connections exist between DUT 20 and test carrier 140 . In some embodiments, DUT 20 may be a semiconductor device, an integrated circuit or an electronic device. In some embodiments, DUT 20 may be a memory device.

FIG. 2 is a schematic diagram illustrating a device under test (DUT) 20 according to some embodiments of the present disclosure. Referring to FIG. 2, the DUT 20 includes three terminals (or pins). In some embodiments, DUT 20 may include more terminals or fewer terminals. During an analysis or an automated test, one or more test signals and commands may be provided to the DUT 20 . In some embodiments, signal S1 is transmitted to DUT 20 and signal S2 is transmitted to DUT 20 . The DUT 20 can generate an output signal (or feedback signal) W in response to the signal S1 and the signal S2.

In some embodiments, the signal S1 and the signal S2 may be provided to different terminals of the DUT 20 . In some embodiments, the signal S1 and the signal S2 may be provided to the same terminal of the DUT 20 . In some embodiments, the output signal W may be a function of the signal S1 and the signal S2.

In some embodiments, the signal S1 and the signal S2 may include at least one of a voltage signal, a current signal, a bit rate (data rate) and a temperature. In some embodiments, signal S1 and signal S2 may include the same attributes (eg, both signals S1 and S2 are voltage signals). In some embodiments, the signal S1 and the signal S2 may include different attributes. For example, the signal S1 can be a bit rate (clock signal), and the signal S2 can be a voltage signal.

In one embodiment, the signal S1 and the signal S2 can be provided to the DUT 20 simultaneously. For example, the signal S1 and the signal S2 can be provided to the DUT 20 at the same time. In some embodiments, the signal S1 and the signal S2 can be provided to the DUT 20 sequentially. In some embodiments, the signal S1 and the signal S2 may be provided to the DUT 20 at different timings.

FIG. 3A is a visual representation illustrating a series of test results for a DUT according to some embodiments of the present disclosure. Referring to FIG. 3A , visual representation 300a includes a series of test results for DUT 20 displayed in the form of a two-dimensional graph. In some embodiments, visual representation 300a may be referred to as a "Shmoo diagram." Referring to FIG. 3A, a visual representation 300a is provided on an abscissa and an ordinate. The abscissa may represent the signal S1 provided to the DUT 20 . The ordinate may represent the signal S2 provided to the DUT 20 .

Referring to FIG. 3A , a test result 31 is obtained by providing a signal S1 with a value 31_s1 and a signal S2 with a value 31_s2 to the DUT 20 . The test result 32 is obtained by providing the DUT 20 with a signal S1 having a value 32_s1 and a signal S2 having a value 32_s2.

As shown in FIG. 3A , the test result 31 marked "P" indicates that the output signal W meets or satisfies a certain standard of the DUT 20, wherein the output signal W is generated by the DUT 20 in response to the signal S1 having a value of 31_s1 and a value of 31_s2 Signal S2 is generated. That is to say, the DUT 20 can operate under the test pattern and condition including the signal S1 with a value of 31_s1 and the signal S2 with a value of 31_s2.

The test result 32 marked "F" in FIG. 3A indicates that the output signal W fails to meet or fails to meet a certain standard of the DUT 20, wherein the output signal W is generated by the DUT 20 in response to the signal S1 having a value of 32_s1 and a value of 32_s2 The signal S2 is generated. That is to say, under the test pattern and condition including the signal S1 with the value 32_s1 and the signal S2 with the value 32_s2 , the DUT 20 may not operate normally.

Visual representation 300a is generated within parameters. Referring to FIG. 3A , visual representation 300 a is generated by providing DUT 20 with the range of signal S1 and the range of signal S2 . For example, the signal S1 may be a bit rate including multiple frequencies. In some embodiments, the signal S2 may be a voltage signal within a range of voltage values (Volts). It is conceivable that the signal S1 and the signal S2 may be parameters other than voltage, current, bit rate and temperature.

In the embodiment shown in FIG. 3A, 20 different signal S1 values are provided to the DUT 20 during a test period. Additionally, 20 different signal S2 values were provided to the DUT 20 during the test. The combination of these different values of signals S1 and S2 results in four hundred test results for DUT 20 .

Referring to FIG. 3A, there is a virtual edge 33a between the area where all test results are "P" and the area where all test results are "F". After obtaining the virtual edge 33a, an operating region of the DUT 20 under varying parameters (eg, voltage, current, and timing) can be determined. As shown in FIG. 3A, the imaginary edge 33a is along an axis from upper right to lower left. After the four hundred tests in FIG. 3A are completed, a virtual edge 33a can be obtained.

Due to the large number of tests to be performed, the input time of each test pattern and condition including signal S1 and signal S2 will increase significantly. In order to improve test efficiency, all test patterns can be input at one time and executed on DUT 20 automatically. Therefore, the time to generate the Shmoo diagram for a single DUT 20 can be shortened.

FIG. 3B is a visual representation illustrating a series of test results of a DUT according to some embodiments of the present disclosure. The visualization 300b in FIG. 3B is similar to the visualization 300a in FIG. 3A, except that in FIG. 3B the virtual edge 33b is along an axis from top left to bottom right.

Different types of DUTs 20 may result in different visual representations 300b. In some embodiments, different types of signals implemented on DUT 20 may result in different visual representations 300b. In some embodiments, different visual representations 300b may result in different ranges of the signal S1 and the signal S2.

After obtaining the virtual edge 33b, the operating region of the DUT 20 under varying parameters can be determined. As shown in FIG. 3B, the virtual edge 33b can be obtained after four hundred tests are completed.

FIG. 3C is a visual representation illustrating a series of test results of a DUT according to some embodiments of the present disclosure. Visual representation 300c in FIG. 3C is similar to visual representation 300a in FIG. 3A, except that in FIG. 3C virtual edge 33c is not in a linear direction.

As shown in FIG. 3C, a test result 34 representing an "F" may be surrounded by a test result "P". In some embodiments, different visual representations 300c may result in different types of DUTs 20 . In some embodiments, different visual representations 300c may result in different types of signals being implemented on DUT 20 . In some embodiments, different visual representations 300c may result in different ranges of the signal S1 and the signal S2.

After obtaining the virtual edge 33c, the operating region of the DUT 20 under a parameter change can be determined. As shown in FIG. 3C, the virtual edge 33c can be obtained after four hundred tests are completed.

FIG. 4 is a schematic diagram illustrating a schematic diagram of a semiconductor device testing system 400 according to some embodiments of the present disclosure. The test system 400 includes a terminal 450 , registers 401 , 411 , 421 , test patterns (or test conditions) 402 , 412 , 422 , and results 403 , 413 , 423 .

Referring to FIG. 4, the testing system 400 has a terminal 450 for receiving a data. In some embodiments, the profile includes one or more test patterns (or test conditions). In some embodiments, the data may be stored in a memory (not shown in FIG. 4 ). The data in the memory can be transferred to registers 401 , 411 and 421 . The number of scratchpads is unlimited. That is, test system 400 may include one or more registers. This material received from terminal 450 may be transferred to registers 401 , 411 and 421 as shown in FIG. 4 . In some embodiments, each register can store at least one test pattern. For example, the register 401 can store the test pattern 402 . The register 411 can store the test pattern 412 . The register 421 can store the test pattern 422 . In some embodiments, the number of test patterns is unlimited. That is, each register can store one or more test patterns.

Test patterns 402, 412, and 422 can be executed on a DUT. For example, test patterns 402, 412, and 422 may be executed on DUT 20 in FIG. 2 . Each test pattern 402, 412 and 422 may include a signal S1 and a signal S2. In some embodiments, the test patterns 402, 412 and 422 may include the same signal S1 and the same signal S2. In some embodiments, the test patterns 402, 412 and 422 may include different signals S1 and different signals S2. In some embodiments, the test patterns 402, 412 and 422 may include the same signal S1 and different signals S2. The test patterns 402, 412 and 422 may include different signals S1 and the same signal S2.

In some embodiments, the test pattern 402 may include a signal S1 having the same value as the signal S1 of the test pattern 412 . The test pattern 402 may include a signal S1 having a different value than the signal S1 of the test pattern 412 . Likewise, the test pattern 402 may include a signal S2 having the same value as the signal S2 of the test pattern 412 . The test pattern 402 may include a signal S2 having a different value than the signal S2 of the test pattern 412 .

In some embodiments, the test pattern 402 may include a signal S1 having the same value as the signal S1 of the test pattern 422 . The test pattern 402 may include a signal S1 having a different value from the signal S1 of the test pattern 422 . Likewise, the test pattern 402 may include a signal S2 having the same value as the signal S2 of the test pattern 422 . The test pattern 402 may include a signal S2 having a different value than the signal S2 of the test pattern 422 .

In some embodiments, the test pattern 412 may include a signal S1 having the same value as the signal S1 of the test pattern 422 . The test pattern 412 may include a signal S1 having a different value from the signal S1 of the test pattern 422 . Likewise, the test pattern 412 may include a signal S2 having the same value as the signal S2 of the test pattern 422 . The test pattern 412 may include a signal S2 having a different value from the signal S2 of the test pattern 422 .

In response to the test pattern 402 being applied to the DUT, a result 403 for the DUT may be obtained. In response to the test pattern 412 being applied to the DUT, a result 413 for the DUT may be obtained. In response to the test pattern 422 being applied to the DUT, a result 423 for the DUT may be obtained. Results 403, 413 and 423 may be a normal-fail result or a digitized result. In some embodiments, each result 403, 413, and 423 may be a visual representation. After all the results are obtained, an overall visual representation (such as the visual representations in FIGS. 3A , 3B and 3C ) can be generated based on all the results. In some embodiments, the visual representation of the whole may be a Shmoo diagram.

In some embodiments, test patterns 402, 412, and 422 may be automatically executed on the DUT. That is, test patterns 402, 412, and 422 can be executed on the DUT without interruption. Results 403, 413 and 423 may then be obtained in sequence. Since the test patterns 402, 412 and 422 do not need to be repeatedly input, the setup time for the test can be shortened.

FIG. 5 is a schematic diagram illustrating a test system for semiconductor devices of some comparative embodiments of the present disclosure. The test system 500 includes a terminal 550 , registers 501 , 511 , 521 , test patterns (or test conditions) 502 , 512 , 522 , and results 503 , 513 , 523 .

Referring to FIG. 5 , the test system 500 has a terminal 550 for receiving a data. In some embodiments, the profile includes one or more test patterns (or test conditions). In some embodiments, this data may be entered into registers 501 , 511 and 521 . The number of registers in test system 500 is not limited. That is, test system 500 may include one or more registers. As shown in FIG. 5 , the material input from terminal 550 may be transferred to registers 501 , 511 and 521 . In some embodiments, each register can store at least one test pattern. For example, each register can store a test pattern. In some embodiments, the register 501 can store the test pattern 502 . The register 511 can store the test pattern 512 . The register 521 can store the test pattern 522 .

Test patterns 502, 512 and 522 can be executed on a DUT. For example, test patterns 502, 512, and 522 may be sequentially executed on DUT 20 in FIG. 2 . Each test pattern 502, 512 and 522 may include a signal S1 and a signal S2. In some embodiments, the test patterns 502, 512 and 522 may include the same signal S1 and the same signal S2. In some embodiments, the test patterns 502, 512 and 522 may include different signals S1 and different signals S2. In some embodiments, the test patterns 502, 512 and 522 may include the same signal S1 and different signals S2. The test patterns 502, 512 and 522 may include different signals S1 and the same signal S2.

In some embodiments, the test pattern 502 may include a signal S1 having the same value as the signal S1 of the test pattern 512 . The test pattern 502 may include a signal S1 having a different value from the signal S1 of the test pattern 512 . Likewise, the test pattern 502 may include a signal S2 having the same value as the signal S2 of the test pattern 512 . The test pattern 502 may include a signal S2 having a different value than the signal S2 of the test pattern 512 .

In some embodiments, the test pattern 502 may include a signal S1 having the same value as the signal S1 of the test pattern 522 . The test pattern 502 may include a signal S1 having a different value from the signal S1 of the test pattern 522 . Likewise, the test pattern 502 may include a signal S2 having the same value as the signal S2 of the test pattern 522 . The test pattern 502 may include a signal S2 having a different value than the signal S2 of the test pattern 522 .

In some embodiments, the test pattern 512 may include a signal S1 having the same value as the signal S1 of the test pattern 522 . The test pattern 512 may include a signal S1 having a different value from the signal S1 of the test pattern 522 . Likewise, the test pattern 512 may include a signal S2 having the same value as the signal S2 of the test pattern 522 . The test pattern 512 may include a signal S2 having a different value from the signal S2 of the test pattern 522 .

In response to the test pattern 502 being applied to the DUT, a result 503 for the DUT may be obtained. In response to the test pattern 512 being applied to the DUT, a result 513 for the DUT is available. In response to the test pattern 522 being applied to the DUT, a result 523 for the DUT is available. Results 503, 513 and 523 may be a normal-fail result or a digitized result. In some embodiments, each result 503, 513, and 523 may be a visual representation. After all the results are obtained, an overall visual representation (such as the visual representations in FIGS. 3A , 3B and 3C ) can be generated based on all the results. In some embodiments, the visual representation of the whole may be a Shmoo diagram.

Referring to FIG. 5 , in response to the test pattern 502 stored in the register 501 being applied to the DUT, a result 503 may be obtained. After the DUT executes the test pattern 502 , the test pattern 512 will be input into the register 511 . In response to the test pattern 512 stored in the register 511 being applied to the DUT, a result 513 may be obtained. After the test pattern 512 is executed on the DUT, the test pattern 522 will be input into the register 521 . In response to the test pattern 522 stored in the register 521 being applied to the DUT, a result 523 may be obtained.

In some embodiments, the test patterns 502, 512 and 522 may be sequentially input into corresponding registers. Results 503, 513 and 523 may then be obtained in sequence. Test patterns 502, 512 and 522 can only be entered after the previous test pattern has been completed. For example, test pattern 512 may be entered after test pattern 502 is completed. Likewise, the test pattern 522 may be input after the test pattern 512 is completed. The test patterns 502, 512 and 522 are repeatedly input. Therefore, testing system 500 will take more setup time. Compared with the test system 500 in FIG. 5 , the test system 400 in FIG. 4 can automatically execute the test patterns 402 , 412 and 422 on the DUT without interruption. Therefore, according to the test system 400, it is possible to shorten the setup time of the test without repeatedly inputting test patterns.

FIG. 6 is a flowchart illustrating a test method 600 for performing multiple tests on a DUT according to some embodiments of the present disclosure. Testing method 600 includes operations 601 , 602 , 603 and 604 . The method of operation 600 may be operated by the testing apparatus 10 shown in FIG. 1 .

In operation 601, one or more test patterns may be input into a test device. In some embodiments, the one or more test patterns are input simultaneously. As shown in FIG. 4 , the one or more test patterns 402 , 411 and 412 may be input to terminal 450 at the same time. In some embodiments, each test pattern may include two signals (such as signal S1 and signal S2 in FIG. 2 ). The test pattern may include at least one of a voltage, a current, a bit rate and a temperature. In some embodiments, the testing device may be an ATE. In some embodiments, the test device may include one or more registers for storing the test pattern. That is, each test pattern is stored in a corresponding register. For example, the test pattern 402 is stored in the register 401 . The test pattern 412 is stored in the register 411 . The test pattern 422 is stored in the register 421 .

Before the test pattern can be input to the device, the device must be set up to receive the test pattern. For example, an environmental data, such as the type or range of the test pattern, needs to be registered in the device.

In operation 602, each test pattern is automatically executed on a DUT. In some embodiments, each test pattern is automatically executed sequentially on the DUT (DUT 20 shown in FIG. 2 ). In other words, the test pattern is continuously executed on the DUT. In current practice, a test pattern can only be entered after a previous test pattern has been completed. Relatively speaking, the present disclosure does not need to repeatedly input test patterns, thus shortening the test setup time.

In operation 603, corresponding to each test pattern, a corresponding result of the DUT may be obtained. The corresponding result can be a normal-failure result or a digitized result. In some embodiments, the corresponding result may be a visual representation. In some embodiments, each test pattern includes two signals (such as signal S1 and signal S2 in FIG. 2 ), therefore, the DUT will generate a corresponding result in response to the signals included in each test pattern. Referring back to FIG. 4 , in response to the test pattern 402 being applied to the DUT, a result 403 for the DUT may be obtained. In response to the test pattern 412 being applied to the DUT, a result 413 for the DUT may be obtained. In response to the test pattern 422 being applied to the DUT, a result 423 for the DUT may be obtained.

In operation 604, a Shmoo graph may be generated from all corresponding results. After all the results are obtained, an overall visual representation (such as the visual representations in FIGS. 3A , 3B and 3C ) can be generated based on all the results. In some embodiments, the visual representation of the whole may be a Shmoo diagram. In some embodiments, the Shmoo diagram is a two-dimensional (2D) diagram. The operating region of the DUT under a parameter change can be determined from the Shmoo diagram.

An embodiment of the present disclosure provides a method for multiple testing of a device under test (DUT), including: inputting a plurality of test patterns into a test device, and continuously executing the tests in the plurality of test patterns on the DUT. Each, and corresponding to each of the plurality of test patterns, a corresponding result of the DUT is obtained.

Another embodiment of the present disclosure provides a device for multiple testing DUT, including: at least one non-transitory computer-readable medium storing a computer-executable instruction thereon; and at least one processor associated with the at least one non-transitory computer The readable medium is coupled, wherein the computer-executable instructions are executable by the at least one processor and cause the device to input a plurality of test patterns in a test device; each of the plurality of test patterns is continuously executed on the DUT one; and corresponding to each of the plurality of test patterns, obtaining a corresponding result of the DUT.

Another embodiment of the present disclosure provides a non-transitory computer-readable medium storing computer-executable instructions executed on a computer system for executing a test method to automatically perform multiple tests on a DUT, wherein the The test method includes: inputting a plurality of test patterns in a test device; continuously executing each of the plurality of test patterns on the DUT; and corresponding to each of the plurality of test patterns, obtaining the DUT a corresponding result.

In this disclosure, a test method for executing multiple test patterns and conditions on a DUT is provided. Two or more test patterns can be input at the same time, and are automatically executed sequentially on the DUT. In other words, the two or more test patterns can be executed on the DUT without interruption. In addition, test setup time can be shortened since repeated input of test patterns is not required.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the patent claims disclosed. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

10: Test device 20: Device under test (DUT) 31: Test results 32: Test results 33a: Virtual Edge 33b: Virtual Edge 33c: Virtual Edge 34: Test results 110: Test equipment 111: Direct current (DC) module 112:Digital module 113: Precision Measurement Unit (PMU) 114: Relay panel 120: Control equipment 121: Processor 122: memory 123: Input and output (I/O) port 130: Computing equipment 131: Processor 132: Memory 140: Test carrier board 300a: Visual representation 300b: Visual representation 300c: Visual Representation 400: Test System 401: scratchpad 402: Test pattern 403: result 411: scratchpad 412: Test pattern 413: result 421: scratchpad 422: Test pattern 423: result 450: terminal 500: test system 501: scratchpad 502: Test pattern 503: result 511: scratchpad 512: Test pattern 513: result 521: scratchpad 522: Test pattern 523: result 550: terminal 600: Test method 601: Operation 602: Operation 603: Operation 604: Operation P: normal F: failure S1: signal S2: signal W: output signal

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components. FIG. 1 is a schematic diagram illustrating a testing device for a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram illustrating a device under test (DUT) of some embodiments of the present disclosure. FIG. 3A is a visual representation illustrating a series of test results for a DUT according to some embodiments of the present disclosure. FIG. 3B is a visual representation illustrating a series of test results of a DUT according to some embodiments of the present disclosure. FIG. 3C is a visual representation illustrating a series of test results of a DUT according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram illustrating a test system for semiconductor devices according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram illustrating a test system for semiconductor devices of some comparative embodiments of the present disclosure. FIG. 6 is a flowchart illustrating a test method for performing multiple tests on a DUT according to some embodiments of the present disclosure.

400: Test System 401: scratchpad 402: Test pattern 403: result 411: scratchpad 412: Test pattern 413: result 421: scratchpad 422: Test pattern 423: result 450: terminal

Claims (18)

A device for multiple testing of a device under test (DUT), comprising: at least one non-transitory computer-readable medium storing a computer-executable instruction thereon; and at least one processor, and the at least one non-transitory A computer-readable medium is coupled, wherein the computer-executable instructions can be executed by the at least one processor, and cause the device to perform the following operations: input a plurality of test patterns into the device, and the plurality of test patterns are simultaneously input And each of the plurality of test patterns is stored in a corresponding register; the plurality of test patterns are continuously executed on the DUT; and corresponding to each of the plurality of test patterns, the DUT is obtained a corresponding result. The device according to claim 1, wherein the corresponding result is a visual representation. The device as claimed in claim 1 further includes generating a Shmoo diagram according to the corresponding results. The device according to claim 3, wherein the Shmoo graph is a 2-dimensional graph. The device as claimed in claim 1, wherein the device is an automatic test equipment (ATE). The device as claimed in claim 1, wherein each of the plurality of test patterns includes at least one of a voltage, a current, a bit rate (data rate) and a temperature. A method for multiple testing of a device under test (DUT), comprising: inputting a plurality of test patterns in a test device, the plurality of test patterns are simultaneously input and each of the plurality of test patterns is stored in a in the corresponding register; continuously execute the plurality of test patterns on the DUT; and obtain a corresponding result of the DUT corresponding to each of the plurality of test patterns. The multiple testing method as claimed in claim 7, wherein the corresponding result is a visual representation. The multiple testing method as described in Claim 7 further includes generating a Shmoo diagram according to the corresponding results. The multiple testing method as claimed in claim 9, wherein the Shmoo graph is a 2-dimensional graph. The multiple testing method as claimed in item 7, wherein the testing device is an automatic test equipment (ATE). The multiple testing method as claimed in claim 7, wherein each of the plurality of test patterns includes at least one of a voltage, a current, a bit rate (data rate) and a temperature. A non-transitory computer-readable medium storing a computer-executable instruction executed on a computer system for executing a test method to perform multiple tests on a device under test (DUT), wherein the The test method includes: inputting a plurality of test patterns in a test device, the plurality of test patterns are input simultaneously and each of the plurality of test patterns is stored in a corresponding register; the DUT is continuously executed the plurality of test patterns; and corresponding to each of the plurality of test patterns, obtaining a corresponding result of the DUT. The non-transitory computer readable medium as claimed in claim 13, wherein the corresponding result is a visual representation. The non-transitory computer readable medium as claimed in claim 13 further comprises generating a Shmoo graph according to the corresponding results. The non-transitory computer readable medium of claim 15, wherein the Shmoo graph is a 2-dimensional graph. The non-transitory computer-readable medium as claimed in claim 13, wherein the testing device is an automatic test equipment (ATE). The non-transitory computer readable medium as claimed in claim 13, wherein each of the plurality of test patterns includes at least one of a voltage, a current, a data rate and a temperature.

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