TWI774510B - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

Info

Publication number
TWI774510B
TWI774510B TW110129532A TW110129532A TWI774510B TW I774510 B TWI774510 B TW I774510B TW 110129532 A TW110129532 A TW 110129532A TW 110129532 A TW110129532 A TW 110129532A TW I774510 B TWI774510 B TW I774510B
Authority
TW
Taiwan
Prior art keywords
transistor
electrostatic discharge
power rail
protection circuit
resistor
Prior art date
Application number
TW110129532A
Other languages
Chinese (zh)
Other versions
TW202308098A (en
Inventor
吳乃聖
王昭龍
林佳龍
Original Assignee
華邦電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 華邦電子股份有限公司 filed Critical 華邦電子股份有限公司
Priority to TW110129532A priority Critical patent/TWI774510B/en
Application granted granted Critical
Publication of TWI774510B publication Critical patent/TWI774510B/en
Publication of TW202308098A publication Critical patent/TW202308098A/en

Links

Images

Landscapes

  • Emergency Protection Circuit Devices (AREA)
  • Burglar Alarm Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electrostatic discharge protection circuit includes a first resistor, a first transistor, a second resistor and a second transistor. The first resistor has a first end coupled to a first power rail. The first transistor has a first end coupled the first power rail, and a control end of the first transistor is coupled to a second end of the first resistor. The second resistor is coupled between a second end of the transistor and a second power rail. The second transistor has a first end coupled to the power rail, a control end of the second transistor is coupled a second end of the first transistor, and a second end of the second transistor is coupled to the second power rail.

Description

靜電放電防護電路Electrostatic discharge protection circuit

本發明是有關於一種靜電放電防護電路，且特別是有關於一種可提升靜電放電電晶體的導通效率的靜電放電防護電路。The present invention relates to an electrostatic discharge protection circuit, and in particular, to an electrostatic discharge protection circuit that can improve the conduction efficiency of an electrostatic discharge transistor.

在習知技術領域中，為確保積體電路不受到靜電放電現象而發生破壞，常在積體電路中加入靜電放電防護電路，以提供靜電放電電流的宣洩路徑，並防止電路元件遭到破壞。在電源軌線間，習知技術常設置電源箝制（power clamp）電路以作為靜電放電防護電路。In the prior art, in order to ensure that the integrated circuit is not damaged by electrostatic discharge, an electrostatic discharge protection circuit is often added to the integrated circuit to provide a discharge path for electrostatic discharge current and prevent circuit components from being damaged. Between the power rails, a power clamp circuit is often provided as an electrostatic discharge protection circuit in the prior art.

為了有效達到靜電放電防護的效果，如何有效的提升靜電放電電晶體的導通效率是很重要的課題。習知技術常透過設置複雜的觸發電路，並利用觸發電路來因應靜電放電現象的發生來使靜電放電電晶體被導通。這種做法中，由於觸發電路需要佔去多餘的布局面積，而導致電路面積的增加。In order to effectively achieve the effect of electrostatic discharge protection, how to effectively improve the conduction efficiency of the electrostatic discharge transistor is a very important topic. In the prior art, a complex trigger circuit is usually set up, and the trigger circuit is used to respond to the occurrence of the electrostatic discharge phenomenon to make the electrostatic discharge transistor turn on. In this way, since the trigger circuit needs to occupy the redundant layout area, the circuit area is increased.

因此，如何在有限的佈局區域中，有效提升靜電放電電晶體的導通效率，是本領域設計人員的重要課題。Therefore, how to effectively improve the conduction efficiency of the electrostatic discharge transistor in a limited layout area is an important issue for designers in the art.

本發明提供一種靜電放電防護電路，在有限的佈局面積下，可提升靜電放電電晶體的導通效率。The invention provides an electrostatic discharge protection circuit, which can improve the conduction efficiency of the electrostatic discharge transistor under a limited layout area.

本發明的靜電放電防護電路包括第一電阻、第一電晶體、第二電阻以及第二電晶體。第一電阻具有第一端耦接至第一電源軌線。第一電晶體具有第一端耦接至第一電源軌線，第一電晶體的控制端耦接至第一電阻的第二端。第二電阻耦接在第一電晶體的第二端與第二電源軌線間。第二電晶體具有第一端耦接至第一電源軌線，第二電晶體的控制端耦接至第一電晶體的第二端，第二電晶體的第二端耦接至第二電源軌線。The electrostatic discharge protection circuit of the present invention includes a first resistor, a first transistor, a second resistor and a second transistor. The first resistor has a first end coupled to the first power rail. The first transistor has a first terminal coupled to the first power rail, and a control terminal of the first transistor is coupled to the second terminal of the first resistor. The second resistor is coupled between the second end of the first transistor and the second power rail. The second transistor has a first terminal coupled to the first power rail, a control terminal of the second transistor is coupled to a second terminal of the first transistor, and a second terminal of the second transistor is coupled to the second power supply track line.

基於上述，本發明的靜電放電防護電路透過第一電阻的延緩效應來導通第一電晶體，並透過第一電晶體宣洩的靜電放電電流，配合第二電阻以導通第二電晶體。如此一來，作為靜電放電電晶體的第二電晶體可以有效的被導通。在搭配第一電晶體的條件下，靜電放電防護電路的效能可以有效被提升。Based on the above, the ESD protection circuit of the present invention conducts the first transistor through the delaying effect of the first resistor, and conducts the second transistor through the ESD current released by the first transistor and cooperates with the second resistor. In this way, the second transistor, which is an electrostatic discharge transistor, can be effectively turned on. Under the condition of matching the first transistor, the performance of the electrostatic discharge protection circuit can be effectively improved.

請參照圖1，靜電放電防護電路100包括電阻Rp、Rn以及電晶體Mp以及Mn。在本實施例中，電阻Rp、Rn以及電晶體Mp構成觸發電路，電晶體Mn則作為靜電放電的主要元件。電阻Rp的第一端耦接至電源軌線PWL1，電阻Rp的第二端耦接至節點N02並耦接至電晶體Mp的控制端。電晶體Mp的第一端耦接至電源軌線PWL1，電晶體Mp的第二端耦接至節點N01並耦接至電阻Rn的第一端。電阻Rn耦接在電晶體Mp的第二端以及電源軌線PWL2間。Referring to FIG. 1 , the ESD protection circuit 100 includes resistors Rp, Rn, and transistors Mp and Mn. In this embodiment, the resistors Rp, Rn and the transistor Mp constitute a trigger circuit, and the transistor Mn is used as the main component of electrostatic discharge. The first end of the resistor Rp is coupled to the power rail line PWL1, and the second end of the resistor Rp is coupled to the node N02 and to the control end of the transistor Mp. The first end of the transistor Mp is coupled to the power rail line PWL1, and the second end of the transistor Mp is coupled to the node N01 and to the first end of the resistor Rn. The resistor Rn is coupled between the second end of the transistor Mp and the power rail line PWL2.

另一方面，電晶體Mn的第一端耦接至電源軌線PWL1，電晶體Mn的第二端耦接至電源軌線PWL2，電晶體Mn的控制端則耦接至節點N01。On the other hand, the first terminal of the transistor Mn is coupled to the power rail PWL1, the second terminal of the transistor Mn is coupled to the power rail PWL2, and the control terminal of the transistor Mn is coupled to the node N01.

在本實施例中，電源軌線PWL1用以接收操作電源VDD，電源軌線PWL2則用以接收接地電源VSS。另一方面，電晶體Mp為P型電晶體，且電晶體Mn可以為N型電晶體。In this embodiment, the power rail line PWL1 is used for receiving the operation power VDD, and the power rail line PWL2 is used for receiving the ground power VSS. On the other hand, the transistor Mp is a P-type transistor, and the transistor Mn may be an N-type transistor.

在正常工作模式（非靜電放電模式）下，當靜電放電防護電路100所屬的積體電路被正常供應操作電源VDD時，電晶體Mp以及Mn都會是被截止的狀態。此時的靜電放電防護電路100維持關閉，並不影響積體電路的正常運作。另外，在靜電放電模式中，當靜電放電現象發生在電源軌線PWL1時（此時電源軌線PWL2接收接地電源VSS），電源軌線PWL1被施加一快速上升的正脈波。此時，電阻Rp可用以延緩電晶體Mp的控制端（節點N02）上的電壓上升的速度，使電晶體Mp的第一端以及控制端間具有一電壓差，並使電晶體Mp被導通。在此同時，被導通的電晶體Mp可以宣洩靜電放電現象所產生的部分的第一靜電放電電流。In the normal working mode (non-ESD mode), when the integrated circuit to which the ESD protection circuit 100 belongs is normally supplied with the operating power VDD, the transistors Mp and Mn are both turned off. At this time, the ESD protection circuit 100 remains closed, and does not affect the normal operation of the integrated circuit. In addition, in the ESD mode, when the ESD phenomenon occurs on the power rail PWL1 (the power rail PWL2 receives the ground power VSS at this time), the power rail PWL1 is applied with a fast rising positive pulse. At this time, the resistor Rp can be used to delay the rising speed of the voltage on the control terminal (node N02 ) of the transistor Mp, so that there is a voltage difference between the first terminal and the control terminal of the transistor Mp, and the transistor Mp is turned on. At the same time, the turned-on transistor Mp can discharge the part of the first electrostatic discharge current generated by the electrostatic discharge phenomenon.

電晶體Mp所宣洩的第一靜電放電電流可以流通過電阻Rn。電阻Rn則可依據第一靜電放電電流以提升節點N01上的電壓，並使節點N01以及電源軌線PWL2間產生一電壓差。這個電壓差被施加在電晶體Mn的控制端以及第二端間，並使電晶體Mn被導通。The first electrostatic discharge current vented by the transistor Mp may flow through the resistor Rn. The resistor Rn can increase the voltage on the node N01 according to the first electrostatic discharge current, and generate a voltage difference between the node N01 and the power rail PWL2. This voltage difference is applied between the control terminal and the second terminal of the transistor Mn, and the transistor Mn is turned on.

被導通的電晶體Mn可在電源軌線PWL1以及PWL2間形成一電流宣洩路徑，並用以宣洩靜電放電現象所產生的部分的另一部分的第二靜電放電電流。The turned-on transistor Mn can form a current draining path between the power rails PWL1 and PWL2, and is used for draining the second electrostatic discharge current of the other part generated by the electrostatic discharge phenomenon.

在本實施例中，電晶體Mn的通道寬長比可大於電晶體Mp的通道寬長比，而第一靜電放電電流小於第二靜電放電電流。In this embodiment, the channel width to length ratio of the transistor Mn may be greater than the channel width to length ratio of the transistor Mp, and the first electrostatic discharge current is smaller than the second electrostatic discharge current.

附帶一提的，本實施例中，電晶體Mn的通道寬長比可以約為電晶體Mp的8倍，電阻Rn可以為數十歐姆，電阻Rp可以為數百k歐姆。當然，上述的數值只是參考用的數值，設計人員可以依據實際的情況進行電晶體Mn、電晶體Mp、電阻Rp、電阻Rn的電性參數的調整動作，沒有一定的限制。Incidentally, in this embodiment, the channel width to length ratio of the transistor Mn may be about 8 times that of the transistor Mp, the resistance Rn may be several tens of ohms, and the resistance Rp may be hundreds of kohms. Of course, the above values are only for reference. The designer can adjust the electrical parameters of transistor Mn, transistor Mp, resistor Rp, and resistor Rn according to the actual situation, without certain restrictions.

本實施例的靜電放電防護電路100在靜電放電現象發生時，可透過先導通電晶體Mp以宣洩部分的靜電放電電流，並對應靜電放電電流以提升節點N01的電壓來達到快速導通電晶體Mn的效果，並完成靜電放電電流的宣洩動作。本實施例的靜電放電防護電路100的導通效率明顯的被提升，同時可提升靜電放電防護的效果。When the electrostatic discharge phenomenon occurs, the electrostatic discharge protection circuit 100 of this embodiment can discharge part of the electrostatic discharge current by turning on the transistor Mp first, and increase the voltage of the node N01 corresponding to the electrostatic discharge current to achieve the effect of quickly turning on the transistor Mn , and complete the discharge action of electrostatic discharge current. The conduction efficiency of the electrostatic discharge protection circuit 100 of this embodiment is significantly improved, and the effect of electrostatic discharge protection can be improved at the same time.

請參照圖2，靜電放電防護電路200包括電阻Rp、Rn以及電晶體Mn以及Mp。在本實施例中，電阻Rp、Rn以及電晶體Mn構成觸發電路，電晶體Mp則作為靜電放電的主要元件。電阻Rn的第一端耦接至電源軌線PWL1，電阻Rn的第二端耦接至節點N02並耦接至電晶體Mn的控制端。電晶體Mp的第一端耦接至電源軌線PWL1，此外，電晶體Mn的第二端耦接至節點N01並耦接至電阻Rp的第一端。電阻Rp耦接在電晶體Mn的第二端以及電源軌線PWL2間。Referring to FIG. 2 , the ESD protection circuit 200 includes resistors Rp, Rn, and transistors Mn and Mp. In this embodiment, the resistors Rp, Rn and the transistor Mn constitute a trigger circuit, and the transistor Mp is used as the main component of electrostatic discharge. The first end of the resistor Rn is coupled to the power rail line PWL1, and the second end of the resistor Rn is coupled to the node N02 and to the control end of the transistor Mn. The first end of the transistor Mp is coupled to the power rail line PWL1, and the second end of the transistor Mn is coupled to the node N01 and to the first end of the resistor Rp. The resistor Rp is coupled between the second end of the transistor Mn and the power rail line PWL2.

在另一方面，電晶體Mp的第一端耦接至電源軌線PWL1，電晶體Mp的第二端耦接至電源軌線PWL2，電晶體Mp的控制端則耦接至節點N01。On the other hand, the first terminal of the transistor Mp is coupled to the power rail line PWL1, the second terminal of the transistor Mp is coupled to the power rail line PWL2, and the control terminal of the transistor Mp is coupled to the node N01.

在本實施例中，電源軌線PWL1用以接收接地電源VSS，電源軌線PWL2則用以接收操作電源VDD。在另一方面，電晶體Mn為N型電晶體，且電晶體Mp可以為P型電晶體。In this embodiment, the power rail line PWL1 is used for receiving the ground power VSS, and the power rail line PWL2 is used for receiving the operating power VDD. In another aspect, the transistor Mn is an N-type transistor, and the transistor Mp may be a P-type transistor.

在正常工作模式（非靜電放電模式）下，當靜電放電防護電路200所屬的積體電路被正常供應操作電源VDD時，電晶體Mp以及Mn都會是被截止的狀態。此時的靜電放電防護電路200維持關閉，並不影響積體電路的正常運作。另外，在靜電放電模式中，當靜電放電現象發生在電源軌線PWL1時（此時電源軌線PWL2接收接地電源VSS），電源軌線PWL1被施加一快速上升的正脈波。此時，電阻Rn可用以延緩電晶體Mn的控制端（節點N02）上的電壓上升的速度，使電晶體Mn的第一端以及控制端間具有一電壓差，並使電晶體Mn被導通。在此同時，被導通的電晶體Mn可以宣洩靜電放電現象所產生的部分的第一靜電放電電流。In the normal working mode (non-ESD mode), when the integrated circuit to which the ESD protection circuit 200 belongs is normally supplied with the operating power VDD, the transistors Mp and Mn are both turned off. At this time, the electrostatic discharge protection circuit 200 remains closed, and does not affect the normal operation of the integrated circuit. In addition, in the ESD mode, when the ESD phenomenon occurs on the power rail PWL1 (the power rail PWL2 receives the ground power VSS at this time), the power rail PWL1 is applied with a fast rising positive pulse. At this time, the resistor Rn can be used to delay the speed of the voltage rise on the control terminal (node N02 ) of the transistor Mn, so that there is a voltage difference between the first terminal and the control terminal of the transistor Mn, and the transistor Mn is turned on. At the same time, the turned-on transistor Mn can discharge a portion of the first electrostatic discharge current generated by the electrostatic discharge phenomenon.

電晶體Mn所宣洩的第一靜電放電電流可以流通過電阻Rp。電阻Rp則可依據第一靜電放電電流以在節點N01以及電源軌線PWL2間產生一電壓差。這個電壓差可以使電晶體Mp的控制端的電壓下降，並使電晶體Mp被導通。The first electrostatic discharge current vented by the transistor Mn may flow through the resistor Rp. The resistor Rp can generate a voltage difference between the node N01 and the power rail PWL2 according to the first electrostatic discharge current. This voltage difference can cause the voltage of the control terminal of the transistor Mp to drop and make the transistor Mp turn on.

被導通的電晶體Mp可在電源軌線PWL1以及PWL2間形成一電流宣洩路徑，並用以宣洩靜電放電現象所產生的部分的另一部分的第二靜電放電電流。The turned-on transistor Mp can form a current draining path between the power rails PWL1 and PWL2, and is used for draining the second electrostatic discharge current of another part generated by the electrostatic discharge phenomenon.

在本實施例中，電晶體Mp的通道寬長比可大於電晶體Mn的通道寬長比，而第一靜電放電電流小於第二靜電放電電流。In this embodiment, the channel width to length ratio of the transistor Mp may be greater than the channel width to length ratio of the transistor Mn, and the first electrostatic discharge current is smaller than the second electrostatic discharge current.

與圖1的實施例相類似的，本實施例的靜電放電防護電路200在靜電放電現象發生時，可先導通電晶體Mn以進行部分的靜電放電電流的宣洩動作。接著，對應部分的靜電放電電流，電晶體Mp可快速的被導通，並完成全部的靜電放電電流的宣洩動作。靜電放電防護電路200的動作效率有效被提升，並可有效提升靜電放電的防護層級。Similar to the embodiment of FIG. 1 , the ESD protection circuit 200 of the present embodiment can first turn on the transistor Mn to perform part of the discharge action of the ESD current when the ESD phenomenon occurs. Then, corresponding to the electrostatic discharge current of the part, the transistor Mp can be quickly turned on, and the discharge action of the entire electrostatic discharge current is completed. The operation efficiency of the electrostatic discharge protection circuit 200 is effectively improved, and the protection level of electrostatic discharge can be effectively improved.

接著請同時參照圖1、圖3以及圖4，在圖3中，靜電放電脈波ESDP被施加在電源軌線PWL1上，並在時間點t1，節點N02的電壓V(N02)隨著靜電放電脈波ESDP開始上升。基於電阻Rp的作用，節點N02的電壓V(N02)的上升速度緩於靜電放電脈波ESDP的上升速度。據此，電晶體Mp的控制端（節點N02）以及第一端（電源軌線PWL1）間可具有一負的電壓差，並使電晶體Mp被導通。Next, please refer to FIG. 1, FIG. 3 and FIG. 4 at the same time. In FIG. 3, the electrostatic discharge pulse ESDP is applied to the power rail PWL1, and at the time point t1, the voltage V(N02) of the node N02 follows the electrostatic discharge. The pulse ESDP starts to rise. Due to the action of the resistor Rp, the rising speed of the voltage V(N02) of the node N02 is slower than the rising speed of the electrostatic discharge pulse wave ESDP. Accordingly, there may be a negative voltage difference between the control terminal (node N02 ) and the first terminal (power rail line PWL1 ) of the transistor Mp, and the transistor Mp is turned on.

被導通的電晶體Mp可提供電流宣洩路徑，並使靜電放電電流流通過電阻Rn，且使節點N01上的電壓V(N01)上升。電晶體Mn可依據快速上升的節點N01上的電壓V(N01)而在時間點t1被導通，並進行靜電放電電流的宣洩動作。隨著電晶體Mn的靜電放電電流的宣洩動作，流通電阻Rn的電流減小，節點N01上的電壓V(N01)隨之下降，並在時間點t2下降至小於電晶體Mn的臨界電壓（例如等於0.32伏特）。The turned-on transistor Mp can provide a current drain path and allow the ESD current to flow through the resistor Rn, and increase the voltage V(N01) on the node N01. The transistor Mn can be turned on at the time point t1 according to the rapidly rising voltage V(N01) on the node N01, and perform the discharge action of the electrostatic discharge current. With the discharge action of the electrostatic discharge current of the transistor Mn, the current of the flow resistance Rn decreases, and the voltage V(N01) on the node N01 decreases accordingly, and at the time point t2, it drops to less than the threshold voltage of the transistor Mn (for example, equal to 0.32 volts).

在圖3中，在時間點t1後，節點N01上的電壓V(N01)可快速上升至電壓Vgsm，此時電源軌線PWL1上的電壓（等於靜電放電脈波ESDP的峰值電壓）與電壓Vgsm的電壓差保持可以使電晶體Mp維持導通的狀態。在本實施中，電壓Vgsm約等於7.1伏特。In Figure 3, after time point t1, the voltage V(N01) on the node N01 can rapidly rise to the voltage Vgsm, at this time the voltage on the power rail PWL1 (equal to the peak voltage of the electrostatic discharge pulse ESDP) and the voltage Vgsm The voltage difference can keep the transistor Mp in a conductive state. In this implementation, the voltage Vgsm is approximately equal to 7.1 volts.

值得一提的，在圖3的實施例中，電晶體Mn在時間點t1至t2維持被導通的狀態。也就是說，電晶體Mn約維持被導通數十個奈秒（ns）。It is worth mentioning that, in the embodiment of FIG. 3 , the transistor Mn maintains a turned-on state from time points t1 to t2 . That is, the transistor Mn remains on for about tens of nanoseconds (ns).

在圖4中，曲線I1表示電源軌線PWL1上的電流；曲線I2表示通過電晶體Mp的電流；曲線I3則表示通過電晶體Mn的電流。在時間點t1，基於電晶體Mp被導通，曲線I2被拉高。對應被拉高的曲線I2，電晶體Mn被導，並使曲線I1、I3同步快速的被拉高。隨著靜電放電脈波ESP能量的削減，曲線I1、I3同步下降。並在時間點t2，對應電晶體Mn被截止，曲線I1、I3可趨近於0安培。In FIG. 4, the curve I1 represents the current on the power rail PWL1; the curve I2 represents the current through the transistor Mp; and the curve I3 represents the current through the transistor Mn. At time point t1, the curve I2 is pulled high based on the transistor Mp being turned on. Corresponding to the pulled-up curve I2, the transistor Mn is conducted, and the curves I1 and I3 are pulled up rapidly and synchronously. With the reduction of the energy of the electrostatic discharge pulse ESP, the curves I1 and I3 decrease synchronously. And at the time point t2, the corresponding transistor Mn is turned off, and the curves I1 and I3 can approach 0 ampere.

值得一提的，在本發明實施例中，（以圖1實施例為範例）基於電晶體Mn以及Mp的尺寸為一大一小，電阻Rp以及Rn的尺寸為一大一小，因此在佈局時，可如圖5繪示的本發明實施例的靜電放電防護電路的佈局區域的配置示意圖，來選擇使電晶體Mn以及電阻Rn設置在同一行，並使電晶體Mp以及電阻Rp設置在相同的另一行。如此，可有效降低佈局所需的面積。It is worth mentioning that in the embodiment of the present invention (taking the embodiment in FIG. 1 as an example), the sizes of the transistors Mn and Mp are one large and one small, and the sizes of the resistors Rp and Rn are one large and one small. Therefore, in the layout When the configuration diagram of the layout area of the electrostatic discharge protection circuit according to the embodiment of the present invention is shown in FIG. 5, the transistor Mn and the resistor Rn can be set in the same row, and the transistor Mp and the resistor Rp can be set in the same row. another line of . In this way, the area required for layout can be effectively reduced.

綜上所述，本發明的靜電放電防護電路利用一電晶體以及二電阻來形成觸發電路，並在靜電放電現象發生時，透過觸發電路的作用來導通靜電放電電晶體。如此一來，靜電放電電晶體可以因應靜電放電現象快速的被導通，有效提升積體電路的靜電放電防護的等級。To sum up, the ESD protection circuit of the present invention uses a transistor and two resistors to form a trigger circuit, and when an ESD phenomenon occurs, the ESD transistor is turned on through the action of the trigger circuit. In this way, the electrostatic discharge transistor can be quickly turned on in response to the electrostatic discharge phenomenon, which effectively improves the level of electrostatic discharge protection of the integrated circuit.

100、200:靜電放電防護電路 ESDP:靜電放電脈波 I1~I3:曲線 Mp、Mn:電晶體 N01、N02:節點 PWL1、PWL2:電源軌線 Rp、Rn:電阻 t1、t2:時間點 V(N01)、V(N02)、Vgsm:電壓 VDD:操作電源 VSS:接地電源 100, 200: Electrostatic discharge protection circuit ESDP: Electrostatic Discharge Pulse I1~I3: Curve Mp, Mn: Transistor N01, N02: Node PWL1, PWL2: Power rail lines Rp, Rn: resistance t1, t2: time point V(N01), V(N02), Vgsm: Voltage VDD: operating power VSS: Ground Power

圖1繪示本發明一實施例的靜電放電防護電路的示意圖。 圖2繪示本發明另一實施例的靜電放電防護電路的示意圖。 圖3以及圖4分別繪示本發明圖1實施例的靜電放電防護電路100在靜電放電現象中的節點電壓波形以及節點電流波形。 圖5繪示本發明實施例的靜電放電防護電路的佈局區域的配置示意圖。 FIG. 1 is a schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention. FIG. 3 and FIG. 4 respectively illustrate the node voltage waveform and the node current waveform of the ESD protection circuit 100 of the embodiment of FIG. 1 in the ESD phenomenon. FIG. 5 is a schematic diagram illustrating the configuration of a layout area of an ESD protection circuit according to an embodiment of the present invention.

100:靜電放電防護電路 100: Electrostatic discharge protection circuit

Rp、Rn:電阻 Rp, Rn: resistance

Mp、Mn:電晶體 Mp, Mn: Transistor

PWL1、PWL2:電源軌線 PWL1, PWL2: Power rail lines

N01、N02:節點 N01, N02: Node

VDD:操作電源 VDD: operating power

VSS:接地電源 VSS: Ground Power

Claims (10)

一種靜電放電防護電路，包括：一第一電阻，具有第一端耦接至一第一電源軌線；一第一電晶體，具有第一端耦接至該第一電源軌線，該第一電晶體的控制端耦接至該第一電阻的第二端；一第二電阻，耦接在該第一電晶體的第二端與一第二電源軌線間；以及一第二電晶體，具有第一端耦接至該第一電源軌線，該第二電晶體的控制端耦接至該第一電晶體的第二端，該第二電晶體的第二端耦接至該第二電源軌線，其中該第一電晶體用以宣洩一第一靜電放電電流，該第二電晶體用以宣洩與該第一靜電放電電流不同的一第二靜電放電電流。 An electrostatic discharge protection circuit, comprising: a first resistor having a first end coupled to a first power rail; a first transistor having a first end coupled to the first power rail, the first The control end of the transistor is coupled to the second end of the first resistor; a second resistor is coupled between the second end of the first transistor and a second power rail; and a second transistor, It has a first end coupled to the first power rail, a control end of the second transistor coupled to a second end of the first transistor, and a second end of the second transistor coupled to the second The power rail line, wherein the first transistor is used for discharging a first electrostatic discharge current, and the second transistor is used for discharging a second electrostatic discharge current different from the first electrostatic discharge current. 如請求項1所述的靜電放電防護電路，其中該第一電源軌線用以接收一操作電源，該第二電源軌線用以接收一接地電源。 The electrostatic discharge protection circuit of claim 1, wherein the first power rail is used for receiving an operating power, and the second power rail is used for receiving a ground power. 如請求項2所述的靜電放電防護電路，其中該第一電晶體為P型電晶體，該第二電晶體為N型電晶體。 The electrostatic discharge protection circuit of claim 2, wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor. 如請求項3所述的靜電放電防護電路，其中當一靜電放電現象發生在該第一電源軌線時，該第一電阻延緩該第一電晶體的控制端上的電壓上升的速度，並使該第一電晶體被導通以宣洩該第一靜電放電電流。 The electrostatic discharge protection circuit of claim 3, wherein when an electrostatic discharge phenomenon occurs on the first power rail, the first resistor delays the speed of the voltage rise on the control terminal of the first transistor, and makes The first transistor is turned on to discharge the first electrostatic discharge current. 如請求項4所述的靜電放電防護電路，其中當該靜電放電現象發生在該第一電源軌線時，該第二電阻依據該第一靜電放電電流提升該第二電晶體的控制端上的電壓，並使該第二電晶體被導通以宣洩該第二靜電放電電流。 The electrostatic discharge protection circuit of claim 4, wherein when the electrostatic discharge phenomenon occurs on the first power rail, the second resistor increases the voltage on the control terminal of the second transistor according to the first electrostatic discharge current voltage, and the second transistor is turned on to discharge the second electrostatic discharge current. 如請求項1所述的靜電放電防護電路，其中該第一電源軌線用以接收一接地電源，該第二電源軌線用以接收一操作電源。 The electrostatic discharge protection circuit of claim 1, wherein the first power rail is used for receiving a ground power, and the second power rail is used for receiving an operating power. 如請求項6所述的靜電放電防護電路，其中該第一電晶體為N型電晶體，該第二電晶體為P型電晶體。 The electrostatic discharge protection circuit of claim 6, wherein the first transistor is an N-type transistor, and the second transistor is a P-type transistor. 如請求項7所述的靜電放電防護電路，其中當一靜電放電現象發生在該第一電源軌線時，該第一電阻延緩該第一電晶體的控制端上的電壓上升的速度，並使該第一電晶體被導通以宣洩該第一靜電放電電流。 The electrostatic discharge protection circuit of claim 7, wherein when an electrostatic discharge phenomenon occurs on the first power rail, the first resistor delays the speed of the voltage rise on the control terminal of the first transistor, and makes The first transistor is turned on to discharge the first electrostatic discharge current. 如請求項8所述的靜電放電防護電路，其中當該靜電放電現象發生在該第一電源軌線時，該第二電阻依據該第一靜電放電電流以在該第二電晶體的控制端以及第二端間產生跨壓，並使該第二電晶體被導通以宣洩該第二靜電放電電流。 The electrostatic discharge protection circuit as claimed in claim 8, wherein when the electrostatic discharge phenomenon occurs on the first power rail, the second resistor is connected to the control terminal of the second transistor and the control terminal of the second transistor according to the first electrostatic discharge current. A cross-voltage is generated between the second terminals, and the second transistor is turned on to discharge the second electrostatic discharge current. 如請求項8所述的靜電放電防護電路，其中該第二電晶體的通道寬長比大於該第一電晶體的通道寬長比。 The electrostatic discharge protection circuit of claim 8, wherein the channel width to length ratio of the second transistor is greater than the channel width to length ratio of the first transistor.
TW110129532A 2021-08-10 2021-08-10 Electrostatic discharge protection circuit TWI774510B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW110129532A TWI774510B (en) 2021-08-10 2021-08-10 Electrostatic discharge protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW110129532A TWI774510B (en) 2021-08-10 2021-08-10 Electrostatic discharge protection circuit

Publications (2)

Publication Number Publication Date
TWI774510B true TWI774510B (en) 2022-08-11
TW202308098A TW202308098A (en) 2023-02-16

Family

ID=83807287

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110129532A TWI774510B (en) 2021-08-10 2021-08-10 Electrostatic discharge protection circuit

Country Status (1)

Country Link
TW (1) TWI774510B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200511556A (en) * 2003-03-26 2005-03-16 Taiwan Semiconductor Mfg Co Ltd ESD protection device
TWI264106B (en) * 2002-04-30 2006-10-11 Winbond Electronics Corp Static charge protection circuit of adopting gate-coupled MOSFET (metal-oxide-semiconductor field effect transistor)
TW201042747A (en) * 2009-05-20 2010-12-01 Ind Tech Res Inst Electrostatic discharge clamp circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI264106B (en) * 2002-04-30 2006-10-11 Winbond Electronics Corp Static charge protection circuit of adopting gate-coupled MOSFET (metal-oxide-semiconductor field effect transistor)
TW200511556A (en) * 2003-03-26 2005-03-16 Taiwan Semiconductor Mfg Co Ltd ESD protection device
TW201042747A (en) * 2009-05-20 2010-12-01 Ind Tech Res Inst Electrostatic discharge clamp circuit

Also Published As

Publication number Publication date
TW202308098A (en) 2023-02-16

Similar Documents

Publication Publication Date Title
TWI539708B (en) Electrostatic discharge protection circuit
CN102593122B (en) Semiconductor ESD circuit and method
KR100835282B1 (en) Electrostatic discharge protection device
US10096994B2 (en) Transient-triggered DC voltage-sustained power-rail ESD clamp circuit
US5946175A (en) Secondary ESD/EOS protection circuit
US20070053120A1 (en) Apparatus and method for improved triggering and leakage current control of esd clamping devices
US20040233595A1 (en) ESD protection circuit with tunable gate-bias
US20160149403A1 (en) Electrostatic protection circuit and semiconductor integrated circuit apparatus
US20030201457A1 (en) Gate-coupled MOSFET ESD protection circuit
JPH0282714A (en) Low noise output buffer circuit
CN103633637A (en) Electrostatic discharge protection circuit and protection method
JP3691554B2 (en) Protection circuit for ESD protection
CN112350702A (en) Output stage circuit of high-side power switch
TW202205775A (en) Circuit and method of forming a circuit
TWI521824B (en) Electrostatic discharge protection circuit and voltage regulator chip having the same
CN113839374B (en) ESD power protection circuit, working power supply and chip
TWI774510B (en) Electrostatic discharge protection circuit
CN111355225A (en) Power supply clamping circuit and integrated circuit chip
US7826188B2 (en) Methods, design structures, and systems for current mode logic (CML) differential driver ESD protection circuitry
JP2006515960A (en) Electrostatic discharge circuit and method therefor
US11557896B1 (en) Electrostatic discharge protection circuit
CN115706405A (en) Electrostatic discharge protection circuit
TWI788054B (en) Electrostatic discharge protection circuit
US9379541B2 (en) EOS protection circuit with FET-based trigger diodes
TWI733957B (en) Transient voltage suppressor