TWI773341B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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TWI773341B
TWI773341B TW110119011A TW110119011A TWI773341B TW I773341 B TWI773341 B TW I773341B TW 110119011 A TW110119011 A TW 110119011A TW 110119011 A TW110119011 A TW 110119011A TW I773341 B TWI773341 B TW I773341B
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sealing body
protective film
semiconductor
manufacturing
semiconductor device
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TW202137340A (en
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篠田智則
根本拓
中西勇人
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日商琳得科股份有限公司
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    • C09J201/00—Adhesives based on unspecified macromolecular compounds
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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Abstract

一種半導體裝置的製造方法，其特徵為包含： 將元件背面(W2)朝向黏著劑層，使具有電路面(W1)及前述元件背面(W2)之複數的半導體元件貼著於具有前述黏著劑層的支撐基板(10)的前述黏著劑層之工程； 將被貼著於支撐基板(10)的前述半導體元件密封，而形成密封體(3)之工程； 將外部端子電極形成於密封體(3)，而使被貼著於支撐基板(10)的前述半導體元件與前述外部端子電極電性連接之工程； 在使前述半導體元件與前述外部端子電極電性連接之後，從密封體(3)剝離支撐基板(10)，而使前述半導體元件的元件背面(W2)露出之工程； 在露出的前述半導體元件的元件背面(W2)形成硬化性的保護膜形成層之工程；及 使前述保護膜形成層硬化而形成保護膜之工程。A method of manufacturing a semiconductor device, comprising: The back side of the element (W2) faces the adhesive layer, and the plurality of semiconductor elements having the circuit surface (W1) and the back side of the element (W2) are attached to the adhesive layer of the support substrate (10) with the adhesive layer. project; The process of sealing the aforementioned semiconductor element attached to the support substrate (10) to form a sealing body (3); The process of forming external terminal electrodes on the sealing body (3), and electrically connecting the semiconductor elements attached to the support substrate (10) with the external terminal electrodes; After the semiconductor element is electrically connected to the external terminal electrode, the support substrate (10) is peeled off from the sealing body (3) to expose the element back surface (W2) of the semiconductor element; The process of forming a curable protective film-forming layer on the element back surface (W2) of the exposed semiconductor element; and The process of forming a protective film by hardening the said protective film forming layer.

Description

半導體裝置的製造方法Manufacturing method of semiconductor device

本發明是有關半導體裝置的製造方法。The present invention relates to a method of manufacturing a semiconductor device.

近年來，電子機器的小型化、輕量化、及高機能化進展。被搭載於電子機器的半導體裝置也被要求小型化、薄型化、及高密度化。半導體晶片(有時只稱晶片)是有被安裝於接近其大小的封裝的情形。如此的封裝亦有被稱為晶片規模封裝(Chip Scale Package；CSP)的情形。作為製造CSP的製程之一，可舉晶圓水準封裝(Wafer Level Package；WLP)。在WLP中是在藉由切割來使封裝小片化之前，在晶片電路形成面形成外部電極等，最後切割包含晶片的封裝晶圓，而使小片化。作為WLP是可舉扇入(Fan-In)型及扇出(Fan-Out)型。在扇出型的WLP(以下有時簡稱為FO-WLP)中，以能成為比晶片大小更大的領域之方式，使用密封構件來覆蓋半導體晶片，而形成半導體晶片密封體，不僅半導體晶片的電路面，在密封構件的表面領域中也形成再配線層或外部電極。 例如，在文獻1(日本特開2012-62372號公報)中記載有使用晶片暫時固定用的黏著膠帶的WLP等的製造方法。在文獻1的方法中，藉由將晶片的電路面朝向基板上的黏著膠帶的黏著劑層貼著的方式(有時稱為面朝下方式)來貼著晶片。 在文獻1的方法中，在樹脂密封晶片之後，從藉由樹脂來密封晶片而成的層(有時稱為晶片密封層)剝離黏著膠帶及基板，在露出的電路面形成電極。如此，在文獻1的方法中，由於在晶片電路面形成電極時，晶片密封層是未藉由基板來支撐，因此藉由伴隨密封樹脂的硬化之應力，恐有發生晶片密封層的彎曲之虞。一旦發生晶片密封層的彎曲，則難以在晶片電路面形成再配線層及電極。In recent years, miniaturization, weight reduction, and high functionality of electronic equipment have progressed. Semiconductor devices mounted on electronic equipment are also required to be reduced in size, thin, and dense. Semiconductor wafers (sometimes just called wafers) are those that are mounted in packages that are close to their size. Such a package is also called a chip scale package (Chip Scale Package; CSP). As one of the processes for manufacturing the CSP, a wafer level package (Wafer Level Package; WLP) can be cited. In WLP, external electrodes and the like are formed on the circuit formation surface of the chip before the package is divided into small pieces by dicing, and finally, the package wafer including the chip is diced and divided into small pieces. As the WLP, a fan-in (Fan-In) type and a fan-out (Fan-Out) type can be mentioned. In fan-out type WLP (hereinafter sometimes abbreviated as FO-WLP), a sealing member is used to cover the semiconductor wafer so that the area can be larger than the size of the wafer to form a semiconductor wafer sealing body. On the circuit surface, rewiring layers or external electrodes are also formed in the surface area of the sealing member. For example, Document 1 (Japanese Unexamined Patent Application Publication No. 2012-62372 ) describes a method for producing WLP or the like using an adhesive tape for temporary wafer fixing. In the method of Document 1, the wafer is attached by a method (sometimes referred to as a face-down method) in which the circuit surface of the wafer faces the adhesive layer of the adhesive tape on the substrate. In the method of Document 1, after the wafer is sealed with resin, the adhesive tape and the substrate are peeled off from a layer in which the wafer is sealed with resin (sometimes referred to as a wafer sealing layer), and electrodes are formed on the exposed circuit surface. As described above, in the method of Document 1, since the wafer sealing layer is not supported by the substrate when the electrodes are formed on the circuit surface of the wafer, there is a fear that the wafer sealing layer may warp due to the stress accompanying the hardening of the sealing resin. . Once the wafer sealing layer is warped, it becomes difficult to form a rewiring layer and electrodes on the circuit surface of the wafer.

本發明的目的是在於提供一種可抑制密封體的彎曲之半導體裝置的製造方法。 本發明之一形態的半導體裝置的製造方法的特徵是包含： 將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 在使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 使前述保護膜形成層硬化而形成保護膜之工程。 在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 在形成前述保護膜之後，將前述密封體貼著於第一支撐薄板之工程；及 使被貼著於前述第一支撐薄板的前述密封體小片化之工程。 在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板之前，將前述密封體貼著於第二支撐薄板之工程， 將前述密封體的前述外部端子電極朝前述第二支撐薄板貼著。 在本發明之一形態的半導體裝置的製造方法中，較理想是將前述密封體貼著於前述第二支撐薄板，從前述密封體剝離前述支撐基板之後，在露出的前述半導體元件的前述元件背面形成前述保護膜形成層。 在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 在形成前述保護膜之後，使被貼著於前述第二支撐薄板的前述密封體小片化之工程。 在本發明之一形態的半導體裝置的製造方法中，較理想是更包含： 在形成前述保護膜之後，從前述第二支撐薄板剝離前述密封體，而貼著於第三支撐薄板之工程； 使被貼著於前述第三支撐薄板的前述密封體小片化之工程。 若根據本發明之一形態，則可提供一種能夠抑制密封體的彎曲之半導體裝置的製造方法。An object of the present invention is to provide a method of manufacturing a semiconductor device that can suppress the warpage of the sealing body. A method of manufacturing a semiconductor device according to an aspect of the present invention is characterized by including: The process of attaching the backside of the element to the adhesive layer, and attaching a plurality of semiconductor elements having a circuit surface and the backside of the element on the opposite side of the circuit surface to the adhesive layer of the support substrate with the adhesive layer; The process of sealing the semiconductor element attached to the supporting substrate to form a sealing body; The process of forming external terminal electrodes on the sealing body to electrically connect the semiconductor elements attached to the support substrate and the external terminal electrodes; The process of exposing the back surface of the semiconductor element by peeling off the support substrate from the sealing body after the semiconductor element and the external terminal electrode are electrically connected; The process of forming a curable protective film-forming layer on the back surface of the exposed semiconductor element; The process of forming a protective film by hardening the said protective film forming layer. In one aspect of the present invention, the method for manufacturing a semiconductor device preferably further includes: After forming the protective film, the process of adhering the sealing body to the first support sheet; and The process of making the said sealing body adhered to the said 1st support sheet into small pieces. In one aspect of the present invention, the method for manufacturing a semiconductor device preferably further includes: The process of attaching the sealing body to the second supporting sheet after the semiconductor element and the external terminal electrodes are electrically connected and before peeling the supporting substrate from the sealing body, The said external terminal electrode of the said sealing body is stuck to the said 2nd support sheet. In the method for manufacturing a semiconductor device according to an aspect of the present invention, preferably, the sealing body is adhered to the second support sheet, and the support substrate is peeled from the sealing body, and then formed on the element back surface of the exposed semiconductor element. The aforementioned protective film forms a layer. In one aspect of the present invention, the method for manufacturing a semiconductor device preferably further includes: After forming the protective film, the sealing body attached to the second support sheet is made into small pieces. In one aspect of the present invention, the method for manufacturing a semiconductor device preferably further includes: The process of peeling off the sealing body from the second supporting sheet after forming the protective film and sticking to the third supporting sheet; The process of making the said sealing body adhered to the said 3rd support sheet into small pieces. According to one aspect of the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of suppressing warpage of the sealing body.

[第一實施形態] 以下，說明有關本實施形態的半導體裝置的製造方法。 本實施形態的半導體裝置的製造方法是包含： 將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 在使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 使前述保護膜形成層硬化而形成保護膜之工程； 在形成前述保護膜之後，將前述密封體貼著於第一支撐薄板之工程；及 使被貼著於前述第一支撐薄板的前述密封體小片化之工程。 圖1(圖1A、圖1B及圖1C)、圖2(圖2A、圖2B、圖2C及圖2D)及圖3(圖3A及圖3B)是表示本實施形態的半導體裝置的製造方法之一例的圖。 (半導體晶片貼著工程) 在圖1A及圖1B是表示說明使作為半導體元件的半導體晶片CP貼著於具有黏著劑層的支撐基板10的工程(有時稱為半導體晶片貼著工程)的剖面概略圖。另外，在圖1A是顯示有1個半導體晶片CP，但在本實施形態是如圖1B所示般使複數的半導體晶片CP貼著於黏著劑層。使半導體晶片CP貼著時，亦可使1個1個貼著，或使複數的半導體晶片CP同時貼著。 在本實施形態中，半導體晶片CP會被貼著於兩面黏著薄板20所具備的黏著劑層，該兩面黏著薄板20是被貼著於支撐基板10。 ･兩面黏著薄板 在圖4是表示兩面黏著薄板20的剖面概略圖。 兩面黏著薄板20是具有基材21、第一黏著劑層22及第二黏著劑層23。基材21是具有第一基材面211及與第一基材面211相反側的第二基材面212。 第一黏著劑層22是形成於第一基材面211。 第二黏著劑層23是形成於第二基材面212。 在本實施形態中，半導體晶片CP會被貼著於第一黏著劑層22，第二黏著劑層23會被貼著於支撐基板10。 如圖1所示般，在本實施形態所使用的半導體晶片CP是具有：設有連接端子W3的電路面W1，及與電路面W1相反側的元件背面W2。在本實施形態中，使元件背面W2貼著於第一黏著劑層22。如此，將電路面W1朝上來使貼著於第一黏著劑層22的方式，有時稱為面朝上方式。 第一黏著劑層22是含有黏著劑。在第一黏著劑層22中所含的黏著劑並未特別加以限定，可將各種種類的黏著劑適用於第一黏著劑層22。作為在第一黏著劑層22中所含的黏著劑，例如可舉由橡膠系、丙烯酸系、矽酮系、聚酯系、及聚氨酯系等所成的群來選擇的黏著劑。另外，黏著劑的種類是考慮用途及所被貼著的被著體的種類等來選擇。在第一黏著劑層22調配有能量線重合性化合物時，從支撐基板10側照射能量線至第一黏著劑層22，使能量線重合性化合物硬化。一旦使能量線重合性化合物硬化，則第一黏著劑層22的凝集力變高，可使第一黏著劑層22與半導體晶片CP之間的黏著力，及第一黏著劑層22與密封構件之間的黏著力降低或消失。例如可舉紫外線(UV)及電子線(EB)等作為能量線，較理想是紫外線。 第一黏著劑層22是亦可含有藉由加熱來發泡的發泡劑。此情況，藉由加熱來使發泡劑發泡，可使第一黏著劑層22與半導體晶片CP之間的黏著力，及第一黏著劑層22與密封構件之間的黏著力降低或消失。 第二黏著劑層23也含有黏著劑。在第二黏著劑層23中所含的黏著劑並未特別加以限定，只要是可固定支撐基板10與兩面黏著薄板20的材質即可。在第二黏著劑層23中所含的黏著劑是可因應所需從支撐基板10剝離兩面黏著薄板20之類的黏著劑為理想。 ･支撐基板 支撐基板10是用以支撐半導體晶片CP及密封體的基板。支撐基板10並無特別加以限定，只要是以能支撐半導體晶片CP及密封體的材質所形成即可。支撐基板10是以硬質材料所形成為理想。在本實施形態中，支撐基板10是玻璃製為理想。又，支撐基板10是硬質塑料薄膜製為理想。 (密封工程) 在圖1C是表示說明密封複數的半導體晶片CP的工程(有時稱為密封工程)的剖面概略圖。 使用密封構件30來密封複數的半導體晶片CP的方法並無特別加以限定。在本實施形態中，以半導體晶片CP的電路面W1側不會被密封構件30覆蓋的方式，使用密封構件30來密封，藉此形成密封體3。在複數的半導體晶片CP之間也充填有密封構件30。如圖1C所示般，在密封體3的表面中，半導體晶片CP的電路面W1及連接端子W3會露出。 密封構件30的材質是樹脂製為理想，例如可舉環氧樹脂等。在作為密封構件30使用的環氧樹脂中，例如亦可含有苯酚樹脂、彈性體、無機充填材及硬化促進劑等。例如，可使用液狀的密封樹脂來以半導體晶片CP的電路面W1側不會被密封構件30覆蓋的方式密封。 亦可在密封工程與其次的工程之間實施更使密封構件30硬化的工程(有時稱為追加的硬化工程)。在此工程中，可舉加熱密封樹脂層來使硬化促進的方法為例。另外，亦可不實施追加的硬化工程，藉由密封工程的加熱來使密封構件30充分地硬化。 (再配線層形成工程) 在圖2A是表示說明形成與半導體晶片CP電性連接的再配線層4的工程(有時稱為再配線層形成工程)的剖面概略圖。 在本實施形態中，使再配線層4與露出於密封體3的表面的連接端子W3電性連接。在本實施形態中是將再配線層4形成於電路面W1及密封體3的面之上。形成再配線層4的方法是可採用以往周知的方法。 再配線層4是具有用以使外部端子電極連接的外部電極焊墊41。在本實施形態中，複數的外部電極焊墊41會被形成於再配線層4的表面側。 (外部端子電極連接工程) 在圖2B是表示說明使外部端子電極5電性連接至再配線層4的工程(有時稱為外部端子電極連接工程)的剖面概略圖。藉由此外部端子電極連接工程，半導體晶片CP與外部端子電極5會被電性連接。 本實施形態是在外部電極焊墊41載置焊錫球等的外部端子電極5，藉由焊錫接合等來使外部端子電極5與外部電極焊墊41電性連接。焊錫球的材質並未特別加以限定。焊錫球的材質是例如可舉含鉛焊錫及無鉛焊錫等。 (支撐基板剝離工程) 在圖2C是表示說明從密封體3剝離支撐基板10而使半導體晶片CP的元件背面W2露出的工程(有時稱為支撐基板剝離工程)的剖面概略圖。 從密封體3剝離支撐基板10的方法並未特別加以限定。作為支撐基板剝離工程的方法是可舉在將支撐基板10從兩面黏著薄板20剝離之後，從密封體3剝離兩面黏著薄板20的方法。又，作為支撐基板剝離工程的方法是可舉將支撐基板10及兩面黏著薄板20設為一體來從密封體3剝離的方法。 在第一黏著劑層22中調配有能量線重合性化合物時，從支撐基板10側照射能量線至第一黏著劑層22，使能量線重合性化合物硬化。一旦使能量線重合性化合物硬化，則第一黏著劑層22的凝集力變高，可使第一黏著劑層22與密封體3之間的黏著力降低或消失。例如可舉紫外線(UV)及電子線(EB)等作為能量線，較理想是紫外線。使第一黏著劑層22與密封體3之間的黏著力降低或消失的方法是不限於能量線照射。作為使此黏著力降低的方法或消失的方法是例如可舉藉由加熱的方法、藉由加熱及能量線照射的方法、以及藉由冷卻的方法。 (保護膜形成層形成工程) 在圖2D是表示說明在露出的半導體晶片CP的元件背面W2形成硬化性的保護膜形成層60的工程(有時稱為保護膜形成層形成工程)的剖面概略圖。本實施形態是在密封體3的背面(與形成有再配線層4等的面相反側的面)側形成保護膜形成層60，藉此覆蓋元件背面W2。 作為本實施形態的保護膜形成層60是例如可使用熱硬化性及能量線硬化性的任一方的保護膜形成層。本實施形態的保護膜形成層60是使用含有從外部接受能量而硬化的硬化性的黏著劑組成物之材料來形成為理想。將含有該硬化性的黏著劑組成物之黏著薄板貼附於密封體3的背面，形成保護膜形成層60，而來覆蓋元件背面W2更為理想。 作為從外部供給的能量是例如可舉紫外線、電子線及熱等。保護膜形成層60是含有紫外線硬化型黏著劑及熱硬化型黏著劑的至少任一種為理想。保護膜形成層60是含有熱硬化型黏著劑的熱硬化性的層也為理想，含有紫外線硬化型黏著劑的紫外線硬化性的層也為理想。 形成保護膜形成層60之後，實施使保護膜形成層60硬化而形成保護膜60A(參照圖3A)的工程(有時稱為保護膜形成工程)。 (第一支撐薄板貼著工程) 在圖3A是表示說明使保護膜形成層60硬化而形成保護膜60A之後，在貼著有環框RF的第一支撐薄板70貼著密封體3的工程(有時稱為第一支撐薄板貼著工程)的剖面概略圖。 本實施形態的第一支撐薄板70是被使用在半導體裝置的製造工程之切割薄板為理想。作為切割薄板的第一支撐薄板70是具有基材薄膜及黏著劑層為理想。將保護膜60A朝向第一支撐薄板70的黏著劑層，而把密封體3貼著於第一支撐薄板70。此情況，在第一支撐薄板70的黏著劑層之上載置環框RF，輕輕推壓環框RF，將環框RF及第一支撐薄板70固定。然後，將在環框RF的環形狀的內側露出的黏著劑層推到密封體3的保護膜60A上，而把密封體3固定於第一支撐薄板70。 (小片化工程) 在圖3B是表示使被貼著於第一支撐薄板70的密封體3小片化的工程(有時稱為小片化工程)的剖面概略圖。 在本實施形態中，使密封體3以半導體晶片CP單位來小片化。使密封體3小片化的方法是未特別加以限定。作為小片化的方法是例如可舉使用切割鋸等的切斷手段來小片化的方法、及雷射照射法等。 藉由使密封體3小片化，作為半導體裝置的半導體封裝1會被製造。 本實施形態的半導體裝置的製造方法是包含將半導體封裝1安裝於印刷配線基板等的工程(有時稱為安裝工程)也為理想。半導體封裝1是在元件背面W2維持附有保護膜60A的情形下從第一支撐薄板70拾取。 ･實施形態的效果 若根據本實施形態，則由於在密封工程中，藉由支撐基板10來支撐半導體晶片CP，因此可抑制以密封構件30來密封半導體晶片CP時的彎曲。 若根據本實施形態，則可在維持以支撐基板10來支撐密封體3的情形下，實施再配線層形成工程及外部端子電極連接工程。一旦密封體彎曲，則密封體的表面彎曲，難以形成再配線層及外部端子電極，但由於密封體3的彎曲會被抑制，因此對於密封體3中的複數的半導體晶片CP可精度佳形成再配線層4及外部端子電極5。 又，由於密封體3是以支撐基板10所支撐，因此密封體3的操縱(handling)性會提升。特別是當半導體晶片CP的厚度及密封體3的厚度薄時，本實施形態的半導體元件的製造方法有效。 [第二實施形態] 其次，說明有關本發明的第二實施形態。 本實施形態的半導體裝置的製造方法是包含： 將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 在使前述半導體元件與前述外部端子電極電性連接之後，將前述密封體貼著於前述第二支撐薄板之工程； 在將前述密封體貼著於前述第二支撐薄板之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 使前述保護膜形成層硬化而形成保護膜之工程；及 使被貼著於前述第二支撐薄板的前述密封體小片化之工程。 前述密封體是使前述外部端子電極朝向第二支撐薄板來貼著於第二支撐薄板。 在本實施形態的半導體裝置的製造方法中，與從第一實施形態的半導體晶片貼著工程到外部端子電極連接工程為止同樣的工程會被實施。 本實施形態的半導體裝置的製造方法是主要外部端子電極連接工程的後的工程會與第一實施形態不同。第二實施形態是在其他的點與第一實施形態同樣，因此省略說明或簡略化。 圖5(圖5A、圖5B、圖5C及圖5D)是表示本實施形態的半導體裝置的製造方法之一例的圖。 (第二支撐薄板貼著工程) 在圖5A是表示說明使外部端子電極5電性連接至半導體晶片CP之後，從密封體3剝離支撐基板10之前，將密封體3貼著於第二支撐薄板71的工程(有時稱為第二支撐薄板貼著工程)的剖面概略圖。 在第二支撐薄板貼著工程中，將以支撐基板10所支撐的狀態的密封體3貼著於第二支撐薄板71。密封體3是將外部端子電極5朝向第二支撐薄板71而貼著。在本實施形態中也是第二支撐薄板71具有基材薄膜及黏著劑層為理想。在本實施形態中也是使密封體3支撐於貼著有環框RF的第二支撐薄板71為理想。又，第二支撐薄板71是被使用在半導體裝置的製造工程的切割薄板為理想。 (支撐基板剝離工程) 在圖5B是表示說明將密封體3貼著於第二支撐薄板71之後，從密封體3剝離支撐基板10而使半導體晶片CP的元件背面W2露出的工程(支撐基板剝離工程)的剖面概略圖。 在本實施形態中也是從密封體3剝離支撐基板10的方法未被特別加以限定。例如，可採用在第一實施形態說明的方法等。作為本實施形態的支撐基板剝離工程的方法是可舉在將支撐基板10從兩面黏著薄板20剝離之後，從密封體3剝離兩面黏著薄板20的方法。並且，作為本實施形態的支撐基板剝離工程的方法是可舉將支撐基板10及兩面黏著薄板20設為一體來從密封體3剝離的方法。 (保護膜形成層形成工程) 在圖5C是表示說明在露出的半導體晶片CP的元件背面W2形成硬化性的保護膜形成層60的工程(保護膜形成層形成工程)的剖面概略圖。 在本實施形態中是在被第二支撐薄板71支撐的密封體3形成保護膜形成層60。藉由在密封體3的背面(與形成有再配線層4等的面相反側的面)側形成保護膜形成層60，來覆蓋元件背面W2。 本實施形態的保護膜形成層60的形成方法是與第一實施形態的保護膜形成層60的情況同樣。當第二支撐薄板71為具備耐熱性時，因為可抑制熱硬化時的殘留應力的發生及殘膠等，所以保護膜形成層60是含有熱硬化型黏著劑的熱硬化性的層為理想。保護膜形成層60是含有紫外線硬化型黏著劑的紫外線硬化性的層為理想。 在本實施形態中也是實施使被第二支撐薄板71支撐的密封體3的保護膜形成層60硬化而形成保護膜60A(參照圖5D)的工程(保護膜形成工程)。使保護膜形成層60硬化的方法是與第一實施形態同樣。 (小片化工程) 在圖5D是表示說明被貼著於第二支撐薄板71的密封體3小片化的工程(小片化工程)的剖面概略圖。 在本實施形態中也與第一實施形態同樣地使密封體3小片化。藉由使密封體3小片化，作為半導體裝置的半導體封裝1會被製造。 本實施形態的半導體裝置的製造方法是包含將半導體封裝1安裝於印刷配線基板等的工程(有時稱為安裝工程)也為理想。半導體封裝1是在元件背面W2維持附有保護膜60A的情形下從第二支撐薄板71拾取。 ･實施形態的效果 若根據本實施形態，則可取得與第一實施形態同樣的效果。 而且，若根據本實施形態，則由於支撐基板剝離工程是可對於被第二支撐薄板71支撐的密封體3實施，因此可容易從密封體3剝離支撐基板10。 而且，若根據本實施形態，則由於剝離支撐基板10後的密封體3是被第二支撐薄板71支撐，因此容易實施保護膜形成層形成工程。 當第二支撐薄板71為切割薄板時，從支撐基板剝離工程到小片化工程，由於可在維持以第二支撐薄板71來支撐密封體3的情形下實施，因此可使半導體裝置的製造工程簡略化。 [第三實施形態] 其次，說明有關本發明的第三實施形態。 本實施形態的半導體裝置的製造方法是包含： 將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程； 將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程； 將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程； 在使前述半導體元件與前述外部端子電極電性連接之後，將前述密封體貼著於前述第二支撐薄板之工程； 在將前述密封體貼著於前述第二支撐薄板之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程； 在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程； 使前述保護膜形成層硬化而形成保護膜之工程； 在形成前述保護膜之後，從前述第二支撐薄板剝離前述密封體，而貼著於第三支撐薄板之工程；及 使被貼著於前述第三支撐薄板的前述密封體小片化之工程。 將前述密封體貼著於前述第二支撐薄板時，前述密封體是將前述外部端子電極朝向第二支撐薄板而貼著。 將前述密封體貼著於前述第三支撐薄板時，前述密封體是將前述保護膜朝向前述第三支撐薄板而貼著。 在本實施形態的半導體裝置的製造方法中，與從第一實施形態的半導體晶片貼著工程到外部端子電極連接工程為止同樣的工程會被實施。 並且，在本實施形態的半導體裝置的製造方法中，外部端子電極連接工程之後，與從第二實施形態的第二支撐薄板貼著工程到保護膜形成工程為止同樣的工程會被實施。 本實施形態的半導體裝置的製造方法主要是保護膜形成工程之後的工程會與第一實施形態及第二實施形態不同。由於第三實施形態在其他的點是與第一實施形態及第二實施形態同樣，因此將說明省略或簡略化。 圖6(圖6A及圖6B)是表示本實施形態的半導體裝置的製造方法之一例的圖。 (第三支撐薄板貼著工程) 在圖6A是表示說明在形成保護膜60A之後，從第二支撐薄板71剝離密封體3，而貼著於第三支撐薄板72的工程(有時稱為第三支撐薄板貼著工程)的剖面概略圖。 在第三支撐薄板貼著工程中，將形成保護膜60A後的密封體3貼著於第三支撐薄板72。密封體3是將保護膜60A朝向第三支撐薄板72而貼著。本實施形態的第三支撐薄板72也是與第一實施形態同樣，被使用在半導體裝置的製造工程的切割薄板為理想。在本實施形態中也是使密封體3支撐於貼著有環框RF2的第三支撐薄板72為理想。 (小片化工程) 在圖6B是表示說明使被貼著於第三支撐薄板72的密封體3小片化的工程(小片化工程)的剖面概略圖。 在本實施形態中也與第一實施形態同樣地使密封體3小片化。藉由使密封體3小片化，作為半導體裝置的半導體封裝1會被製造。 本實施形態的半導體裝置的製造方法是包含將半導體封裝1安裝於印刷配線基板等的工程(有時稱為安裝工程)也為理想。 半導體封裝1是在元件背面W2維持附有保護膜60A的情形下從第三支撐薄板72拾取。 ･實施形態的效果 若根據本實施形態，則取得與第一實施形態同樣的效果。 而且，在本實施形態中也是與第二實施形態同樣，由於支撐基板剝離工程是可對於被第二支撐薄板71支撐的密封體3實施，因此可容易從密封體3剝離支撐基板10。 而且，在本實施形態中也是與第二實施形態同樣，由於剝離支撐基板10後的密封體3是被第二支撐薄板71支撐，因此可容易實施保護膜形成層形成工程。 若根據本實施形態，則即使第二支撐薄板71未具有作為切割薄板的特性，還是可藉由在作為切割薄板的第三支撐薄板72貼著密封體3，來使密封體3小片化，可取得半導體封裝1。 [實施形態的變形] 本發明是不限於前述實施形態。本發明是包含在可達成本發明的目的之範圍將前述實施形態變形後的形態等。 在前述實施形態的半導體裝置的製造方法的任一中，亦可實施雷射印字於保護膜的工程(有時稱雷射印字工程)。 雷射印字是藉由雷射標記法來進行，藉由雷射光的照射來削掉保護膜的表面，藉此在保護膜標記產品的編號等。 在雷射印字工程中，亦可直接照射雷射光至保護膜，或隔著支撐薄板照射雷射光。 例如，在前述實施形態的半導體裝置的製造方法的任一中，雷射印字工程是在形成保護膜之後，比使被貼著於支撐薄板的密封體小片化的工程更前面實施為理想。若根據前述實施形態的半導體裝置的製造方法的任一，則可抑制密封體的彎曲，因此在實施雷射印字工程時，雷射光的焦點會正確地確定，可精度佳標記。 在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可在支撐基板剝離工程與保護膜形成層形成工程之間實施將密封體的露出的元件背面側研削的工程(有時稱為密封體研削工程)。藉由實施此研削工程，可將密封體的厚度形成薄，可謀求半導體裝置的薄型化。實施密封體研削工程時，在密封體的研削面形成保護膜形成層。 在前述實施形態中，是舉在支撐基板10貼附兩面黏著薄板20，使半導體晶片CP貼著於兩面黏著薄板20所具有的第一黏著劑層22的形態為例進行說明，但本發明是不限於如此的形態。 例如，在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可在支撐基板的表面形成黏著劑層，使半導體元件貼著於此黏著劑層。此情況的黏著劑層是含有與第一黏著劑層22同樣的黏著劑為理想。 利用密封構件來密封複數的半導體晶片CP的方法是不限於在前述實施形態說明的方法。例如，在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可採用將被支撐於支撐基板10的狀態的複數的半導體晶片CP載置於金屬模具內，在金屬模具內注入具有流動性的密封樹脂材料，使密封樹脂材料加熱硬化而形成密封樹脂層的方法。 並且，在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一中，亦可採用將薄板狀的密封樹脂載置成覆蓋複數的半導體晶片CP的電路面W1，將薄板狀的密封樹脂載置成覆蓋半導體晶片CP，使密封樹脂加熱硬化，而形成密封樹脂層的方法。 在使用薄板狀的密封樹脂時，是藉由真空層壓法來密封半導體晶片CP為理想。 在前述實施形態的半導體裝置的製造方法及實施形態的變形的半導體裝置的製造方法的任一密封工程中，亦可用密封構件30來覆蓋半導體晶片CP的電路面W1側。此情況，實行使半導體晶片CP的連接端子W3露出於密封體3的表面的工程(有時稱為連接端子露出工程)。 在此連接端子露出工程中，除去覆蓋半導體晶片CP的電路面W1或連接端子W3的密封體3的表面側的密封樹脂層的一部分或全體來使連接端子W3露出。使半導體晶片CP的連接端子W3露出的方法並未被特別加以限定。作為使半導體晶片CP的連接端子W3露出的方法是例如可舉將密封樹脂層研削而使連接端子W3露出的方法，藉由雷射照射等的方法來除去密封樹脂層而使連接端子W3露出的方法，及藉由蝕刻法來除去密封樹脂層而使連接端子W3露出的方法等。只要連接端子W3與再配線層4及外部端子電極5能夠電性連接，亦可使連接端子W3的全體露出，或使連接端子W3的一部分露出。 半導體封裝是不限於在前述實施形態及實施形態的變形中說明的形態。亦可為使外部電極焊墊扇出於密封體的半導體元件的領域外，使外部端子電極連接至該外部電極焊墊的FO-WLP型的半導體封裝。 在前述實施形態及實施形態的變形是舉以半導體元件單位來使密封體小片化的形態為例進行說明，但本發明並非限於如此的形態。例如，亦可如包含複數的半導體元件之方式使密封體小片化，藉此製造包含複數的半導體元件的半導體封裝。 [First Embodiment] Hereinafter, a method of manufacturing a semiconductor device according to this embodiment will be described. The manufacturing method of the semiconductor device of the present embodiment includes: orienting the back surface of the element toward the adhesive layer, and adhering a plurality of semiconductor elements having a circuit surface and the back surface of the device on the opposite side of the circuit surface to a support having the adhesive layer The process of the above-mentioned adhesive layer of the substrate; The process of sealing the above-mentioned semiconductor element attached to the above-mentioned supporting substrate to form a sealing body; The process of electrically connecting the semiconductor element and the external terminal electrodes; the process of exposing the element back surface of the semiconductor element by peeling the support substrate from the sealing body after the semiconductor element and the external terminal electrodes are electrically connected ; The process of forming a curable protective film-forming layer on the element back surface of the exposed semiconductor element; The process of hardening the protective film-forming layer to form a protective film; After forming the protective film, the sealing body is adhered to the first A process of supporting the thin plate; and a process of making the sealing body attached to the first supporting thin plate into small pieces. 1 (FIG. 1A, FIG. 1B, and FIG. 1C), FIG. 2 (FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D) and FIG. Figure of an example. (Semiconductor Wafer Attachment Process) FIGS. 1A and 1B are cross-sections illustrating a process (sometimes referred to as a semiconductor wafer attachment process) for attaching a semiconductor wafer CP as a semiconductor element to a support substrate 10 having an adhesive layer. Sketch map. In addition, although one semiconductor wafer CP is shown in FIG. 1A, in this embodiment, as shown in FIG. 1B, a plurality of semiconductor wafers CP are adhered to the adhesive layer. When the semiconductor wafers CP are bonded, one may be bonded one by one, or a plurality of semiconductor wafers CP may be bonded at the same time. In the present embodiment, the semiconductor wafer CP is attached to the adhesive layer of the double-sided adhesive sheet 20 which is attached to the support substrate 10 . ･Double-Sided Adhesive Sheet FIG. 4 is a schematic cross-sectional view showing the double-faced adhesive sheet 20 . The double-sided adhesive sheet 20 has a base material 21 , a first adhesive layer 22 and a second adhesive layer 23 . The base material 21 has a first base material surface 211 and a second base material surface 212 opposite to the first base material surface 211 . The first adhesive layer 22 is formed on the first substrate surface 211 . The second adhesive layer 23 is formed on the second substrate surface 212 . In this embodiment, the semiconductor wafer CP is attached to the first adhesive layer 22 , and the second adhesive layer 23 is attached to the support substrate 10 . As shown in FIG. 1 , the semiconductor wafer CP used in this embodiment has a circuit surface W1 on which connection terminals W3 are provided, and an element back surface W2 on the opposite side of the circuit surface W1. In this embodiment, the element back surface W2 is made to adhere to the first adhesive layer 22 . In this way, the method of making the circuit surface W1 face up to adhere to the first adhesive layer 22 is sometimes referred to as a face-up method. The first adhesive layer 22 contains an adhesive. The adhesive contained in the first adhesive layer 22 is not particularly limited, and various types of adhesives can be applied to the first adhesive layer 22 . As an adhesive agent contained in the 1st adhesive agent layer 22, the adhesive agent selected from the group of rubber type, acrylic type, silicone type, polyester type, urethane type, etc. is mentioned, for example. In addition, the type of the adhesive is selected in consideration of the application, the type of the body to be attached, and the like. When the energy ray superimposed compound is prepared in the first adhesive layer 22 , the energy ray is irradiated to the first adhesive layer 22 from the side of the support substrate 10 to cure the energy ray superimposed compound. Once the energy ray superimposition compound is cured, the cohesive force of the first adhesive layer 22 becomes high, and the adhesive force between the first adhesive layer 22 and the semiconductor wafer CP, and the first adhesive layer 22 and the sealing member can be improved. The adhesion between them decreases or disappears. For example, ultraviolet rays (UV), electron beams (EB), etc. are mentioned as energy rays, and ultraviolet rays are preferable. The first adhesive layer 22 may contain a foaming agent that is foamed by heating. In this case, by heating the foaming agent to foam, the adhesive force between the first adhesive layer 22 and the semiconductor wafer CP and the adhesive force between the first adhesive layer 22 and the sealing member can be reduced or eliminated . The second adhesive layer 23 also contains an adhesive. The adhesive contained in the second adhesive layer 23 is not particularly limited, as long as it is a material that can fix the support substrate 10 and the double-sided adhesive sheet 20 . The adhesive contained in the second adhesive layer 23 is preferably an adhesive that can peel off the double-sided adhesive sheet 20 from the support substrate 10 as required. ･Supporting substrate The supporting substrate 10 is a substrate for supporting the semiconductor wafer CP and the sealing body. The support substrate 10 is not particularly limited as long as it is formed of a material capable of supporting the semiconductor wafer CP and the sealing body. The support substrate 10 is preferably formed of a hard material. In the present embodiment, the support substrate 10 is preferably made of glass. In addition, the support substrate 10 is preferably made of a rigid plastic film. (Sealing Process) FIG. 1C is a schematic cross-sectional view illustrating a process of sealing a plurality of semiconductor wafers CP (sometimes referred to as a sealing process). The method of sealing the plurality of semiconductor wafers CP using the sealing member 30 is not particularly limited. In the present embodiment, the sealing body 3 is formed by sealing with the sealing member 30 so that the circuit surface W1 side of the semiconductor wafer CP is not covered by the sealing member 30 . The sealing member 30 is also filled between the plurality of semiconductor wafers CP. As shown in FIG. 1C , on the surface of the sealing body 3 , the circuit surface W1 and the connection terminals W3 of the semiconductor wafer CP are exposed. The material of the sealing member 30 is preferably made of resin, for example, epoxy resin etc. are mentioned. The epoxy resin used as the sealing member 30 may contain, for example, a phenol resin, an elastomer, an inorganic filler, a hardening accelerator, and the like. For example, a liquid sealing resin can be used to seal the semiconductor wafer CP so that the circuit surface W1 side of the semiconductor wafer CP is not covered by the sealing member 30 . A process of further hardening the sealing member 30 (sometimes referred to as an additional hardening process) may be performed between the sealing process and the next process. In this process, the method of heating the sealing resin layer to accelerate hardening is exemplified. In addition, the sealing member 30 may be sufficiently hardened by heating of the sealing process without performing an additional hardening process. (Rewiring Layer Formation Process) FIG. 2A is a schematic cross-sectional view illustrating a process for forming the rewiring layer 4 electrically connected to the semiconductor wafer CP (sometimes referred to as a rewiring layer forming process). In the present embodiment, the rewiring layer 4 is electrically connected to the connection terminals W3 exposed on the surface of the sealing body 3 . In this embodiment, the rewiring layer 4 is formed on the circuit surface W1 and the surface of the sealing body 3 . As a method of forming the rewiring layer 4, a conventionally known method can be used. The rewiring layer 4 has external electrode pads 41 for connecting external terminal electrodes. In this embodiment, a plurality of external electrode pads 41 are formed on the surface side of the rewiring layer 4 . (External Terminal Electrode Connection Process) FIG. 2B is a schematic cross-sectional view illustrating a process for electrically connecting the external terminal electrodes 5 to the rewiring layer 4 (sometimes referred to as an external terminal electrode connection process). Through this external terminal electrode connection process, the semiconductor chip CP and the external terminal electrodes 5 are electrically connected. In the present embodiment, the external terminal electrodes 5 such as solder balls are placed on the external electrode pads 41 , and the external terminal electrodes 5 and the external electrode pads 41 are electrically connected by solder bonding or the like. The material of the solder balls is not particularly limited. The material of the solder ball is, for example, lead-containing solder, lead-free solder, and the like. (Support Substrate Peeling Process) FIG. 2C is a schematic cross-sectional view illustrating a process of peeling the supporting substrate 10 from the sealing body 3 to expose the element back surface W2 of the semiconductor wafer CP (sometimes referred to as a supporting substrate peeling process). The method of peeling the support substrate 10 from the sealing body 3 is not particularly limited. As a method of the support substrate peeling process, after peeling the support substrate 10 from the double-sided adhesive sheet 20 , a method of peeling the double-sided adhesive sheet 20 from the sealing body 3 can be mentioned. Moreover, as a method of a support substrate peeling process, the method of integrating the support substrate 10 and the double-sided adhesive sheet 20 and peeling from the sealing body 3 is mentioned. When the energy ray superimposed compound is prepared in the first adhesive layer 22 , the energy ray is irradiated to the first adhesive layer 22 from the side of the support substrate 10 to cure the energy ray superimposed compound. Once the energy ray superimposed compound is cured, the cohesive force of the first adhesive layer 22 increases, and the adhesive force between the first adhesive layer 22 and the sealing body 3 can be reduced or eliminated. For example, ultraviolet rays (UV), electron beams (EB), etc. are mentioned as energy rays, and ultraviolet rays are preferable. The method of reducing or disappearing the adhesive force between the first adhesive layer 22 and the sealing body 3 is not limited to energy ray irradiation. As a method of reducing or disappearing the adhesive force, for example, a method by heating, a method by heating and energy ray irradiation, and a method by cooling can be mentioned. (Protective film forming layer forming process) FIG. 2D is a schematic cross-sectional view illustrating a process for forming a curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor wafer CP (sometimes referred to as a protective film forming layer forming process). picture. In the present embodiment, the protective film forming layer 60 is formed on the back surface of the sealing body 3 (the surface opposite to the surface on which the rewiring layer 4 and the like are formed) to cover the element back surface W2. As the protective film forming layer 60 of the present embodiment, for example, any one of thermosetting properties and energy ray curability can be used. The protective film forming layer 60 of the present embodiment is preferably formed using a material containing a curable adhesive composition that is cured by receiving energy from the outside. It is more preferable to attach an adhesive sheet containing the curable adhesive composition to the back surface of the sealing body 3 to form the protective film forming layer 60 to cover the back surface W2 of the element. Examples of energy supplied from the outside include ultraviolet rays, electron rays, heat, and the like. The protective film forming layer 60 preferably contains at least any one of an ultraviolet curable adhesive and a thermosetting adhesive. The protective film forming layer 60 is also preferably a thermosetting layer containing a thermosetting adhesive, and also preferably an ultraviolet curable layer containing an ultraviolet curable adhesive. After the protective film forming layer 60 is formed, a process of forming the protective film 60A (refer to FIG. 3A ) by curing the protective film forming layer 60 (sometimes referred to as a protective film forming process) is performed. (First support sheet sticking process) FIG. 3A shows and explains the process of sticking the first support sheet 70 with the ring frame RF to the sealing body 3 after the protective film forming layer 60 is hardened to form the protective film 60A ( It is sometimes referred to as a schematic cross-sectional view of the first support sheet attaching process). The first support sheet 70 of the present embodiment is preferably a dicing sheet used in a manufacturing process of a semiconductor device. The first support sheet 70 as a dicing sheet preferably has a base film and an adhesive layer. With the protective film 60A facing the adhesive layer of the first support sheet 70 , the sealing body 3 is attached to the first support sheet 70 . In this case, the ring frame RF is placed on the adhesive layer of the first support sheet 70 , and the ring frame RF is lightly pressed to fix the ring frame RF and the first support sheet 70 . Then, the adhesive layer exposed inside the ring shape of the ring frame RF is pushed onto the protective film 60A of the sealing body 3 , and the sealing body 3 is fixed to the first support sheet 70 . (Segmentation Process) FIG. 3B is a schematic cross-sectional view showing a process of segmenting the sealing body 3 adhered to the first support sheet 70 (sometimes referred to as a segmenting process). In the present embodiment, the sealing body 3 is divided into small pieces in units of semiconductor wafers CP. The method of making the sealing body 3 into small pieces is not particularly limited. As a method of forming into small pieces, for example, a method of forming into small pieces using a cutting means such as a dicing saw, a laser irradiation method, and the like can be mentioned. By reducing the sealing body 3 into pieces, the semiconductor package 1 as a semiconductor device is manufactured. It is also desirable that the manufacturing method of the semiconductor device of the present embodiment includes a process of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting process). The semiconductor package 1 is picked up from the first support sheet 70 with the protective film 60A attached to the element back surface W2 maintained. ･Effects of Embodiment According to the present embodiment, since the semiconductor wafer CP is supported by the support substrate 10 in the sealing process, warping when the semiconductor wafer CP is sealed with the sealing member 30 can be suppressed. According to this embodiment, the rewiring layer formation process and the external terminal electrode connection process can be performed while maintaining the sealing body 3 supported by the support substrate 10 . Once the sealing body is bent, the surface of the sealing body is bent, and it is difficult to form the rewiring layer and the external terminal electrodes. However, since the bending of the sealing body 3 is suppressed, the sealing body 3 can be formed with high precision for a plurality of semiconductor wafers CP. Wiring layer 4 and external terminal electrodes 5 . Moreover, since the sealing body 3 is supported by the support substrate 10, the handling property of the sealing body 3 is improved. The manufacturing method of the semiconductor element of this embodiment is effective especially when the thickness of the semiconductor wafer CP and the thickness of the sealing body 3 are thin. [Second Embodiment] Next, a second embodiment of the present invention will be described. The manufacturing method of the semiconductor device of the present embodiment includes: orienting the back surface of the element toward the adhesive layer, and adhering a plurality of semiconductor elements having a circuit surface and the back surface of the device on the opposite side of the circuit surface to a support having the adhesive layer The process of the above-mentioned adhesive layer of the substrate; The process of sealing the above-mentioned semiconductor element attached to the above-mentioned supporting substrate to form a sealing body; The process of electrically connecting the semiconductor element and the external terminal electrodes; the process of attaching the sealing body to the second support sheet after the semiconductor device and the external terminal electrodes are electrically connected; attaching the sealing body to the second supporting sheet After the second supporting sheet, the supporting substrate is peeled off from the sealing body to expose the element back surface of the semiconductor element; The process of forming a curable protective film forming layer on the exposed element back surface of the semiconductor element; The process of forming a protective film by hardening the said protective film forming layer; and the process of making the said sealing body adhered to the said 2nd support sheet into small pieces. The sealing body is attached to the second support sheet so that the external terminal electrodes face the second support sheet. In the manufacturing method of the semiconductor device of the present embodiment, the same processes as those from the semiconductor wafer bonding process to the external terminal electrode connection process of the first embodiment are carried out. The manufacturing method of the semiconductor device of the present embodiment differs from the first embodiment in that the main process after the external terminal electrode connection process is different. The second embodiment is the same as the first embodiment in other points, so the description is omitted or simplified. FIG. 5 (FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D ) is a diagram showing an example of a method of manufacturing the semiconductor device of the present embodiment. (Second Supporting Sheet Attachment Process) FIG. 5A illustrates that the sealing body 3 is attached to the second supporting sheet before the support substrate 10 is peeled off from the sealing body 3 after the external terminal electrodes 5 are electrically connected to the semiconductor wafer CP. A schematic cross-sectional view of the process of 71 (sometimes referred to as the second support sheet attaching process). In the second support sheet bonding process, the sealing body 3 in the state supported by the support substrate 10 is bonded to the second support sheet 71 . The sealing body 3 adheres the external terminal electrodes 5 toward the second support sheet 71 . Also in this embodiment, it is desirable that the second support sheet 71 has a base film and an adhesive layer. Also in this embodiment, it is desirable to support the sealing body 3 by the second support sheet 71 to which the ring frame RF is attached. In addition, it is preferable that the second support sheet 71 is a dicing sheet used in a manufacturing process of a semiconductor device. (Support Substrate Peeling Process) FIG. 5B illustrates a process for exposing the element back surface W2 of the semiconductor wafer CP by peeling the supporting substrate 10 from the sealing body 3 after the sealing body 3 is adhered to the second supporting sheet 71 (supporting substrate peeling off). Project) cross-sectional schematic diagram. Also in this embodiment, the method of peeling the support substrate 10 from the sealing body 3 is not particularly limited. For example, the method described in the first embodiment or the like can be employed. As a method of the support substrate peeling process of the present embodiment, after peeling the support substrate 10 from the double-sided adhesive sheet 20 , a method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is exemplified. Moreover, as a method of the support substrate peeling process of this embodiment, the method of integrating the support substrate 10 and the double-sided adhesive sheet 20 and peeling off the sealing body 3 can be mentioned. (Protective film forming layer forming process) FIG. 5C is a schematic cross-sectional view illustrating a process (protective film forming layer forming process) of forming the curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor wafer CP. In the present embodiment, the protective film forming layer 60 is formed on the sealing body 3 supported by the second supporting sheet 71 . The element back surface W2 is covered by forming the protective film forming layer 60 on the back surface of the sealing body 3 (surface opposite to the surface on which the rewiring layer 4 and the like are formed). The formation method of the protective film formation layer 60 of this embodiment is the same as that of the case of the protective film formation layer 60 of 1st Embodiment. When the second support sheet 71 has heat resistance, the generation of residual stress and adhesive residue during thermosetting can be suppressed, so the protective film forming layer 60 is preferably a thermosetting layer containing a thermosetting adhesive. The protective film forming layer 60 is preferably an ultraviolet curable layer containing an ultraviolet curable adhesive. Also in the present embodiment, a process (protective film forming process) of forming a protective film 60A (refer to FIG. 5D ) by curing the protective film forming layer 60 of the sealing body 3 supported by the second supporting sheet 71 is performed. The method of hardening the protective film forming layer 60 is the same as that of the first embodiment. (Segmentation Process) FIG. 5D is a schematic cross-sectional view for explaining the process of reducing the sealing body 3 attached to the second support sheet 71 into pieces (the segmenting process). Also in the present embodiment, the sealing body 3 is formed into small pieces in the same manner as in the first embodiment. By reducing the sealing body 3 into pieces, the semiconductor package 1 as a semiconductor device is manufactured. It is also desirable that the manufacturing method of the semiconductor device of the present embodiment includes a process of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting process). The semiconductor package 1 is picked up from the second support sheet 71 with the protective film 60A attached to the element back surface W2 maintained. ･Effects of Embodiment According to this embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, according to this embodiment, since the support substrate peeling process can be performed with respect to the sealing body 3 supported by the second support sheet 71 , the support substrate 10 can be easily peeled off from the sealing body 3 . Furthermore, according to this embodiment, since the sealing body 3 after peeling off the support substrate 10 is supported by the second support sheet 71, the protective film forming layer forming process can be easily performed. When the second support sheet 71 is a dicing sheet, the peeling process from the support substrate to the dicing process can be performed while maintaining the sealing body 3 supported by the second support sheet 71 , so that the manufacturing process of the semiconductor device can be simplified. change. [Third Embodiment] Next, a third embodiment of the present invention will be described. The manufacturing method of the semiconductor device of the present embodiment includes: orienting the back surface of the element toward the adhesive layer, and adhering a plurality of semiconductor elements having a circuit surface and the back surface of the device on the opposite side of the circuit surface to a support having the adhesive layer The process of the above-mentioned adhesive layer of the substrate; The process of sealing the above-mentioned semiconductor element attached to the above-mentioned supporting substrate to form a sealing body; The process of electrically connecting the semiconductor element and the external terminal electrodes; the process of attaching the sealing body to the second support sheet after the semiconductor device and the external terminal electrodes are electrically connected; attaching the sealing body to the second supporting sheet After the second supporting sheet, the supporting substrate is peeled off from the sealing body to expose the element back surface of the semiconductor element; The process of forming a curable protective film forming layer on the exposed element back surface of the semiconductor element; The process of hardening the protective film forming layer to form a protective film; The process of peeling the sealing body from the second supporting sheet after forming the protective film and sticking it to the third supporting sheet; The above-mentioned sealing body of the third supporting sheet is small-sized. When the sealing body is attached to the second support sheet, the sealing body is attached so that the external terminal electrodes face the second support sheet. When sticking the said sealing body to the said 3rd support sheet, the said sealing body sticks the said protective film toward the said 3rd support sheet. In the manufacturing method of the semiconductor device of the present embodiment, the same processes as those from the semiconductor wafer bonding process to the external terminal electrode connection process of the first embodiment are carried out. Furthermore, in the manufacturing method of the semiconductor device of the present embodiment, after the external terminal electrode connection step, the same steps as the second support sheet bonding step of the second embodiment to the protective film forming step are performed. The manufacturing method of the semiconductor device of the present embodiment is mainly different from the first embodiment and the second embodiment in the steps after the protective film formation step. Since the third embodiment is the same as the first embodiment and the second embodiment in other points, the description will be omitted or simplified. FIG. 6 ( FIGS. 6A and 6B ) is a diagram showing an example of a method of manufacturing the semiconductor device of the present embodiment. (Third support sheet sticking process) FIG. 6A shows and explains the process of peeling off the sealing body 3 from the second support sheet 71 after forming the protective film 60A and sticking it to the third support sheet 72 (sometimes referred to as the second support sheet 72). Schematic cross-sectional view of the three-support sheet sticking project). In the third support sheet sticking process, the sealing body 3 after forming the protective film 60A is stuck to the third support sheet 72 . The sealing body 3 is attached with the protective film 60A facing the third support sheet 72 . Similar to the first embodiment, the third support sheet 72 of the present embodiment is also preferably a dicing sheet used in a manufacturing process of a semiconductor device. Also in the present embodiment, it is desirable to support the sealing body 3 by the third support sheet 72 to which the ring frame RF2 is attached. (Segmentation Process) FIG. 6B is a schematic cross-sectional view illustrating a process of segmenting the sealing body 3 adhered to the third support sheet 72 (segmentation process). Also in the present embodiment, the sealing body 3 is formed into small pieces in the same manner as in the first embodiment. By reducing the sealing body 3 into pieces, the semiconductor package 1 as a semiconductor device is manufactured. It is also desirable that the manufacturing method of the semiconductor device of the present embodiment includes a process of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting process). The semiconductor package 1 is picked up from the third support sheet 72 with the protective film 60A attached to the element back surface W2 maintained. ･Effects of Embodiment According to this embodiment, the same effects as those of the first embodiment can be obtained. Also in the present embodiment, similarly to the second embodiment, since the supporting substrate peeling process can be performed on the sealing body 3 supported by the second supporting sheet 71 , the supporting substrate 10 can be easily peeled off from the sealing body 3 . Also in the present embodiment, as in the second embodiment, since the sealing body 3 after peeling the support substrate 10 is supported by the second support sheet 71, the protective film forming layer forming process can be easily performed. According to the present embodiment, even if the second support sheet 71 does not have the properties as a cut sheet, the sealing body 3 can be reduced into small pieces by adhering the sealing body 3 to the third support sheet 72 as a cut sheet. A semiconductor package 1 is obtained. [Variation of Embodiment] The present invention is not limited to the above-described embodiment. The present invention includes modifications and the like of the above-described embodiments within the scope in which the object of the present invention can be achieved. In any of the manufacturing methods of the semiconductor device of the aforementioned embodiments, a process of laser printing on the protective film (may be referred to as a laser printing process) may be performed. Laser printing is performed by a laser marking method, and the surface of the protective film is cut off by the irradiation of laser light, thereby marking the serial number of the product on the protective film. In the laser printing process, the laser light can also be directly irradiated to the protective film, or the laser light can be irradiated through the supporting sheet. For example, in any of the manufacturing methods of the semiconductor device of the above-mentioned embodiments, it is preferable that the laser printing process is performed after the protective film is formed, rather than the process of reducing the sealing body attached to the support sheet into small pieces. According to any one of the manufacturing methods of the semiconductor device of the above-mentioned embodiments, since the warpage of the sealing body can be suppressed, the focal point of the laser beam can be accurately determined when the laser printing process is performed, and the marking can be performed with high precision. In any of the method for manufacturing a semiconductor device according to the aforementioned embodiment and the method for manufacturing a semiconductor device according to the modification of the embodiment, the element for exposing the sealing body may be performed between the step of peeling the support substrate and the step of forming the protective film forming layer. The backside grinding process (sometimes called the sealing body grinding process). By carrying out this grinding process, the thickness of the sealing body can be reduced, and the thickness of the semiconductor device can be reduced. When carrying out the sealing body grinding process, a protective film forming layer is formed on the grinding surface of the sealing body. In the above-mentioned embodiment, the double-sided adhesive sheet 20 is attached to the support substrate 10, and the semiconductor wafer CP is attached to the first adhesive layer 22 of the double-sided adhesive sheet 20. It is not limited to such a form. For example, in any of the method for manufacturing a semiconductor device according to the aforementioned embodiment and the method for manufacturing a semiconductor device according to the modified embodiment, an adhesive layer may be formed on the surface of the support substrate, and the semiconductor element may be adhered to the adhesive layer. . The adhesive layer in this case preferably contains the same adhesive as the first adhesive layer 22 . The method of sealing the plurality of semiconductor wafers CP with the sealing member is not limited to the method described in the foregoing embodiment. For example, in any of the method for manufacturing a semiconductor device according to the aforementioned embodiment and the method for manufacturing a semiconductor device according to the modification of the embodiment, a plurality of semiconductor wafers CP supported by the support substrate 10 may be mounted on a metal. In the mold, a fluid sealing resin material is injected into a metal mold, and the sealing resin material is heated and hardened to form a sealing resin layer. In addition, in any of the method for manufacturing a semiconductor device according to the aforementioned embodiment and the method for manufacturing a semiconductor device according to the modification of the embodiment, it is also possible to employ a thin plate-shaped sealing resin placed so as to cover the circuit surfaces W1 of the plurality of semiconductor wafers CP. A method of forming a sealing resin layer by placing a thin plate-shaped sealing resin so as to cover the semiconductor wafer CP, and heating and curing the sealing resin. When a thin plate-shaped sealing resin is used, it is preferable to seal the semiconductor wafer CP by a vacuum lamination method. The sealing member 30 may cover the circuit surface W1 side of the semiconductor wafer CP in any sealing process of the manufacturing method of the semiconductor device of the above-described embodiment and the manufacturing method of the modified semiconductor device of the embodiment. In this case, a process of exposing the connection terminals W3 of the semiconductor wafer CP to the surface of the sealing body 3 (sometimes referred to as a connection terminal exposure process) is performed. In this connection terminal exposing process, a part or the whole of the sealing resin layer covering the circuit surface W1 of the semiconductor wafer CP or the surface side of the sealing body 3 of the connection terminal W3 is removed to expose the connection terminal W3. The method of exposing the connection terminals W3 of the semiconductor wafer CP is not particularly limited. As a method of exposing the connection terminals W3 of the semiconductor wafer CP, for example, a method of grinding the sealing resin layer to expose the connection terminals W3, removing the sealing resin layer by a method such as laser irradiation, and exposing the connection terminals W3 can be mentioned. method, and a method of exposing the connection terminal W3 by removing the sealing resin layer by an etching method, and the like. As long as the connection terminal W3 can be electrically connected to the rewiring layer 4 and the external terminal electrode 5 , the entire connection terminal W3 may be exposed, or a part of the connection terminal W3 may be exposed. The semiconductor package is not limited to the form described in the above-mentioned embodiment and the modification of the embodiment. A FO-WLP type semiconductor package in which the external terminal electrodes are connected to the external electrode pads may also be used outside the field of the semiconductor element of the sealing body. The above-mentioned embodiment and the modification of the embodiment are described by taking as an example the form in which the sealing body is formed into small pieces in units of semiconductor elements, but the present invention is not limited to this form. For example, it is also possible to manufacture a semiconductor package including a plurality of semiconductor elements by forming the sealing body into small pieces so as to include a plurality of semiconductor elements.

1:半導體封裝 3:密封體 4:再配線層 5:外部端子電極 10:支撐基板 20:兩面黏著薄板 21:基材 22:第一黏著劑層 23:第二黏著劑層 30:密封構件 41:外部電極焊墊 60:保護膜形成層 60A:保護膜 70:第一支撐薄板 71:第二支撐薄板 72:第三支撐薄板 211:第一基材面 212:第二基材面 CP:半導體晶片 W1:電路面 W2:元件背面 W3:連接端子 RF:環框1: Semiconductor packaging 3: Sealing body 4: Rewiring layer 5: External terminal electrode 10: Support substrate 20: Adhesive sheet on both sides 21: Substrate 22: The first adhesive layer 23: Second Adhesive Layer 30: Sealing member 41: External electrode pads 60: Protective film forming layer 60A: Protective film 70: The first support sheet 71: Second support sheet 72: Third support sheet 211: The first substrate surface 212: Second substrate surface CP: Semiconductor wafer W1: circuit surface W2: Back of component W3: Connection terminal RF: Ring Box

[圖1A]是說明第一實施形態的半導體裝置的製造方法的剖面圖。 [圖1B]是說明第一實施形態的半導體裝置的製造方法的剖面圖。 [圖1C]是說明第一實施形態的半導體裝置的製造方法的剖面圖。 [圖2A]是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 [圖2B]是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 [圖2C]是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 [圖2D]是接續於圖1A、圖1B及圖1C，說明第一實施形態的製造方法的剖面圖。 [圖3A]是接續於圖2A、圖2B、圖2C及圖2D，說明第一實施形態的製造方法的剖面圖。 [圖3B]是接續於圖2A、圖2B、圖2C及圖2D，說明第一實施形態的製造方法的剖面圖。 [圖4]是使用在第一實施形態的兩面黏著薄板的剖面圖。 [圖5A]是說明第二實施形態的半導體裝置的製造方法的剖面圖。 [圖5B]是說明第二實施形態的半導體裝置的製造方法的剖面圖。 [圖5C]是說明第二實施形態的半導體裝置的製造方法的剖面圖。 [圖5D]是說明第二實施形態的半導體裝置的製造方法的剖面圖。 [圖6A]是說明第三實施形態的半導體裝置的製造方法的剖面圖。 [圖6B]是說明第三實施形態的半導體裝置的製造方法的剖面圖。1A is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. 1B is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. 1C is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. 2A is a cross-sectional view illustrating the manufacturing method of the first embodiment following FIG. 1A , FIG. 1B and FIG. 1C . 2B is a cross-sectional view illustrating the manufacturing method of the first embodiment following FIG. 1A , FIG. 1B and FIG. 1C . 2C is a cross-sectional view illustrating the manufacturing method of the first embodiment following FIG. 1A , FIG. 1B and FIG. 1C . 2D is a cross-sectional view illustrating the manufacturing method of the first embodiment following FIG. 1A , FIG. 1B and FIG. 1C . 3A is a cross-sectional view illustrating the manufacturing method of the first embodiment following FIGS. 2A , 2B, 2C, and 2D. 3B is a cross-sectional view illustrating the manufacturing method of the first embodiment following FIGS. 2A , 2B, 2C, and 2D. 4 is a cross-sectional view of the double-sided adhesive sheet used in the first embodiment. 5A is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the second embodiment. 5B is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the second embodiment. 5C is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the second embodiment. 5D is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the second embodiment. 6A is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. 6B is a cross-sectional view illustrating a method of manufacturing the semiconductor device of the third embodiment.

3:密封體 3: Sealing body

4:再配線層 4: Rewiring layer

5:外部端子電極 5: External terminal electrode

10:支撐基板 10: Support substrate

20:兩面黏著薄板 20: Adhesive sheet on both sides

30:密封構件 30: Sealing member

41:外部電極焊墊 41: External electrode pads

60:保護膜形成層 60: Protective film forming layer

CP:半導體晶片 CP: Semiconductor wafer

W1:電路面 W1: circuit surface

W2:元件背面 W2: Back of component

W3:連接端子 W3: Connection terminal

Claims (6)

一種半導體裝置的製造方法，其特徵為包含：將元件背面朝向黏著劑層，使具有電路面及與前述電路面相反側的前述元件背面之複數的半導體元件貼著於具有前述黏著劑層的支撐基板的前述黏著劑層之工程；將被貼著於前述支撐基板的前述半導體元件密封，而形成密封體之工程；將外部端子電極形成於前述密封體，而使被貼著於前述支撐基板的前述半導體元件與前述外部端子電極電性連接之工程；在使前述半導體元件與前述外部端子電極電性連接之後，從前述密封體剝離前述支撐基板，而使前述半導體元件的前述元件背面露出之工程；在露出的前述半導體元件的前述元件背面形成硬化性的保護膜形成層之工程；使前述保護膜形成層硬化而形成保護膜之工程；在形成前述保護膜之後，將前述密封體貼著於第一支撐薄板之工程；及使被貼著於前述第一支撐薄板的前述密封體小片化之工程，將被形成於前述密封體的前述保護膜朝向前述第一支撐薄板貼著。 A method of manufacturing a semiconductor device, comprising: orienting the backside of the element toward an adhesive layer, and attaching a plurality of semiconductor elements having a circuit surface and the backside of the element on the opposite side of the circuit surface to a support having the adhesive layer The process of the aforementioned adhesive layer of the substrate; the process of sealing the aforementioned semiconductor element attached to the aforementioned support substrate to form a sealing body; The process of electrically connecting the semiconductor element and the external terminal electrodes; the process of exposing the element back surface of the semiconductor element by peeling the support substrate from the sealing body after the semiconductor element and the external terminal electrodes are electrically connected ; The process of forming a curable protective film forming layer on the back surface of the element of the exposed semiconductor element; The process of hardening the protective film forming layer to form a protective film; After forming the protective film, the sealing body is adhered to the first A process of supporting a thin plate; and a process of making the sealing body adhered to the first supporting thin plate into small pieces, the protective film formed on the sealing body is adhered toward the first supporting thin plate. 如請求項1記載的半導體裝置的製造方 法，其中，前述第一支撐薄板為切割薄板。 Manufacturer of the semiconductor device according to claim 1 method, wherein the first supporting sheet is a cutting sheet. 如請求項1記載的半導體裝置的製造方法，其中，前述第一支撐薄板，係具有基材薄膜及黏著劑層。 The method for manufacturing a semiconductor device according to claim 1, wherein the first support sheet includes a base film and an adhesive layer. 如請求項3記載的半導體裝置的製造方法，其中，將前述保護膜貼著於前述第一支撐薄板的前述黏著劑層。 The manufacturing method of the semiconductor device of Claim 3 which adheres the said protective film to the said adhesive bond layer of the said 1st support sheet. 如請求項3記載的半導體裝置的製造方法，其中，在前述第一支撐薄板的前述黏著劑層上載置環框，將前述環框及前述第一支撐薄板固定，將在前述環框的環形狀的內側露出的前述黏著劑層推到前述密封體的前述保護膜上，而把前述密封體固定於前述第一支撐薄板。 The method of manufacturing a semiconductor device according to claim 3, wherein a ring frame is placed on the adhesive layer of the first support sheet, the ring frame and the first support sheet are fixed, and the ring shape of the ring frame is fixed. The adhesive layer exposed on the inner side is pushed onto the protective film of the sealing body, and the sealing body is fixed to the first supporting sheet. 如請求項1~5的任一項所記載的半導體裝置的製造方法，其中，前述保護膜形成層係含有紫外線硬化型黏著劑及熱硬化型黏著劑的至少任一種。 The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the protective film forming layer contains at least any one of an ultraviolet curable adhesive and a thermosetting adhesive.
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