TWI766580B - A semiconductor device - Google Patents

A semiconductor device Download PDF

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TWI766580B
TWI766580B TW110105147A TW110105147A TWI766580B TW I766580 B TWI766580 B TW I766580B TW 110105147 A TW110105147 A TW 110105147A TW 110105147 A TW110105147 A TW 110105147A TW I766580 B TWI766580 B TW I766580B
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semiconductor
layer
substrate
semiconductor epitaxial
epitaxial stack
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TW110105147A
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TW202127527A (en
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呂志強
林俊宇
陳怡名
林敬倍
簡崇訓
黃建富
顧浩民
謝明勳
徐子傑
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晶元光電股份有限公司
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Abstract

A semiconductor device comprises a substrate having a first surface; a semiconductor unit on the first surface; and a adhesion structure between the first surface and the semiconductor unit and directly contacting the semiconductor unit and the substrate; wherein the adhesion structure comprises an adhesion layer and a sacrificing layer. and the materials of the adhesion layer and the sacrificing layer are different.

Description

一種半導體裝置a semiconductor device

本發明係關於一種光電半導體元件的製造方法。 The present invention relates to a method of manufacturing an optoelectronic semiconductor element.

隨著科技日新月異,光電半導體元件在資訊的傳輸以及能量的轉換上有極大的貢獻。以系統的運用為例,例如光纖通訊、光學儲存及軍事系統等,光電半導體元件皆能有所發揮。以能量的轉換方式進行區分,光電半導體元件一般可分為三類:將電能轉換為光的放射,如發光二極體及雷射二極體;將光的訊號轉換為電的信號,如光檢測器;將光的輻射能轉換為電能,如太陽能電池。 With the rapid development of science and technology, optoelectronic semiconductor components have made great contributions to the transmission of information and the conversion of energy. Take the application of the system as an example, such as optical fiber communication, optical storage and military systems, etc., optoelectronic semiconductor components can all play a role. Distinguished by the way of energy conversion, optoelectronic semiconductor components can generally be divided into three categories: convert electrical energy into light emission, such as light-emitting diodes and laser diodes; convert light signals into electrical signals, such as light Detector; converts the radiant energy of light into electricity, such as a solar cell.

在光電半導體元件之中,成長基板扮演著非常重要的角色。形成光電半導體元件所必要的半導體磊晶結構皆成長於基板之上,並透過基板得到支持。因此,選擇一個適合的成長基板,往往成為決定光電半導體元件中元件成長品質的重要因素。 Among optoelectronic semiconductor devices, the growth substrate plays a very important role. The semiconductor epitaxial structures necessary for the formation of optoelectronic semiconductor devices are grown on and supported by the substrate. Therefore, choosing a suitable growth substrate often becomes an important factor in determining the growth quality of components in optoelectronic semiconductor devices.

然而,有時一個好的元件成長基板並不一定是一個好的元件承載基板。以發光二極體為例,在習知的紅光元件製程中,為了提昇元件的成長品質,會選擇晶格常數與半導體磊晶結構較為接近但不透明的砷化鎵(GaAs)基板 作為成長基板。然而,對於以發光為操作目的的發光二極體元件而言,於操作過程之中,不透明的成長基板會造成元件的發光效率下降。 However, sometimes a good component growth substrate is not necessarily a good component carrier substrate. Taking light emitting diodes as an example, in the conventional red light device process, in order to improve the growth quality of the device, a gallium arsenide (GaAs) substrate with a lattice constant close to the semiconductor epitaxial structure but opaque is selected. as a growth substrate. However, for the light-emitting diode device whose operation purpose is to emit light, the opaque growth substrate will cause the luminous efficiency of the device to decrease during the operation.

為了滿足光電半導體元件對於成長基板與承載基板不同需求條件的要求,基板的轉移技術於是因應而生。亦即,半導體磊晶結構先於成長基板上進行成長,再將成長完成的半導體磊晶結構轉移至承載基板,以方便後續的元件操作進行。在半導體磊晶結構與承載基板結合之後,原有成長基板的移除則成為轉移技術的關鍵之一。 In order to meet the different requirements of optoelectronic semiconductor components for growth substrates and carrier substrates, the transfer technology of substrates is developed accordingly. That is, the semiconductor epitaxial structure is grown on the growth substrate first, and then the grown semiconductor epitaxial structure is transferred to the carrier substrate to facilitate subsequent device operations. After the semiconductor epitaxial structure is combined with the carrier substrate, the removal of the original growth substrate becomes one of the keys to the transfer technology.

成長基板的移除方式主要包括將原有的成長基板以蝕刻液蝕刻溶解,以物理方式切割磨除,或事先在成長基板與半導體磊晶結構之間生成犧牲層,再藉由蝕刻去除犧牲層的方式將成長基板與半導體分離等。然而,不論是以蝕刻液溶解基板或是以物理性切割方式磨除基板,對原有的成長基板而言,都是一種破壞。成長基板無法再度利用,在強調環保及節能的現代,無疑是一種材料的浪費。然而,若是使用犧牲層結構進行分離,對於光電半導體元件而言,如何進行有效地選擇性轉移,則是目前研究的方向之一。 The removal method of the growth substrate mainly includes etching and dissolving the original growth substrate with an etchant, cutting and grinding it physically, or generating a sacrificial layer between the growth substrate and the semiconductor epitaxial structure in advance, and then removing the sacrificial layer by etching. Separate the growth substrate from the semiconductor in a way. However, whether the substrate is dissolved by the etching solution or the substrate is removed by physical cutting, it is a kind of damage to the original growth substrate. Growth substrates cannot be reused. In modern times, which emphasize environmental protection and energy saving, it is undoubtedly a waste of materials. However, if a sacrificial layer structure is used for separation, for optoelectronic semiconductor devices, how to effectively perform selective transfer is one of the current research directions.

一半導體裝置,包含一基板具有一第一表面;一半導體元件位於該第一表面上;以及一黏結結構位於該第一表面與該半導體元件之間,與該半導體元件以及該基板直接接觸;其中,該黏結結構包含一黏結層以及一犧牲層,該黏結層與該犧牲層的材質相異。 A semiconductor device, comprising a substrate with a first surface; a semiconductor element located on the first surface; and a bonding structure located between the first surface and the semiconductor element, in direct contact with the semiconductor element and the substrate; wherein , the bonding structure includes a bonding layer and a sacrificial layer, and the material of the bonding layer and the sacrificial layer are different.

101:黏結基板 101: Bonding the substrate

3011:表面 3011: Surface

1011:表面 1011: Surface

3012:表面 3012: Surface

1012:表面 1012: Surface

302:轉換單元 302: Conversion unit

102:成長基板 102: Growth substrate

303:第二半導體層 303: second semiconductor layer

1022:表面 1022: Surface

304:半導體層 304: Semiconductor layer

103:擷取元件 103: Capture Components

3031:表面 3031: Surface

1031:支撐結構 1031: Support Structure

31:第一半導體磊晶疊層 31: The first semiconductor epitaxial stack

1032:軟性基板 1032: Flexible Substrate

311:表面 311: Surface

110:孔洞 110: Hole

32:第二半導體磊晶疊層 32: Second semiconductor epitaxial stack

1101:壁面 1101: Wall

4:黏著介質 4: Adhesive medium

120:孔洞 120: Hole

5:支撐結構 5: Support structure

2:黏著結構 2: Adhesive structure

601:犧牲層 601: Sacrificial Layer

202:黏結層 202: Bonding layer

7:雷射光 7: Laser light

201:犧牲層 201: Sacrificial Layer

t:厚度 t: thickness

3:半導體磊晶疊層 3: Semiconductor epitaxial stack

w:間隔寬度 w: interval width

301:第一半導體層 301: first semiconductor layer

303s:第一下表面 303s: First lower surface

304s:第二下表面 304s: Second lower surface

第1A圖至第1I圖係分別為依本發明第一實施例之製程方法於各步驟之對應結構示意圖;第2A圖至第2H圖係分別為依本發明第二實施例之製程方法於各步驟之對應結構示意圖;第3A圖至第3H圖係分別為依本發明第三實施例之製程方法於各步驟之對應結構示意圖;第4A圖至第4C圖為依本發明第四實施例之結構示意圖;第5A圖至第5G圖為依本發明第五實施例之結構示意圖;第6A圖至第6H圖為依本發明第六實施例之結構示意圖;第7A圖至第7F圖為依本發明第七實施例之結構示意圖;第8A圖至第8F圖係分別為依本發明第八實施例之製程方法於各步驟之對應結構示意圖;第9A圖至第9I圖係分別為依本發明第九實施例之製程方法於各步驟之對應結構示意圖;第10A圖至第10C圖係分別為依本發明第十實施例之製程方法於各步驟之對應結構示意圖;第11A圖至第11B圖係分別為依本發明一實施例之製程方法於各步驟之對應結構示意圖。 Figures 1A to 1I are schematic diagrams of the corresponding structures in each step of the manufacturing method according to the first embodiment of the present invention; Figures 2A to 2H are respectively the schematic diagrams of the manufacturing method according to the second embodiment of the present invention in each step. Schematic diagrams corresponding to the steps; Figures 3A to 3H are schematic diagrams of the corresponding structures in each step of the process method according to the third embodiment of the present invention; Figures 4A to 4C are the schematic diagrams according to the fourth embodiment of the present invention. Figures 5A to 5G are schematic views of the structure according to the fifth embodiment of the present invention; Figures 6A to 6H are schematic views of the structure according to the sixth embodiment of the present invention; Figures 7A to 7F are schematic views of the structure according to the sixth embodiment of the present invention. Schematic diagram of the structure of the seventh embodiment of the present invention; Figures 8A to 8F are schematic diagrams of the corresponding structure of each step of the manufacturing method according to the eighth embodiment of the present invention; Figures 9A to 9I are respectively according to the present invention 10A to 10C are schematic diagrams of corresponding structures of each step of the manufacturing method according to the tenth embodiment of the present invention, respectively; FIGS. 11A to 11B The figures are schematic diagrams of corresponding structures of each step of a manufacturing method according to an embodiment of the present invention.

第一實施例 first embodiment

第1A圖至第1I圖係分別為依本發明第一實施例之製程方法於各步驟之對應結構示意圖。請參閱第1A圖以及第1B圖,其中第1A圖為第1B圖中 虛線AA’的剖面圖。根據本發明所揭露的光電半導體元件製程,提供一黏結基板101具有一表面1011,形成一黏著結構2在表面1011上,黏著結構2具有一厚度t,於本實施例中,厚度t的範圍介於1μm到10μm之間,較佳的是介於2μm到6μm之間。黏著結構2包含一黏結層202及一犧牲層201,黏結層202與犧牲層201並列在表面1011上與表面1011相接,如第1B圖所示之黏著結構2的上視圖,黏結層202與犧牲層201各具有特定的形狀。 FIG. 1A to FIG. 1I are schematic diagrams of corresponding structures in each step of the manufacturing method according to the first embodiment of the present invention, respectively. Please refer to Figure 1A and Figure 1B, where Figure 1A is Figure 1B Sectional view of dashed line AA'. According to the optoelectronic semiconductor device manufacturing process disclosed in the present invention, an adhesive substrate 101 having a surface 1011 is provided, and an adhesive structure 2 is formed on the surface 1011 , and the adhesive structure 2 has a thickness t. In this embodiment, the thickness t ranges between between 1 μm and 10 μm, preferably between 2 μm and 6 μm. The adhesive structure 2 includes an adhesive layer 202 and a sacrificial layer 201. The adhesive layer 202 and the sacrificial layer 201 are juxtaposed on the surface 1011 and connected to the surface 1011. As shown in FIG. 1B, the top view of the adhesive structure 2, the adhesive layer 202 and the The sacrificial layers 201 each have a specific shape.

黏結基板101的材料包含電絕緣基板或導電基板,電絕緣基板的材料包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、壓克力(Acryl)、氧化鋅(ZnO)、氮化鋁(AlN)、氧化二鋁鋰(LiAlO2)或陶瓷基板等;導電基板的材料包含矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)或金屬材料之一種或其組合。在本實施例中,黏結層202的材質與犧牲層201不同,黏結層202的材料包含苯并環丁烯(BCB);犧牲層201的材料包含有機材料,例如紫外光(UV)解離膠,包含丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)等;熱塑性塑膠,包含尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)等;或者無機材料,例如金屬包含鈦(Ti)、金(Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)或其組合,氧化物包含SiOx,或者氮化物包含SiNx等。 The material of the bonding substrate 101 includes an electrically insulating substrate or a conductive substrate, and the material of the electrically insulating substrate includes sapphire (Sapphire), diamond (Diamond), glass (Glass), quartz (Quartz), acrylic (Acryl), zinc oxide (ZnO) ), aluminum nitride (AlN), lithium aluminum oxide (LiAlO2), or ceramic substrates, etc.; materials for conductive substrates include silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), zinc oxide (ZnO), One or a combination of Gallium Nitride (GaN), Aluminum Nitride (AlN) or metallic materials. In this embodiment, the material of the adhesive layer 202 is different from that of the sacrificial layer 201. The material of the adhesive layer 202 includes benzocyclobutene (BCB); the material of the sacrificial layer 201 includes organic materials, such as ultraviolet (UV) dissociative adhesive, Contains Acrylic acid, Unsaturated polyester, Epoxy, Oxetane, Vinyl ether, etc.; Thermoplastics, including Nylon ), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS), polychlorinated Ethylene (PVC), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al), germanium (Ge) or combinations thereof, oxides including SiOx , or the nitride contains SiNx, etc.

接續如圖1C所示,提供一成長基板102,在成長基板102上具有以磊晶方式成長的一半導體磊晶疊層3,接著藉由黏著結構2將成長基板102及半導體磊晶疊層3,以加熱、加壓的方式黏結至表面1011上與黏結基板101黏合,其中黏結層202與犧牲層201皆與半導體磊晶疊層3相接。由於黏結層202的材質選擇不同於犧牲層201的材質,用以造成半導體磊晶疊層3與黏結層202之間的黏著 力不同於半導體磊晶疊層3與犧牲層201之間的黏著力,在本實施例中,半導體磊晶疊層3與黏結層202之間的黏著力大於半導體磊晶疊層3與犧牲層201之間的黏著力。 Next, as shown in FIG. 1C , a growth substrate 102 is provided, and a semiconductor epitaxial stack 3 grown in an epitaxial manner is provided on the growth substrate 102 , and then the growth substrate 102 and the semiconductor epitaxial stack 3 are formed by the adhesive structure 2 . , which is bonded to the surface 1011 by heating and pressing, and bonded to the bonding substrate 101 , wherein the bonding layer 202 and the sacrificial layer 201 are both connected to the semiconductor epitaxial stack 3 . Since the material of the adhesive layer 202 is different from that of the sacrificial layer 201 , it is used to cause adhesion between the semiconductor epitaxial stack 3 and the adhesive layer 202 . The force is different from the adhesive force between the semiconductor epitaxial stack 3 and the sacrificial layer 201. In this embodiment, the adhesive force between the semiconductor epitaxial stack 3 and the adhesive layer 202 is greater than that between the semiconductor epitaxial stack 3 and the sacrificial layer. Adhesion between 201.

其中,半導體磊晶疊層3包括至少一第一半導體層301具有第一導電型態,一轉換單元302以及一第二半導體層303具有第二導電型態,依序形成於成長基板102之上。第一半導體層301和第二半導體層303可為兩個單層結構或兩個多層結構(多層結構係指兩層或兩層以上)。第一半導體層301和第二半導體層303具有不同的導電型態、電性、極性或依摻雜的元素以提供電子或電洞。當第一半導體層301為p型半導體,第二半導體層303可為相異電性的n型半導體,反之,當第一半導體層301為n型半導體,第二半導體層303可為相異電性的p型半導體。轉換單元302形成在第一半導體層301和第二半導體層303之間,轉換單元302係將光能和電能相互轉換或導致轉換。半導體磊晶疊層3可進一步加工應用於一半導體元件、設備、產品、電路,以進行或導致光能和電能相互轉換。具體而言,半導體磊晶疊層3可進一步加工成為一發光二極體(LED)、一雷射二極體(LD)、一太陽能電池或一液晶顯示器其中之一。以發光二極體為例,可以藉由改變半導體磊晶疊層3裡的其中一層或多層的物理及化學組成,調整發出的光波長。常用的材料為磷化鋁鎵銦(aluminum gallium indium phosphide,AlGaInP)系列、氮化鋁鎵銦(aluminum gallium indium nitride,AlGaInN)系列、氧化鋅系列(zinc oxide,ZnO)。轉換單元302可為單異質結構(single heterostructure,SH),雙異質結構(double heterostructure,DH),雙側雙異質結(double-side double heterostructure,DDH),多層量子井(multi-quantum well,MWQ)。具體來說,轉換單元302可為中性、p型或n型電性的半導體。施以電流通過半導體磊晶疊層3時,轉換單元302會發光。當轉換單元302以磷化鋁銦鎵(AlGaInP)為基礎的材 料時,會發出紅、橙、黃光之琥珀色系的光;當以氮化鋁鎵銦(AlGaInN)為基礎的材料時,會發出藍或綠光。 The semiconductor epitaxial stack 3 includes at least a first semiconductor layer 301 having a first conductivity type, a conversion unit 302 and a second semiconductor layer 303 having a second conductivity type, and are sequentially formed on the growth substrate 102 . The first semiconductor layer 301 and the second semiconductor layer 303 may be two single-layer structures or two multi-layer structures (a multi-layer structure refers to two or more layers). The first semiconductor layer 301 and the second semiconductor layer 303 have different conductivity types, electrical properties, polarities or elements depending on doping to provide electrons or holes. When the first semiconductor layer 301 is a p-type semiconductor, the second semiconductor layer 303 can be an n-type semiconductor with different electrical properties. On the contrary, when the first semiconductor layer 301 is an n-type semiconductor, the second semiconductor layer 303 can be a different electrical conductivity. a p-type semiconductor. The conversion unit 302 is formed between the first semiconductor layer 301 and the second semiconductor layer 303, and the conversion unit 302 converts light energy and electric energy into each other or causes conversion. The semiconductor epitaxial stack 3 can be further processed and applied to a semiconductor device, device, product, or circuit to perform or cause the mutual conversion of light energy and electrical energy. Specifically, the semiconductor epitaxial stack 3 can be further processed into one of a light emitting diode (LED), a laser diode (LD), a solar cell or a liquid crystal display. Taking the light emitting diode as an example, the wavelength of the emitted light can be adjusted by changing the physical and chemical composition of one or more layers in the semiconductor epitaxial stack 3 . Commonly used materials are aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide series (zinc oxide, ZnO). The conversion unit 302 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MWQ) ). Specifically, the conversion unit 302 can be a neutral, p-type or n-type semiconductor. When a current is applied through the semiconductor epitaxial stack 3, the conversion unit 302 emits light. When the conversion unit 302 is based on aluminum indium gallium phosphide (AlGaInP) When the material is used, it will emit amber light of red, orange and yellow light; when it is based on aluminum gallium indium nitride (AlGaInN), it will emit blue or green light.

接續如圖1D所示,將成長基板102與半導體磊晶疊層3分離並露出半導體磊晶疊層3之一表面3011。分離成長基板102的方法包括利用光照法,使用雷射光穿透成長基板102照射成長基板102與半導體磊晶疊層3之間的界面,來達到分離半導體磊晶疊層3與成長基板102的目的。另外,也可以利用濕式蝕刻法直接移除成長基板102,或移除成長基板102與半導體磊晶疊層3之間的介面層(未顯示),進而分離成長基板102與半導體磊晶疊層3。除此之外,還可以於高溫下利用蒸氣蝕刻直接移除成長基板102與半導體磊晶疊層3之間的介面層(未顯示),達到成長基板102與半導體磊晶疊層3分離之目的。 Next, as shown in FIG. 1D , the growth substrate 102 is separated from the semiconductor epitaxial stack 3 and a surface 3011 of the semiconductor epitaxial stack 3 is exposed. The method for separating the growth substrate 102 includes using an illumination method, using laser light to penetrate the growth substrate 102 to irradiate the interface between the growth substrate 102 and the semiconductor epitaxial stack 3 to achieve the purpose of separating the semiconductor epitaxial stack 3 and the growth substrate 102 . In addition, wet etching can also be used to directly remove the growth substrate 102 , or remove the interface layer (not shown) between the growth substrate 102 and the semiconductor epitaxial stack 3 , thereby separating the growth substrate 102 and the semiconductor epitaxial stack 3 3. Besides, the interface layer (not shown) between the growth substrate 102 and the semiconductor epitaxial stack 3 can also be directly removed by vapor etching at high temperature, so as to achieve the purpose of separating the growth substrate 102 and the semiconductor epitaxial stack 3 .

如圖1E所示,在半導體磊晶疊層3之表面3011上形成一圖形化的黏著介質4對應犧牲層201,其中形成圖形化的黏著介質4的方式包含先形成一整層的黏著介質4在表面3011上,接著利用黃光微影製程或者圖形化蝕刻的方式,形成圖形化的黏著介質4,黃光微影製程及圖形化蝕刻係為一般習知的半導體製程。黏著介質4的材料包含有機材料,例如丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)、尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)、苯并環丁烯(BCB)等;或者無機材料,例如金屬包含鈦(Ti)、金(Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)、銅(Cu)或其組合,氧化物包含銦錫氧化物(ITO)、鎘錫氧化物(CTO)、銻氧化錫、氧化銦鋅、氧化鋅鋁、及鋅錫氧化物、氧化鋅(ZnO)、氧化矽(SiOx),或者氮化物包含氮化矽(SiNx)等。 As shown in FIG. 1E , a patterned adhesive medium 4 is formed on the surface 3011 of the semiconductor epitaxial stack 3 corresponding to the sacrificial layer 201 , wherein the method of forming the patterned adhesive medium 4 includes first forming a whole layer of the adhesive medium 4 On the surface 3011, a patterned adhesive medium 4 is then formed by a yellow light lithography process or a patterned etching method. The yellow light lithography process and the patterned etching are generally known semiconductor manufacturing processes. The material of the adhesive medium 4 includes organic materials, such as acrylic acid, unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane), vinyl ether (Vinyl ether) , nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS) ), polyvinyl chloride (PVC), benzocyclobutene (BCB), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al) , germanium (Ge), copper (Cu) or combinations thereof, oxides including indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide , zinc oxide (ZnO), silicon oxide (SiOx), or nitrides including silicon nitride (SiNx) and the like.

接續如第1F圖所示,圖形化半導體磊晶疊層3及黏著結構2並露出表面1011以形成互相隔開的複數個半導體磊晶疊層,其中複數個半導體磊晶疊 層包含至少一個第一半導體磊晶疊層31及至少一個第二半導體磊晶疊層32,在每一個第一半導體磊晶疊層31上具有黏著介質4,而每一個第二半導體磊晶疊層32的表面3011上則無黏著介質4。圖形化半導體磊晶疊層3及黏著結構2的方法包含乾蝕刻或濕蝕刻,在本實施例中,使用乾蝕刻製程使第一半導體磊晶疊層31及第二半導體磊晶疊層32之間的間隔寬度w盡量縮小,以避免蝕刻過多的半導體磊晶疊層3造成浪費,本實施例的間隔寬度w介於1μm及10μm,較佳的為5μm。 Continuing as shown in FIG. 1F, the semiconductor epitaxial stack 3 and the adhesive structure 2 are patterned and the surface 1011 is exposed to form a plurality of semiconductor epitaxial stacks separated from each other, wherein a plurality of semiconductor epitaxial stacks The layers include at least one first semiconductor epitaxial stack 31 and at least one second semiconductor epitaxial stack 32, each first semiconductor epitaxial stack 31 having an adhesive medium 4, and each second semiconductor epitaxial stack 32 There is no adhesive medium 4 on the surface 3011 of the layer 32 . The method of patterning the semiconductor epitaxial stack 3 and the adhesive structure 2 includes dry etching or wet etching. In this embodiment, a dry etching process is used to make the first semiconductor epitaxial stack 31 and the second semiconductor epitaxial stack 32 The interval width w between them is as small as possible to avoid waste caused by etching too much semiconductor epitaxial stack 3 . The interval width w in this embodiment is between 1 μm and 10 μm, preferably 5 μm.

接續如第1G圖所示,提供一擷取元件103藉由加溫、加壓或者利用擷取元件103本身具有之黏性,與黏著介質4黏結。擷取元件103包含導電材料,例如導電基板或印刷電路板,其中導電基板的材料包含矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)或金屬材料之一種或其組合;印刷電路板包含單面印刷電路板、雙面印刷電路板、多層印刷電路板或軟性電路板;或非導電材料,例如包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、壓克力(Acryl)、氧化鋅(ZnO)、氮化鋁(AlN)、氧化二鋁鋰(LiAlO2)、陶瓷基板或發泡聚苯乙烯(EPS)膠帶等,其中當以發泡聚苯乙烯(EPS)膠帶形成擷取元件103時,可提供一硬質基板與發泡聚苯乙烯(EPS)膠帶黏合,用以支撐發泡聚苯乙烯(EPS)膠帶,以避免發泡聚苯乙烯(EPS)膠帶沾黏第二半導體磊晶疊層32的表面3011。在另一實施例中,如第11A圖所示,擷取元件103可進一步包含一軟性基板1032及一支撐結構1031,其中軟性基板1032的材料包含聚酯樹脂(polyester resin;PET)、聚萘二甲酸乙二醇酯(polyethylene naphthalate;PEN)或聚醯亞胺(polyimide;PI),支撐結構的材料包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)或壓克力(Acryl)等硬質的基板,用以支撐軟性基板1032。 Continuing as shown in FIG. 1G , a capturing element 103 is provided to adhere to the adhesive medium 4 by heating, pressing or using the viscosity of the capturing element 103 itself. The extraction element 103 includes a conductive material, such as a conductive substrate or a printed circuit board, wherein the material of the conductive substrate includes silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), zinc oxide (ZnO), gallium nitride ( GaN), Aluminum Nitride (AlN), or one or a combination of metallic materials; printed circuit boards including single-sided, double-sided, multilayer, or flexible circuit boards; or non-conductive materials such as those containing Sapphire (Sapphire), Diamond (Diamond), Glass (Glass), Quartz (Quartz), Acrylic (Acryl), Zinc Oxide (ZnO), Aluminum Nitride (AlN), Lithium Aluminum Oxide (LiAlO2), Ceramic Substrate Or expanded polystyrene (EPS) tape, etc., wherein when the capturing element 103 is formed with the expanded polystyrene (EPS) tape, a rigid substrate can be provided for bonding with the expanded polystyrene (EPS) tape for bonding The expanded polystyrene (EPS) tape is supported to prevent the expanded polystyrene (EPS) tape from sticking to the surface 3011 of the second semiconductor epitaxial stack 32 . In another embodiment, as shown in FIG. 11A , the capturing element 103 may further include a flexible substrate 1032 and a supporting structure 1031 , wherein the material of the flexible substrate 1032 includes polyester resin (PET), polynaphthalene Polyethylene naphthalate (PEN) or polyimide (polyimide; PI), the material of the support structure includes sapphire (Sapphire), diamond (Diamond), glass (Glass), quartz (Quartz) or acrylic A hard substrate such as Acryl is used to support the flexible substrate 1032 .

在另一實施例中,可以先將圖形化的黏著介質4形成在擷取元件103上,使用對位黏合的技術,將黏著介質4與第一半導體磊晶疊層31對齊後,藉由加溫及加壓的方式,使黏著介質4與第一半導體磊晶疊層31黏結。 In another embodiment, the patterned adhesive medium 4 can be formed on the capture element 103 first, and the adhesive medium 4 can be aligned with the first semiconductor epitaxial layer 31 by using the alignment bonding technique. The adhesive medium 4 is bonded to the first semiconductor epitaxial stack 31 in a warm and pressurized manner.

接續如第1H圖所示,若犧牲層201與第一半導體磊晶疊層31的黏著力小於黏著介質4與第一半導體磊晶疊層31的黏著力的時候,可直接分別施以反方向的力量於擷取元件103及黏結基板101,使第一半導體磊晶疊層31與犧牲層201分離而不會傷害到第一半導體磊晶疊層31的結構,例如當犧牲層201的材質為紫外光(UV)解離材料包含丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)等,使用紫外光(UV)照射犧牲層201可使犧牲層201的黏著力降低或消失,再分別施以反方向的力量於擷取元件103及黏結基板101,使得第一半導體磊晶疊層31與犧牲層201分離;或者,當犧牲層201的材質為熱塑性塑膠包含尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)等,加熱犧牲層201可使犧牲層201之間的黏著力降低或消失,再分別施以反方向的力量於擷取元件103及黏結基板101,使得第一半導體磊晶疊層31與犧牲層201分離;或者當黏著介質4係為苯并環丁烯(BCB)等具有高黏著力的材料構成,犧牲層201的材質係為黏著力較低的材料所構成時,可不需將犧牲層201施以光照射或者加熱等方式進行改質,直接分別施以反方向的力量於擷取元件103及黏結基板101,使得第一半導體磊晶疊層31與犧牲層201分離,其中黏著力較低的材料包含金屬材料,例如鈦(Ti)、鋁(Al)、鈦鎢合金(TiW)等、氧化物,例如氧化矽(SiOx)、或者氮化物,例如氮化矽(SiNx)。 Continuing as shown in FIG. 1H, if the adhesive force between the sacrificial layer 201 and the first semiconductor epitaxial stack 31 is smaller than the adhesive force between the adhesive medium 4 and the first semiconductor epitaxial stack 31, it can be directly applied in the opposite direction. The power is used to extract the element 103 and the bonding substrate 101 to separate the first semiconductor epitaxial layer 31 from the sacrificial layer 201 without damaging the structure of the first semiconductor epitaxial layer 31. For example, when the material of the sacrificial layer 201 is Ultraviolet (UV) dissociation materials include Acrylic acid, Unsaturated polyester, Epoxy, Oxetane, Vinyl ether, etc., Using ultraviolet light (UV) to irradiate the sacrificial layer 201 can reduce or disappear the adhesive force of the sacrificial layer 201, and then apply force in opposite directions to the extraction element 103 and the bonding substrate 101 respectively, so that the first semiconductor epitaxial stack 31 and the The sacrificial layer 201 is separated; or, when the material of the sacrificial layer 201 is thermoplastic plastic including nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate Ester (PC), acrylonitrile-butadiene-styrene (ABS), polyvinyl chloride (PVC), etc., heating the sacrificial layer 201 can reduce or disappear the adhesion between the sacrificial layers 201, and then apply the opposite directions respectively. The force is used to extract the element 103 and the bonding substrate 101, so that the first semiconductor epitaxial stack 31 is separated from the sacrificial layer 201; or when the bonding medium 4 is made of a material with high adhesion such as benzocyclobutene (BCB) When the material of the sacrificial layer 201 is made of a material with low adhesive force, the sacrificial layer 201 does not need to be modified by light irradiation or heating, and the force in the opposite direction is directly applied to the capture element 103 and the bonding substrate. 101, so that the first semiconductor epitaxial stack 31 is separated from the sacrificial layer 201, wherein the material with lower adhesion includes metal materials, such as titanium (Ti), aluminum (Al), titanium-tungsten alloy (TiW), etc., oxides, For example, silicon oxide (SiOx), or nitride, such as silicon nitride (SiNx).

此外,如第1I圖所示,當犧牲層201的材質為金屬材料,例如鈦(Ti)、鋁(Al)、鈦鎢(TiW)、銀(Ag)等,或者含矽的材料,例如氧化矽(SiOx)、氮 化矽(SiNx)或者多晶矽(poly-Si)等材料,可使用濕蝕刻或者蒸氣蝕刻的方式,移除犧牲層201,再分別施以反方向的力量於擷取元件103及黏結基板101,使得第一半導體磊晶疊層31與犧牲層201分離,本實施例中,濕蝕刻使用的蝕刻液包含氫氟酸,蒸氣蝕刻使用的化學材料包含氟化氫(HF)蒸氣。 In addition, as shown in FIG. 1I, when the material of the sacrificial layer 201 is a metal material, such as titanium (Ti), aluminum (Al), titanium tungsten (TiW), silver (Ag), etc., or a material containing silicon, such as oxide Silicon (SiOx), Nitrogen The sacrificial layer 201 can be removed by wet etching or vapor etching for materials such as silicide (SiNx) or polysilicon (poly-Si), and then the force in the opposite direction is applied to the extraction element 103 and the bonding substrate 101 respectively, so that the The first semiconductor epitaxial stack 31 is separated from the sacrificial layer 201. In this embodiment, the etchant used for wet etching includes hydrofluoric acid, and the chemical material used for vapor etching includes hydrogen fluoride (HF) vapor.

在另一實施例中,如前述擷取元件103包含一軟性基板1032及一支撐結構1031,當第一半導體磊晶疊層31與犧牲層201分離後,接續如第11B圖所示,可將軟性基板1032與支撐結構1031分離,進一步製作成軟性顯示器。 In another embodiment, as the aforementioned capture element 103 includes a flexible substrate 1032 and a support structure 1031 , after the first semiconductor epitaxial stack 31 is separated from the sacrificial layer 201 , as shown in FIG. 11B , the The flexible substrate 1032 is separated from the support structure 1031, and is further fabricated into a flexible display.

第二實施例 Second Embodiment

第2A圖至第2H圖係分別為依本發明第二實施例之製程方法於各步驟之對應結構示意圖。如第2A圖所示,本實施例與前述第一實施例的差異在於黏著結構2的結構不同。本實施例中,犧牲層201位於黏結基板101的表面1011與黏結層202之間。後續的製程如第2B圖至第2H圖所示,皆與前述第一實施相同,其中,經由本實施例所揭露之製程所形成的每一個第一半導體磊晶疊層31的表面311上,都有黏結層202。 FIG. 2A to FIG. 2H are schematic diagrams of corresponding structures in each step of the manufacturing method according to the second embodiment of the present invention, respectively. As shown in FIG. 2A , the difference between this embodiment and the aforementioned first embodiment lies in the structure of the adhesive structure 2 . In this embodiment, the sacrificial layer 201 is located between the surface 1011 of the bonding substrate 101 and the bonding layer 202 . As shown in FIG. 2B to FIG. 2H, the subsequent process is the same as that of the aforementioned first implementation, wherein, on the surface 311 of each first semiconductor epitaxial stack 31 formed by the process disclosed in this embodiment, Both have adhesive layers 202 .

第三實施例 Third Embodiment

第3A圖至第3H圖係分別為依本發明第三實施例之製程方法於各步驟之對應結構示意圖。如第3A圖所示,本實施例中,先將犧牲層201與黏結層202分別形成在半導體磊晶疊層3的表面311及黏結基板101的表面1011上,接續如第3B圖所示,藉由黏結層202及犧牲層201,以加熱、加壓的方式將半導體磊晶疊層3與黏結基板101黏合,由於黏結層202的材料包含苯并環丁烯(BCB),在上述黏合過程中犧牲層201會將犧牲層201與黏結基板101之間的黏結層202材料推開,使得犧牲層201與黏結基板101之間的黏結層202厚度小於半導體磊晶疊層3與黏結基板101之間的黏結層202厚度,以形成圖中黏著結構2。本實施例與前述第一實施例的差異在於黏著結構2的結構不同,犧牲層201位於黏結層202之 上,不與黏結基板101的表面1011相接。後續的製程如第3B圖至第3H圖所示,皆與前述第一實施相同。 FIG. 3A to FIG. 3H are schematic diagrams of corresponding structures in each step of the manufacturing method according to the third embodiment of the present invention, respectively. As shown in FIG. 3A, in this embodiment, the sacrificial layer 201 and the bonding layer 202 are first formed on the surface 311 of the semiconductor epitaxial stack 3 and the surface 1011 of the bonding substrate 101, respectively, and then as shown in FIG. 3B, Through the adhesive layer 202 and the sacrificial layer 201, the semiconductor epitaxial stack 3 is bonded to the bonding substrate 101 by heating and pressing. Since the material of the bonding layer 202 includes benzocyclobutene (BCB), in the above bonding process The middle sacrificial layer 201 will push away the material of the bonding layer 202 between the sacrificial layer 201 and the bonding substrate 101 , so that the thickness of the bonding layer 202 between the sacrificial layer 201 and the bonding substrate 101 is smaller than that between the semiconductor epitaxial stack 3 and the bonding substrate 101 . The thickness of the adhesive layer 202 between the two is to form the adhesive structure 2 in the figure. The difference between this embodiment and the aforementioned first embodiment is that the structure of the adhesive structure 2 is different, and the sacrificial layer 201 is located between the adhesive layer 202 . , not in contact with the surface 1011 of the bonding substrate 101 . Subsequent manufacturing processes are shown in FIG. 3B to FIG. 3H , which are the same as those of the first implementation.

第四實施例 Fourth Embodiment

第4A圖至第4C圖為依本發明第四實施例之結構示意圖。如第4A圖所示,本實施例與前述第三實施例的差異在於每一個第一半導體磊晶疊層31的表面311,都與圖形化的犧牲層201及黏結層202相接。或者,如第4B圖所示,本實施例與前述第一實施例的差異在於每一個第一半導體磊晶疊層31的表面311,都與圖形化的犧牲層201及黏結層202相接。或者,如第4C圖所示,本實施例與前述第

Figure 110105147-A0305-02-0011-72
二實施例的差異在於每一個第一半導體磊晶疊層31所對應的圖形化的犧牲層201被黏結層202所覆蓋,並且與黏結基板101黏結。 4A to 4C are schematic structural diagrams of a fourth embodiment according to the present invention. As shown in FIG. 4A , the difference between this embodiment and the aforementioned third embodiment is that the surface 311 of each first semiconductor epitaxial stack 31 is in contact with the patterned sacrificial layer 201 and the bonding layer 202 . Alternatively, as shown in FIG. 4B , the difference between this embodiment and the aforementioned first embodiment is that the surface 311 of each first semiconductor epitaxial stack 31 is in contact with the patterned sacrificial layer 201 and the bonding layer 202 . Alternatively, as shown in Figure 4C, this embodiment is the same as the aforementioned
Figure 110105147-A0305-02-0011-72
The difference between the two embodiments is that the patterned sacrificial layer 201 corresponding to each of the first semiconductor epitaxial stacks 31 is covered by the bonding layer 202 and bonded to the bonding substrate 101 .

第五實施例 Fifth Embodiment

第5A圖至第5G圖為依本發明第五實施例之結構示意圖。如第5A圖所示,根據本發明所揭露的光電半導體元件製程,提供一黏結基板101具有一表面1011,形成一黏著結構2在表面1011上,黏著結構2具有一厚度t,厚度t的範圍介於1μm到10μm之間,較佳的是介於2μm到6μm之間。黏結基板101的材料包含電絕緣基板或導電基板,電絕緣基板的材料包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、壓克力(Acryl)、氧化鋅(ZnO)、氮化鋁(AlN)、氧化二鋁鋰(LiAlO2)或陶瓷基板等;導電基板的材料包含矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)或金屬材料之一種或其組合。黏著結構2的材料包含有機材料,例如丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)、尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)、苯并環丁烯(BCB)等;或者無機材料,例如金屬包含鈦(Ti)、金 (Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)、銅(Cu)或其組合,氧化物包含銦錫氧化物(ITO)、鎘錫氧化物(CTO)、銻氧化錫、氧化銦鋅、氧化鋅鋁、及鋅錫氧化物、氧化鋅(ZnO)、氧化矽(SiOx),或者氮化物包含氮化矽(SiNx)等。提供一成長基板102,在成長基板102上具有以磊晶方式成長的一半導體磊晶疊層3,接著藉由黏著結構2將成長基板102及半導體磊晶疊層3黏結至表面1011上與黏結基板101黏合。其中,半導體磊晶疊層3包括至少一第一半導體層301具有第一導電型態,一轉換單元302以及一第二半導體層303具有第二導電型態,依序形成於成長基板102之上。第一半導體層301和第二半導體層303可為兩個單層結構或兩個多層結構(多層結構係指兩層或兩層以上)。第一半導體層301和第二半導體層303具有不同的導電型態、電性、極性或依摻雜的元素以提供電子或電洞。當第一半導體層301為p型半導體,第二半導體層303可為相異電性的n型半導體,反之,當第一半導體層301為n型半導體,第二半導體層303可為相異電性的p型半導體。轉換單元302形成在第一半導體層301和第二半導體層303之間,轉換單元302係將光能和電能相互轉換或導致轉換。半導體磊晶疊層3可進一步加工應用於一半導體元件、設備、產品、電路,以進行或導致光能和電能相互轉換。具體而言,半導體磊晶疊層3可進一步加工成為一發光二極體(LED)、一雷射二極體(LD)、一太陽能電池或一液晶顯示器其中之一。以發光二極體為例,可以藉由改變半導體磊晶疊層3裡的其中一層或多層的物理及化學組成,調整發出的光波長。常用的材料為磷化鋁鎵銦(aluminum gallium indium phosphide,AlGaInP)系列、氮化鋁鎵銦(aluminum gallium indium nitride,AlGaInN)系列、氧化鋅系列(zinc oxide,ZnO)。轉換單元302可為單異質結構(single heterostructure,SH),雙異質結構(double heterostructure,DH),雙側雙異質結(double-side double heterostructure,DDH),多層量子井(multi-quantum well,MWQ)。具體來說,轉換單元302可為中性、p型或n型電性的半導體。施以電流通過半導體磊晶疊層3時,轉換單元302 會發光。當轉換單元302以磷化鋁銦鎵(AlGaInP)為基礎的材料時,會發出紅、橙、黃光之琥珀色系的光;當以氮化鋁鎵銦(AlGaInN)為基礎的材料時,會發出藍或綠光。 5A to 5G are schematic structural diagrams according to a fifth embodiment of the present invention. As shown in FIG. 5A , according to the optoelectronic semiconductor device manufacturing process disclosed in the present invention, an adhesive substrate 101 having a surface 1011 is provided, and an adhesive structure 2 is formed on the surface 1011 , and the adhesive structure 2 has a thickness t in the range of thickness t Between 1 μm and 10 μm, preferably between 2 μm and 6 μm. The material of the bonding substrate 101 includes an electrically insulating substrate or a conductive substrate, and the material of the electrically insulating substrate includes sapphire (Sapphire), diamond (Diamond), glass (Glass), quartz (Quartz), acrylic (Acryl), zinc oxide (ZnO) ), aluminum nitride (AlN), lithium aluminum oxide (LiAlO2), or ceramic substrates, etc.; materials for conductive substrates include silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), zinc oxide (ZnO), One or a combination of Gallium Nitride (GaN), Aluminum Nitride (AlN) or metallic materials. The material of the adhesive structure 2 includes organic materials, such as acrylic acid, unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane), vinyl ether (Vinyl ether) , nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS) ), polyvinyl chloride (PVC), benzocyclobutene (BCB), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al), germanium (Ge), copper (Cu) or combinations thereof, oxides including indium tin oxide (ITO), cadmium tin oxide (CTO) , antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide, zinc oxide (ZnO), silicon oxide (SiOx), or nitrides including silicon nitride (SiNx) and the like. A growth substrate 102 is provided, and a semiconductor epitaxial stack 3 grown in an epitaxial manner is provided on the growth substrate 102 , and then the growth substrate 102 and the semiconductor epitaxial stack 3 are bonded to the surface 1011 by the adhesive structure 2 and bonded The substrate 101 is bonded. The semiconductor epitaxial stack 3 includes at least a first semiconductor layer 301 having a first conductivity type, a conversion unit 302 and a second semiconductor layer 303 having a second conductivity type, and are sequentially formed on the growth substrate 102 . The first semiconductor layer 301 and the second semiconductor layer 303 may be two single-layer structures or two multi-layer structures (a multi-layer structure refers to two or more layers). The first semiconductor layer 301 and the second semiconductor layer 303 have different conductivity types, electrical properties, polarities or elements depending on doping to provide electrons or holes. When the first semiconductor layer 301 is a p-type semiconductor, the second semiconductor layer 303 can be an n-type semiconductor with different electrical properties. On the contrary, when the first semiconductor layer 301 is an n-type semiconductor, the second semiconductor layer 303 can be a different electrical conductivity. a p-type semiconductor. The conversion unit 302 is formed between the first semiconductor layer 301 and the second semiconductor layer 303, and the conversion unit 302 converts light energy and electric energy into each other or causes conversion. The semiconductor epitaxial stack 3 can be further processed and applied to a semiconductor device, device, product, or circuit to perform or cause the mutual conversion of light energy and electrical energy. Specifically, the semiconductor epitaxial stack 3 can be further processed into one of a light emitting diode (LED), a laser diode (LD), a solar cell or a liquid crystal display. Taking the light emitting diode as an example, the wavelength of the emitted light can be adjusted by changing the physical and chemical composition of one or more layers in the semiconductor epitaxial stack 3 . Commonly used materials are aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide series (zinc oxide, ZnO). The conversion unit 302 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MWQ) ). Specifically, the conversion unit 302 can be a neutral, p-type or n-type semiconductor. When a current is applied through the semiconductor epitaxial stack 3, the conversion unit 302 will glow. When the conversion unit 302 is made of aluminum indium gallium phosphide (AlGaInP) based material, it will emit amber light of red, orange, and yellow light; when it is based on aluminum gallium indium nitride (AlGaInN) based material, it will emit light blue or green light.

在另一實施例中,黏著結構2可先形成在半導體磊晶疊層3的表面3012上,接著藉由黏著結構2將成長基板102及半導體磊晶疊層3黏結至黏結基板101的表面1011上與黏結基板101黏合。 In another embodiment, the adhesive structure 2 can be formed on the surface 3012 of the semiconductor epitaxial stack 3 first, and then the growth substrate 102 and the semiconductor epitaxial stack 3 are bonded to the surface 1011 of the bonding substrate 101 by the adhesive structure 2 is bonded to the bonding substrate 101 .

接續如圖5B所示,將成長基板102與半導體磊晶疊層3分離並露出半導體磊晶疊層3之一表面3011。分離成長基板102的方法包括利用光照法,使用雷射光穿透成長基板102照射成長基板102與半導體磊晶疊層3之間的界面,來達到分離半導體磊晶疊層3與成長基板102的目的。另外,也可以利用濕式蝕刻法直接移除成長基板102,或移除成長基板102與半導體磊晶疊層3之間的介面層(未顯示),進而分離成長基板102與半導體磊晶疊層3。除此之外,還可以於高溫下利用蒸氣蝕刻直接移除成長基板102與半導體磊晶疊層3之間的介面層(未顯示),達到成長基板102與半導體磊晶疊層3分離之目的。 Continuing as shown in FIG. 5B , the growth substrate 102 is separated from the semiconductor epitaxial stack 3 and a surface 3011 of the semiconductor epitaxial stack 3 is exposed. The method for separating the growth substrate 102 includes using an illumination method, using laser light to penetrate the growth substrate 102 to irradiate the interface between the growth substrate 102 and the semiconductor epitaxial stack 3 to achieve the purpose of separating the semiconductor epitaxial stack 3 and the growth substrate 102 . In addition, wet etching can also be used to directly remove the growth substrate 102 , or remove the interface layer (not shown) between the growth substrate 102 and the semiconductor epitaxial stack 3 , thereby separating the growth substrate 102 and the semiconductor epitaxial stack 3 3. Besides, the interface layer (not shown) between the growth substrate 102 and the semiconductor epitaxial stack 3 can also be directly removed by vapor etching at high temperature, so as to achieve the purpose of separating the growth substrate 102 and the semiconductor epitaxial stack 3 .

接續如圖5C所示,在半導體磊晶疊層3之表面3011上形成一圖形化的黏著介質4,其中形成圖形化的黏著介質4的方式包含先形成一整層的黏著介質4在表面3011上,接著利用黃光微影製程或者圖形化蝕刻的方式,形成圖形化的黏著介質4,黃光微影製程及圖形化蝕刻係為一般習知的半導體製程。黏著介質4的材料包含有機材料,例如丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)、尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)、苯并環丁烯(BCB)等;或者無機材料,例如金屬包含鈦(Ti)、金(Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)、銅(Cu)或其組合,氧化物包含銦錫氧化物(ITO)、鎘錫氧化物(CTO)、銻氧 化錫、氧化銦鋅、氧化鋅鋁、及鋅錫氧化物、氧化鋅(ZnO)、氧化矽(SiOx),或者氮化物包含氮化矽(SiNx)等。 Continuing as shown in FIG. 5C , a patterned adhesive medium 4 is formed on the surface 3011 of the semiconductor epitaxial stack 3 , wherein the method of forming the patterned adhesive medium 4 includes first forming a whole layer of the adhesive medium 4 on the surface 3011 Then, a patterned adhesive medium 4 is formed by a yellow light lithography process or a patterned etching method. The yellow light lithography process and the patterned etching are generally known semiconductor processes. The material of the adhesive medium 4 includes organic materials, such as acrylic acid, unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane), vinyl ether (Vinyl ether) , nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS) ), polyvinyl chloride (PVC), benzocyclobutene (BCB), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al) , germanium (Ge), copper (Cu) or a combination thereof, the oxides include indium tin oxide (ITO), cadmium tin oxide (CTO), antimony oxide Tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide, zinc oxide (ZnO), silicon oxide (SiOx), or nitrides including silicon nitride (SiNx) and the like.

接續如第5D圖所示,圖形化半導體磊晶疊層3及黏著結構2以露出表面1011,形成互相隔開的複數個半導體磊晶疊層,其中複數個半導體磊晶疊層包含至少一個第一半導體磊晶疊層31及至少一個第二半導體磊晶疊層32,本實施例中,如第5E圖所示第5D圖之上視圖,第一半導體磊晶疊層31的面積較第二半導體磊晶疊層32的面積小,且在每一個第一半導體磊晶疊層31上具有黏著介質4,而每一個第二半導體磊晶疊層31的表面3011上則無黏著介質4。圖形化半導體磊晶疊層3及黏著結構2的方法可包含乾蝕刻或濕蝕刻,在本實施例中使用屬於乾蝕刻的ICP蝕刻方式圖形化半導體磊晶疊層3及黏著結構2,使第一半導體磊晶疊層31及第二半導體磊晶疊層32之間的間隔寬度w盡量縮小,以避免蝕刻過多的半導體磊晶疊層3造成浪費,本實施例的間隔寬度w介於1μm及10μm,較佳的為5μm。 Continuing as shown in FIG. 5D, the semiconductor epitaxial stack 3 and the adhesive structure 2 are patterned to expose the surface 1011 to form a plurality of semiconductor epitaxial stacks separated from each other, wherein the plurality of semiconductor epitaxial stacks include at least one first A semiconductor epitaxial stack 31 and at least one second semiconductor epitaxial stack 32. In this embodiment, as shown in FIG. 5E and FIG. 5D, the area of the first semiconductor epitaxial stack 31 is larger than that of the second semiconductor epitaxial stack 31. The semiconductor epitaxial stacks 32 have a small area, and each of the first semiconductor epitaxial stacks 31 has an adhesive medium 4 , and each second semiconductor epitaxial stack 31 has no adhesive medium 4 on the surface 3011 . The method for patterning the semiconductor epitaxial stack 3 and the adhesive structure 2 may include dry etching or wet etching. The spacing width w between the first semiconductor epitaxial stack 31 and the second semiconductor epitaxial stack 32 is as small as possible to avoid waste caused by etching too much of the semiconductor epitaxial stack 3. The spacing width w in this embodiment is between 1 μm and 10 μm, preferably 5 μm.

接續如第5F圖所示,提供一擷取元件103藉由加溫、加壓或者利用擷取元件103本身具有之黏性,與黏著介質4黏結。擷取元件103包含導電材料,例如導電基板或印刷電路板,其中導電基板的材料包含矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)或金屬材料之一種或其組合;印刷電路板包含單面印刷電路板、雙面印刷電路板、多層印刷電路板或軟性電路板;或非導電材料,例如包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、壓克力(Acryl)、氧化鋅(ZnO)、氮化鋁(AlN)、氧化二鋁鋰(LiAlO2)、陶瓷基板或發泡聚苯乙烯(EPS)膠帶等,其中當以發泡聚苯乙烯(EPS)膠帶形成擷取元件103時,可提供一硬質基板與發泡聚苯乙烯(EPS)膠帶黏合,用以支撐發泡聚苯乙烯(EPS)膠帶,以避免發泡聚苯乙烯(EPS)膠帶沾黏第二半導體磊晶疊層32的表面3011。 Continuing as shown in FIG. 5F , a capturing element 103 is provided to adhere to the adhesive medium 4 by heating, pressurizing or utilizing the viscosity of the capturing element 103 itself. The extraction element 103 includes a conductive material, such as a conductive substrate or a printed circuit board, wherein the material of the conductive substrate includes silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), zinc oxide (ZnO), gallium nitride ( GaN), Aluminum Nitride (AlN), or one or a combination of metallic materials; printed circuit boards including single-sided, double-sided, multilayer, or flexible circuit boards; or non-conductive materials such as those containing Sapphire (Sapphire), Diamond (Diamond), Glass (Glass), Quartz (Quartz), Acrylic (Acryl), Zinc Oxide (ZnO), Aluminum Nitride (AlN), Lithium Aluminum Oxide (LiAlO2), Ceramic Substrate Or expanded polystyrene (EPS) tape, etc., wherein when the capturing element 103 is formed with the expanded polystyrene (EPS) tape, a rigid substrate can be provided for bonding with the expanded polystyrene (EPS) tape for bonding The expanded polystyrene (EPS) tape is supported to prevent the expanded polystyrene (EPS) tape from sticking to the surface 3011 of the second semiconductor epitaxial stack 32 .

在另一實施例中,如第11A圖所示,擷取元件103可進一步包含一軟性基板1032及一支撐結構1031,其中軟性基板1032的材料包含聚酯樹脂(polyester resin;PET)、聚萘二甲酸乙二醇酯(polyethylene naphthalate;PEN)或聚醯亞胺(polyimide;PI),支撐結構1031的材料包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)或壓克力(Acryl)等硬質的基板,用以支撐軟性基板1032。 In another embodiment, as shown in FIG. 11A , the capturing element 103 may further include a flexible substrate 1032 and a supporting structure 1031 , wherein the material of the flexible substrate 1032 includes polyester resin (PET), polynaphthalene polyethylene naphthalate (PEN) or polyimide (polyimide; PI), the material of the support structure 1031 includes sapphire (Sapphire), diamond (Diamond), glass (Glass), quartz (Quartz) or pressure A hard substrate such as Acryl is used to support the flexible substrate 1032 .

在另一實施例中,可以先將圖形化的黏著介質4形成在擷取元件103上,使用對位黏合的技術,將黏著介質4與第一半導體磊晶疊層31對齊後,藉由加溫及加壓的方式,使黏著介質4與第一半導體磊晶疊層31黏結,以形成如第5F圖所示之結構。 In another embodiment, the patterned adhesive medium 4 can be formed on the capture element 103 first, and the adhesive medium 4 can be aligned with the first semiconductor epitaxial layer 31 by using the alignment bonding technique. The adhesive medium 4 is bonded to the first semiconductor epitaxial stack 31 in a warm and pressurized manner to form the structure shown in FIG. 5F .

接續如第5G圖所示,使用濕蝕刻製程或蒸氣蝕刻製程蝕刻黏著結構2,並控制濕蝕刻製程或蒸氣蝕刻製程的時間,使第一半導體磊晶疊層31與黏結基板101完全分離,而第二半導體磊晶疊層32與黏結基板101之間留下部分的黏著結構2以支撐第二半導體磊晶疊層32。 Then, as shown in FIG. 5G , the adhesive structure 2 is etched by a wet etching process or a vapor etching process, and the time of the wet etching process or the vapor etching process is controlled to completely separate the first semiconductor epitaxial stack 31 from the adhesive substrate 101 , and Part of the adhesive structure 2 is left between the second semiconductor epitaxial stack 32 and the bonding substrate 101 to support the second semiconductor epitaxial stack 32 .

在另一實施例中,如前述擷取元件103包含一軟性基板1032及一支撐結構1031,當第一半導體磊晶疊層31與犧牲層201分離後,接續如第11B圖所示,可將軟性基板1032與支撐結構1031分離,進一步製作成軟性顯示器。 In another embodiment, as the aforementioned capture element 103 includes a flexible substrate 1032 and a support structure 1031 , after the first semiconductor epitaxial stack 31 is separated from the sacrificial layer 201 , as shown in FIG. 11B , the The flexible substrate 1032 is separated from the support structure 1031, and is further fabricated into a flexible display.

第六實施例 Sixth Embodiment

第6A圖至第6H圖為依本發明第六實施例之結構示意圖。如第6A圖所示,根據本發明所揭露的光電半導體元件製程,提供一黏結基板101具有一表面1011及一表面1012對應表面1011,黏結基板101具有至少一孔洞110從表面1011穿透到表面1012,黏結基板101的上視圖如第6B圖所示,其中第6A圖為第6B圖中虛線CC’的剖面圖。黏結基板101的材料包含電絕緣基板或導電基板,電絕緣基板的材料包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、 壓克力(Acryl)、氧化鋅(ZnO)、氮化鋁(AlN)、氧化二鋁鋰(LiAlO2)或陶瓷基板等;導電基板的材料包含矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)或金屬材料之一種或其組合。 6A to 6H are schematic structural diagrams according to a sixth embodiment of the present invention. As shown in FIG. 6A , according to the optoelectronic semiconductor device manufacturing process disclosed in the present invention, a bonding substrate 101 having a surface 1011 and a surface 1012 corresponding to the surface 1011 is provided, and the bonding substrate 101 has at least one hole 110 penetrating from the surface 1011 to the surface 1012 , the top view of the bonded substrate 101 is shown in FIG. 6B , wherein FIG. 6A is a cross-sectional view of the dotted line CC′ in FIG. 6B . The material of the bonding substrate 101 includes an electrically insulating substrate or a conductive substrate, and the material of the electrically insulating substrate includes Sapphire, Diamond, Glass, Quartz, Acrylic (Acryl), Zinc Oxide (ZnO), Aluminum Nitride (AlN), Lithium Aluminum Oxide (LiAlO2) or ceramic substrates, etc.; the materials of conductive substrates include silicon (Si), gallium arsenide (GaAs), carbide One or a combination of silicon (SiC), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN) or metal materials.

接續如第7C圖所示,提供一成長基板102,在成長基板102上具有以磊晶方式成長的一半導體磊晶疊層3,接著藉由一黏著結構2將半導體磊晶疊層3黏結至黏結基板101的表面1011上與黏結基板101黏合,孔洞110露出部分的黏著結構2。在本實施例中,黏著結構2可先形成在半導體磊晶疊層3的表面3012上,接著藉由黏著結構2將成長基板102及半導體磊晶疊層3黏結至黏結基板101的表面1011上與黏結基板101黏合。 Next, as shown in FIG. 7C , a growth substrate 102 is provided, and a semiconductor epitaxial stack 3 grown in an epitaxial manner is provided on the growth substrate 102 , and then the semiconductor epitaxial stack 3 is bonded to the growth substrate 102 by an adhesive structure 2 . The surface 1011 of the bonding substrate 101 is bonded to the bonding substrate 101 , and the hole 110 exposes part of the bonding structure 2 . In this embodiment, the adhesive structure 2 can be formed on the surface 3012 of the semiconductor epitaxial stack 3 first, and then the growth substrate 102 and the semiconductor epitaxial stack 3 are bonded to the surface 1011 of the bonding substrate 101 by the adhesive structure 2 Bonded with the bonding substrate 101 .

黏著結構2具有一厚度t,厚度t的範圍介於1μm到10μm之間,較佳的是介於2μm到6μm之間。黏著結構2的材料包含有機材料,例如丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)、尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)、苯并環丁烯(BCB)等;或者無機材料,例如金屬包含鈦(Ti)、金(Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)、銅(Cu)或其組合,氧化物包含銦錫氧化物(ITO)、鎘錫氧化物(CTO)、銻氧化錫、氧化銦鋅、氧化鋅鋁、及鋅錫氧化物、氧化鋅(ZnO)、氧化矽(SiOx),或者氮化物包含氮化矽(SiNx)等。半導體磊晶疊層3包括至少一第一半導體層301具有第一導電型態,一轉換單元302以及一第二半導體層303具有第二導電型態,依序形成於成長基板102之上。第一半導體層301和第二半導體層303可為兩個單層結構或兩個多層結構(多層結構係指兩層或兩層以上)。第一半導體層301和第二半導體層303具有不同的導電型態、電性、極性或依摻雜的元素以提供電子或電洞。當第一半導體層301為p型半導體,第二半導體層303可為相異電性的n型半導體,反之,當第一半導體層301為n型半 導體,第二半導體層303可為相異電性的p型半導體。轉換單元302形成在第一半導體層301和第二半導體層303之間,轉換單元302係將光能和電能相互轉換或導致轉換。半導體磊晶疊層3可進一步加工應用於一半導體元件、設備、產品、電路,以進行或導致光能和電能相互轉換。具體而言,半導體磊晶疊層3可進一步加工成為一發光二極體(LED)、一雷射二極體(LD)、一太陽能電池或一液晶顯示器其中之一。以發光二極體為例,可以藉由改變半導體磊晶疊層3裡的其中一層或多層的物理及化學組成,調整發出的光波長。常用的材料為磷化鋁鎵銦(aluminum gallium indium phosphide,AlGaInP)系列、氮化鋁鎵銦(aluminum gallium indium nitride,AlGaInN)系列、氧化鋅系列(zinc oxide,ZnO)。轉換單元302可為單異質結構(single heterostructure,SH),雙異質結構(double heterostructure,DH),雙側雙異質結(double-side double heterostructure,DDH),多層量子井(multi-quantum well,MWQ)。具體來說,轉換單元302可為中性、p型或n型電性的半導體。施以電流通過半導體磊晶疊層3時,轉換單元302會發光。當轉換單元302以磷化鋁銦鎵(AlGaInP)為基礎的材料時,會發出紅、橙、黃光之琥珀色系的光;當以氮化鋁鎵銦(AlGaInN)為基礎的材料時,會發出藍或綠光。 The adhesive structure 2 has a thickness t, and the thickness t ranges from 1 μm to 10 μm, preferably from 2 μm to 6 μm. The material of the adhesive structure 2 includes organic materials, such as acrylic acid, unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane), vinyl ether (Vinyl ether) , nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS) ), polyvinyl chloride (PVC), benzocyclobutene (BCB), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al) , germanium (Ge), copper (Cu) or combinations thereof, oxides including indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide , zinc oxide (ZnO), silicon oxide (SiOx), or nitrides including silicon nitride (SiNx) and the like. The semiconductor epitaxial stack 3 includes at least a first semiconductor layer 301 having a first conductivity type, a conversion unit 302 and a second semiconductor layer 303 having a second conductivity type, and are sequentially formed on the growth substrate 102 . The first semiconductor layer 301 and the second semiconductor layer 303 may be two single-layer structures or two multi-layer structures (a multi-layer structure refers to two or more layers). The first semiconductor layer 301 and the second semiconductor layer 303 have different conductivity types, electrical properties, polarities or elements depending on doping to provide electrons or holes. When the first semiconductor layer 301 is a p-type semiconductor, the second semiconductor layer 303 can be an n-type semiconductor with different electrical properties. On the contrary, when the first semiconductor layer 301 is an n-type semi-conductor A conductor, the second semiconductor layer 303 can be a p-type semiconductor with different electrical properties. The conversion unit 302 is formed between the first semiconductor layer 301 and the second semiconductor layer 303, and the conversion unit 302 converts light energy and electric energy into each other or causes conversion. The semiconductor epitaxial stack 3 can be further processed and applied to a semiconductor device, device, product, or circuit to perform or cause the mutual conversion of light energy and electrical energy. Specifically, the semiconductor epitaxial stack 3 can be further processed into one of a light emitting diode (LED), a laser diode (LD), a solar cell or a liquid crystal display. Taking the light emitting diode as an example, the wavelength of the emitted light can be adjusted by changing the physical and chemical composition of one or more layers in the semiconductor epitaxial stack 3 . Commonly used materials are aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide series (zinc oxide, ZnO). The conversion unit 302 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MWQ) ). Specifically, the conversion unit 302 can be a neutral, p-type or n-type semiconductor. When a current is applied through the semiconductor epitaxial stack 3, the conversion unit 302 emits light. When the conversion unit 302 is based on the material of aluminum indium gallium phosphide (AlGaInP), it will emit amber light of red, orange and yellow; when it is based on the material of aluminum gallium indium nitride (AlGaInN), it will emit light blue or green light.

接續如圖6D所示,將成長基板102與半導體磊晶疊層3分離並露出半導體磊晶疊層3之表面3011,以及形成一支撐結構5於黏結基板101的表面1012上、孔洞110的壁面1101上、以及從孔洞110顯露出的部分黏著結構2上。其中,分離成長基板102的方法可包含前述第一實施例中所描述之方法。支撐結構5的材料包含有機材料,例如紫外光(UV)解離膠,像是丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)等;熱塑性塑膠,像是尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯 (ABS)、聚氯乙烯(PVC)等;或者無機材料,例如金屬包含鈦(Ti)、金(Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)或其組合,氧化物包含氧化矽(SiOx),或者氮化物包含氮化矽(SiNx)等。 Continuing as shown in FIG. 6D , the growth substrate 102 is separated from the semiconductor epitaxial stack 3 to expose the surface 3011 of the semiconductor epitaxial stack 3 , and a support structure 5 is formed on the surface 1012 of the bonding substrate 101 and the walls of the holes 110 1101 , and on the part of the adhesive structure 2 exposed from the hole 110 . The method for separating the growth substrate 102 may include the method described in the foregoing first embodiment. The material of the support structure 5 includes organic materials, such as ultraviolet light (UV) dissociative glue, such as acrylic acid (Acrylic acid), unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane), vinyl ether (Vinyl ether), etc.; thermoplastics, such as nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate Esters (PC), Acrylonitrile-Butadiene-Styrene (ABS), polyvinyl chloride (PVC), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al), germanium (Ge) or its In combination, the oxide includes silicon oxide (SiOx), or the nitride includes silicon nitride (SiNx), or the like.

接續如第6E圖所示,在半導體磊晶疊層3之表面3011上形成一圖形化的黏著介質4對應孔洞110,其中形成圖形化的黏著介質4的方式包含先形成一整層的黏著介質4在表面3011上,接著利用黃光微影製程或者圖形化蝕刻的方式,形成圖形化的黏著介質4,黃光微影製程及圖形化蝕刻係為一般習知的半導體製程。黏著介質4的材料包含有機材料,例如丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)、尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)等;或者無機材料,例如金屬包含鈦(Ti)、金(Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)、銅(Cu)或其組合,氧化物包含銦錫氧化物(ITO)、鎘錫氧化物(CTO)、銻氧化錫、氧化銦鋅、氧化鋅鋁、及鋅錫氧化物、氧化鋅(ZnO)、氧化矽(SiOx),或者氮化物包含氮化矽(SiNx)等。 Continuing as shown in FIG. 6E, a patterned adhesive medium 4 is formed on the surface 3011 of the semiconductor epitaxial stack 3 corresponding to the holes 110, wherein the method of forming the patterned adhesive medium 4 includes first forming a whole layer of the adhesive medium 4. On the surface 3011, a patterned adhesive medium 4 is then formed by a yellow light lithography process or a patterned etching method. The yellow light lithography process and the patterned etching are commonly known semiconductor processes. The material of the adhesive medium 4 includes organic materials, such as acrylic acid, unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane), vinyl ether (Vinyl ether) , nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS) ), polyvinyl chloride (PVC), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al), germanium (Ge), copper (Cu) ) or a combination thereof, the oxides include indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide, zinc oxide (ZnO), silicon oxide (SiOx), or the nitride includes silicon nitride (SiNx) or the like.

接續如第6F圖所示,圖形化半導體磊晶疊層3及黏著結構2並露出表面1011以形成互相隔開的複數個半導體磊晶疊層,其中複數個半導體磊晶疊層包含至少一個第一半導體磊晶疊層31及至少一個第二半導體磊晶疊層32,在每一個第一半導體磊晶疊層31上具有黏著介質4,而每一個第二半導體磊晶疊層32的表面3011上則無黏著介質4,其中,第一半導體磊晶疊層31在孔洞110上,因此第一半導體磊晶疊層31與黏結基板101之間的黏著力小於第二半導體磊晶疊層32與黏結基板101之間的黏著力。圖形化半導體磊晶疊層3及黏著結構2的方法包含乾蝕刻或濕蝕刻,在本實施例中使用乾蝕刻製成使第一半導體磊晶疊層 31及第二半導體磊晶疊層32之間的間隔寬度w盡量縮小,以避免蝕刻過多的半導體磊晶疊層3造成浪費,本實施例的間隔寬度w介於1μm及10μm,較佳的為5μm。 Continuing as shown in FIG. 6F, the semiconductor epitaxial stack 3 and the adhesive structure 2 are patterned and the surface 1011 is exposed to form a plurality of semiconductor epitaxial stacks separated from each other, wherein the plurality of semiconductor epitaxial stacks include at least one first A semiconductor epitaxial stack 31 and at least one second semiconductor epitaxial stack 32 with an adhesive medium 4 on each of the first semiconductor epitaxial stacks 31 , and a surface 3011 of each second semiconductor epitaxial stack 32 The above is the non-adhesive medium 4, wherein the first semiconductor epitaxial stack 31 is on the hole 110, so the adhesive force between the first semiconductor epitaxial stack 31 and the bonding substrate 101 is smaller than that between the second semiconductor epitaxial stack 32 and the bonding substrate 101. Adhesion between the bonded substrates 101 . The method of patterning the semiconductor epitaxial stack 3 and the adhesive structure 2 includes dry etching or wet etching. In this embodiment, dry etching is used to form the first semiconductor epitaxial stack. The interval width w between 31 and the second semiconductor epitaxial stack 32 is minimized as much as possible to avoid waste caused by etching too much semiconductor epitaxial stack 3. The interval width w in this embodiment is between 1 μm and 10 μm, preferably 5μm.

接續如第6G圖所示提供一擷取元件103藉由加溫、加壓或者利用擷取元件103本身具有之黏性,與黏著介質4黏結。擷取元件103包含導電材料,例如導電基板或印刷電路板,其中導電基板的材料包含矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)或金屬材料之一種或其組合;印刷電路板包含單面印刷電路板、雙面印刷電路板、多層印刷電路板或軟性電路板;或非導電材料,例如包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、壓克力(Acryl)、氧化鋅(ZnO)、氮化鋁(AlN)、氧化二鋁鋰(LiAlO2)、陶瓷基板或發泡聚苯乙烯(EPS)膠帶等,其中當以發泡聚苯乙烯(EPS)膠帶形成擷取元件103時,可提供一硬質基板與發泡聚苯乙烯(EPS)膠帶黏合,用以支撐發泡聚苯乙烯(EPS)膠帶,以避免發泡聚苯乙烯(EPS)膠帶沾黏第二半導體磊晶疊層32的表面3011。 Next, as shown in FIG. 6G, a capturing element 103 is provided to adhere to the adhesive medium 4 by heating, pressing or using the viscosity of the capturing element 103 itself. The extraction element 103 includes a conductive material, such as a conductive substrate or a printed circuit board, wherein the material of the conductive substrate includes silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), zinc oxide (ZnO), gallium nitride ( GaN), Aluminum Nitride (AlN), or one or a combination of metallic materials; printed circuit boards including single-sided, double-sided, multilayer, or flexible circuit boards; or non-conductive materials such as those containing Sapphire (Sapphire), Diamond (Diamond), Glass (Glass), Quartz (Quartz), Acrylic (Acryl), Zinc Oxide (ZnO), Aluminum Nitride (AlN), Lithium Aluminum Oxide (LiAlO2), Ceramic Substrate Or expanded polystyrene (EPS) tape, etc., wherein when the capturing element 103 is formed with the expanded polystyrene (EPS) tape, a rigid substrate can be provided for bonding with the expanded polystyrene (EPS) tape for bonding The expanded polystyrene (EPS) tape is supported to prevent the expanded polystyrene (EPS) tape from sticking to the surface 3011 of the second semiconductor epitaxial stack 32 .

在另一實施例中,如第11A圖所示,擷取元件103可進一步包含一軟性基板1032及一支撐結構1031,其中軟性基板1032的材料包含聚酯樹脂(polyester resin;PET)、聚萘二甲酸乙二醇酯(polyethylene naphthalate;PEN)或聚醯亞胺(polyimide;PI),支撐結構的材料包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)或壓克力(Acryl)等硬質的基板,用以支撐軟性基板1032。 In another embodiment, as shown in FIG. 11A , the capturing element 103 may further include a flexible substrate 1032 and a supporting structure 1031 , wherein the material of the flexible substrate 1032 includes polyester resin (PET), polynaphthalene Polyethylene naphthalate (PEN) or polyimide (polyimide; PI), the material of the support structure includes sapphire (Sapphire), diamond (Diamond), glass (Glass), quartz (Quartz) or acrylic A hard substrate such as Acryl is used to support the flexible substrate 1032 .

在另一實施例中,可以先將圖形化的黏著介質4形成在擷取元件103上,使用對位黏合的技術,將黏著介質4與第一半導體磊晶疊層31對齊後,藉由加溫及加壓的方式,使黏著介質4與第一半導體磊晶疊層31黏結。 In another embodiment, the patterned adhesive medium 4 can be formed on the capture element 103 first, and the adhesive medium 4 can be aligned with the first semiconductor epitaxial layer 31 by using the alignment bonding technique. The adhesive medium 4 is bonded to the first semiconductor epitaxial stack 31 in a warm and pressurized manner.

接續如第6H圖所示,當支撐結構5的材質為金屬材料,例如鈦(Ti)、鋁(Al)、鈦鎢(TiW)、銀(Ag)等,或者含矽的材料,例如氧化矽(SiOx)、氮 化矽(SiNx)或者多晶矽(poly-Si)等材料,可使用濕蝕刻或者蒸氣蝕刻的方式,移除支撐結構5,再分別施以反方向的力量於擷取元件103及黏結基板101,使得第一半導體磊晶疊層31與犧牲層201分離,本實施例中,濕蝕刻使用的蝕刻液包含氫氟酸,蒸氣蝕刻使用的化學材料包含氟化氫(HF)蒸氣。若支撐結構5的材質為紫外光(UV)解離材料,像是丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)等,使用紫外光(UV)照射支撐結構5可使支撐結構5與黏著結構2之間的黏著力降低或消失,再分別施以反方向的力量於擷取元件103及黏結基板101,使得第一半導體磊晶疊層31與支撐結構5分離;若支撐結構5的材質為熱塑性塑膠,像是尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)等,加熱支撐結構5可使支撐結構5與黏著結構2之間的黏著力降低或消失,再分別施以反方向的力量於擷取元件103及黏結基板101,使得第一半導體磊晶疊層31與支撐結構5分離。 Continuing as shown in Figure 6H, when the material of the support structure 5 is a metal material, such as titanium (Ti), aluminum (Al), titanium tungsten (TiW), silver (Ag), etc., or a material containing silicon, such as silicon oxide (SiOx), nitrogen Silicon (SiNx) or polysilicon (poly-Si) and other materials can use wet etching or vapor etching to remove the support structure 5, and then apply force in the opposite direction to the extraction element 103 and the bonding substrate 101 respectively, so that the The first semiconductor epitaxial stack 31 is separated from the sacrificial layer 201. In this embodiment, the etchant used for wet etching includes hydrofluoric acid, and the chemical material used for vapor etching includes hydrogen fluoride (HF) vapor. If the material of the support structure 5 is an ultraviolet (UV) dissociative material, such as acrylic acid, unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane) , vinyl ether, etc., using ultraviolet light (UV) to irradiate the support structure 5 can reduce or disappear the adhesive force between the support structure 5 and the adhesive structure 2, and then apply the force in the opposite direction to the extraction element 103 respectively. and bonding the substrate 101, so that the first semiconductor epitaxial stack 31 is separated from the support structure 5; if the support structure 5 is made of thermoplastic, such as nylon (Nylon), polypropylene (PP), polybutylene terephthalate Alcohol ester (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS), polyvinyl chloride (PVC), etc., heating the support structure 5 can make the support structure 5 The adhesive force between the adhesive structure 2 and the adhesive structure 2 is reduced or disappeared, and the force in the opposite direction is applied to the extraction element 103 and the adhesive substrate 101 respectively, so that the first semiconductor epitaxial stack 31 is separated from the support structure 5 .

在另一實施例中,如前述擷取元件103包含一軟性基板1032及一支撐結構1031,當第一半導體磊晶疊層31與犧牲層201分離後,接續如第11B圖所示,可將軟性基板1032與支撐結構1031分離,進一步製作成軟性顯示器。 In another embodiment, as the aforementioned capture element 103 includes a flexible substrate 1032 and a support structure 1031 , after the first semiconductor epitaxial stack 31 is separated from the sacrificial layer 201 , as shown in FIG. 11B , the The flexible substrate 1032 is separated from the support structure 1031, and is further fabricated into a flexible display.

第七實施例 Seventh Embodiment

第7A圖至第7F圖係分別為依本發明第七實施例之製程方法於各步驟之對應結構示意圖。本實施例與前述第二實施例的差異在於黏結基板101具有複數個孔洞120對應每一個第一半導體磊晶疊層31,使第一半導體磊晶疊層31與黏結基板101之間的黏著力比第二實施例中第一半導體磊晶疊層31與黏結基板101之間的黏著力還低,以增加使用機械力分離第一半導體磊晶疊層31與黏結基板101的成功機率;或者,利用濕蝕刻或蒸氣蝕刻去除犧牲層201時,蝕刻液 包含氫氟酸或者蒸氣蝕刻使用的化學材料包含氟化氫(HF)蒸氣,可經由複數個孔洞120蝕刻犧牲層201,以減少蝕刻所需的時間。 FIGS. 7A to 7F are schematic diagrams of corresponding structures of each step of the manufacturing method according to the seventh embodiment of the present invention, respectively. The difference between this embodiment and the aforementioned second embodiment is that the bonding substrate 101 has a plurality of holes 120 corresponding to each of the first semiconductor epitaxial stacks 31 , so that the adhesive force between the first semiconductor epitaxial stack 31 and the bonding substrate 101 is improved. The adhesive force between the first semiconductor epitaxial stack 31 and the bonding substrate 101 is lower than that of the second embodiment, so as to increase the success probability of separating the first semiconductor epitaxial stack 31 and the bonding substrate 101 by mechanical force; or, When removing the sacrificial layer 201 by wet etching or vapor etching, the etching solution The chemical material used in the vapor etching including hydrofluoric acid includes hydrogen fluoride (HF) vapor, and the sacrificial layer 201 can be etched through the plurality of holes 120 to reduce the time required for the etching.

第八實施例 Eighth Embodiment

第8A圖至第8F圖係分別為依本發明第八實施例之製程方法於各步驟之對應結構示意圖。本實施例與前述第七實施例的差異在黏著結構2不包含犧牲層,於黏結基板101具有複數個孔洞120對應每一個第一半導體磊晶疊層31,使第一半導體磊晶疊層31與黏結基板101之間的黏著力比第二半導體磊晶疊層32與黏結基板101之間的黏著力還低,使用機械力即可分離第一半導體磊晶疊層31與黏結基板101。 FIG. 8A to FIG. 8F are schematic diagrams of corresponding structures in each step of the manufacturing method according to the eighth embodiment of the present invention, respectively. The difference between this embodiment and the aforementioned seventh embodiment is that the adhesive structure 2 does not include a sacrificial layer, and the adhesive substrate 101 has a plurality of holes 120 corresponding to each of the first semiconductor epitaxial stacks 31 , so that the first semiconductor epitaxial stacks 31 The adhesive force with the bonding substrate 101 is lower than the adhesive force between the second semiconductor epitaxial stack 32 and the bonding substrate 101 , and the first semiconductor epitaxial stack 31 and the bonding substrate 101 can be separated by mechanical force.

第九實施例 Ninth Embodiment

第9A圖至第9I圖係分別為依本發明第九實施例之製程方法於各步驟之對應結構示意圖。參閱第9A圖,提供一成長基板102具有一表面1021用以後續成長半導體疊層,構成成長基板102的材料包含但不限於鍺(Ge)、砷化鎵(GaAs)、磷化銦(InP)、磷化鎵(GaP)、藍寶石(sapphire)、碳化矽(SiC)、矽(Si)、氧化二鋁鋰(LiAlO2)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)之一種或其組合。在成長基板102的表面1021上形成一圖形化的犧牲層601,犧牲層601的材料包含半導體材料,例如砷化鋁(AlAs)或氮化鋁(AlN),或者氧化物,例如氧化矽(SiOx),其中,若圖形化的犧牲層601的材料為砷化鋁(AlAs)或氮化鋁(AlN),形成的方式包含以有機金屬化學氣相沉積(MOCVD)的方法成長後,再以圖形化蝕刻的方式形成;若圖形化的犧牲層601的材料為氧化矽(SiOx),形成的方式包含以物理氣相沈積法(PVD)或化學氣相沈積法(CVD)的方式形成在成長基板102上,再施以圖形化蝕刻的方式形成。 9A to 9I are schematic diagrams of corresponding structures in each step of the manufacturing method according to the ninth embodiment of the present invention, respectively. Referring to FIG. 9A, a growth substrate 102 is provided with a surface 1021 for subsequent growth of semiconductor stacks. The materials constituting the growth substrate 102 include but are not limited to germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). , gallium phosphide (GaP), sapphire (sapphire), silicon carbide (SiC), silicon (Si), lithium aluminum oxide (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN) ) or a combination thereof. A patterned sacrificial layer 601 is formed on the surface 1021 of the growth substrate 102. The material of the sacrificial layer 601 includes semiconductor materials, such as aluminum arsenide (AlAs) or aluminum nitride (AlN), or oxides, such as silicon oxide (SiOx). ), wherein, if the material of the patterned sacrificial layer 601 is aluminum arsenide (AlAs) or aluminum nitride (AlN), the formation method includes growing by metal organic chemical vapor deposition (MOCVD), and then patterning If the material of the patterned sacrificial layer 601 is silicon oxide (SiOx), the formation method includes physical vapor deposition (PVD) or chemical vapor deposition (CVD) on the growth substrate. On 102, patterned etching is applied to form.

接續如第9B圖所示,在成長基板102的表面1021上形成一半導體層304並覆蓋圖形化的犧牲層601,其中半導體層304的材料有別於犧牲層601。 半導體層304可包含一過渡層(未顯示)或一窗口層(未顯示)。所述之過渡層可當作一緩衝層介於成長基板102及窗口層之間,或介於成長基板102及後續形成的半導體磊晶疊層3。在發光二極體的結構中,所述之過渡層係為了減少二層材料間的晶格不匹配。另一方面,所述之過渡層可以為單層、多層、二種材料的結合或二分開的結構,其中所述之過渡層的材料可為有機金屬、無機金屬或半導體中的任一種。所述之過渡層也可作為反射層、熱傳導層、電傳導層、歐姆接觸層、抗形變層、應力釋放層、應力調整層、接合層、波長轉換層或固定結構等。所述之窗口層係為一厚度較大的半導體層,可提升半導體磊晶疊層3的出光效率,以及增加電流橫向散佈的效果,其材料係包含至少一元素選自於鋁(Al)、鎵(Ga)、銦(In)、砷(As)、磷(P)及氮(N)所構成之群組,或為其組合,例如為GaN或AlGaInP之半導體化合物。 Continuing as shown in FIG. 9B , a semiconductor layer 304 is formed on the surface 1021 of the growth substrate 102 and covers the patterned sacrificial layer 601 , wherein the material of the semiconductor layer 304 is different from that of the sacrificial layer 601 . The semiconductor layer 304 may include a transition layer (not shown) or a window layer (not shown). The transition layer can be used as a buffer layer between the growth substrate 102 and the window layer, or between the growth substrate 102 and the semiconductor epitaxial stack 3 formed subsequently. In the structure of the light emitting diode, the transition layer is used to reduce the lattice mismatch between the two layers of materials. On the other hand, the transition layer can be a single layer, a multi-layer, a combination of two materials or a two-separate structure, wherein the material of the transition layer can be any one of organic metals, inorganic metals or semiconductors. The transition layer can also be used as a reflective layer, a thermal conduction layer, an electrical conduction layer, an ohmic contact layer, an anti-deformation layer, a stress release layer, a stress adjustment layer, a bonding layer, a wavelength conversion layer, or a fixed structure. The window layer is a semiconductor layer with a larger thickness, which can improve the light extraction efficiency of the semiconductor epitaxial stack 3 and increase the effect of lateral current distribution. The material of the window layer includes at least one element selected from aluminum (Al), A group consisting of gallium (Ga), indium (In), arsenic (As), phosphorus (P) and nitrogen (N), or a combination thereof, such as a semiconductor compound of GaN or AlGaInP.

接續如第9C圖所示,在半導體層304上繼續形成半導體磊晶疊層3,其中,半導體磊晶疊層3包括至少一第一半導體層301具有第一導電型態,一轉換單元302以及一第二半導體層303具有第二導電型態,依序形成於成長基板102之上。第一半導體層301和第二半導體層303可為兩個單層結構或兩個多層結構(多層結構係指兩層或兩層以上)。第一半導體層301和第二半導體層303具有不同的導電型態、電性、極性或依摻雜的元素以提供電子或電洞。當第一半導體層301為p型半導體,第二半導體層303可為相異電性的n型半導體,反之,當第一半導體層301為n型半導體,第二半導體層303可為相異電性的p型半導體。轉換單元302形成在第一半導體層301和第二半導體層303之間,轉換單元302係將光能和電能相互轉換或導致轉換。半導體磊晶疊層3可進一步加工應用於一半導體元件、設備、產品、電路,以進行或導致光能和電能相互轉換。具體而言,半導體磊晶疊層3可進一步加工成為一發光二極體(LED)、一雷射二極體(LD)、一太陽能電池或一液晶顯示器其中之一。以發光二極體為例,可以藉由改變半 導體磊晶疊層3裡的其中一層或多層的物理及化學組成,調整發出的光波長。常用的材料為磷化鋁鎵銦(aluminum gallium indium phosphide,AlGaInP)系列、氮化鋁鎵銦(aluminum gallium indium nitride,AlGaInN)系列、氧化鋅系列(zinc oxide,ZnO)。轉換單元302可為單異質結構(single heterostructure,SH),雙異質結構(double heterostructure,DH),雙側雙異質結(double-side double heterostructure,DDH),多層量子井(multi-quantum well,MWQ)。具體來說,轉換單元302可為中性、p型或n型電性的半導體。施以電流通過半導體磊晶疊層3時,轉換單元302會發光。當轉換單元302以磷化鋁銦鎵(AlGaInP)為基礎的材料時,會發出紅、橙、黃光之琥珀色系的光;當以氮化鋁鎵銦(AlGaInN)為基礎的材料時,會發出藍或綠光。 Next, as shown in FIG. 9C, the semiconductor epitaxial stack 3 is further formed on the semiconductor layer 304, wherein the semiconductor epitaxial stack 3 includes at least a first semiconductor layer 301 having a first conductivity type, a conversion unit 302 and A second semiconductor layer 303 having a second conductivity type is sequentially formed on the growth substrate 102 . The first semiconductor layer 301 and the second semiconductor layer 303 may be two single-layer structures or two multi-layer structures (a multi-layer structure refers to two or more layers). The first semiconductor layer 301 and the second semiconductor layer 303 have different conductivity types, electrical properties, polarities or elements depending on doping to provide electrons or holes. When the first semiconductor layer 301 is a p-type semiconductor, the second semiconductor layer 303 can be an n-type semiconductor with different electrical properties. On the contrary, when the first semiconductor layer 301 is an n-type semiconductor, the second semiconductor layer 303 can be a different electrical conductivity. a p-type semiconductor. The conversion unit 302 is formed between the first semiconductor layer 301 and the second semiconductor layer 303, and the conversion unit 302 converts light energy and electric energy into each other or causes conversion. The semiconductor epitaxial stack 3 can be further processed and applied to a semiconductor device, device, product, or circuit to perform or cause the mutual conversion of light energy and electrical energy. Specifically, the semiconductor epitaxial stack 3 can be further processed into one of a light emitting diode (LED), a laser diode (LD), a solar cell or a liquid crystal display. Taking light-emitting diodes as an example, it can be changed by changing the half The physical and chemical composition of one or more layers in the conductor epitaxial stack 3 adjusts the wavelength of the emitted light. Commonly used materials are aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide series (zinc oxide, ZnO). The conversion unit 302 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MWQ) ). Specifically, the conversion unit 302 can be a neutral, p-type or n-type semiconductor. When a current is applied through the semiconductor epitaxial stack 3, the conversion unit 302 emits light. When the conversion unit 302 is based on the material of aluminum indium gallium phosphide (AlGaInP), it will emit amber light of red, orange and yellow; when it is based on the material of aluminum gallium indium nitride (AlGaInN), it will emit light blue or green light.

接續如第9D圖所示,在半導體磊晶疊層3之表面3011上形成一圖形化的黏著介質4對應圖形化的犧牲層601,其中形成圖形化的黏著介質4的方式包含先形成一整層的黏著介質4在表面3011上,接著利用黃光微影製程或者圖形化蝕刻的方式,形成圖形化的黏著介質4,黃光微影製程及圖形化蝕刻係為一般習知的半導體製程。黏著介質4的材料包含有機材料,例如丙烯酸(Acrylic acid)、不飽和聚酯環氧樹脂(Unsaturated polyester)、環氧樹脂(Epoxy)、氧雜環丁烷(Oxetane)、乙烯醚(Vinyl ether)、尼龍(Nylon)、聚丙烯(PP)、聚對苯二甲酸丁二醇酯(PBT)、聚苯醚(PPO)、聚碳酸酯(PC)、丙烯腈-丁二烯-苯乙烯(ABS)、聚氯乙烯(PVC)、苯并環丁烯(BCB)等;或者無機材料,例如金屬包含鈦(Ti)、金(Au)、鈹(Be)、鎢(W)、鋁(Al)、鍺(Ge)、銅(Cu)或其組合,氧化物包含銦錫氧化物(ITO)、鎘錫氧化物(CTO)、銻氧化錫、氧化銦鋅、氧化鋅鋁、及鋅錫氧化物、氧化鋅(ZnO)、氧化矽(SiOx),或者氮化物包含氮化矽(SiNx)等。 Continuing as shown in FIG. 9D, a patterned adhesive medium 4 is formed on the surface 3011 of the semiconductor epitaxial stack 3 corresponding to the patterned sacrificial layer 601, wherein the method of forming the patterned adhesive medium 4 includes first forming an integral The adhesive medium 4 of the layer is on the surface 3011, and then a patterned adhesive medium 4 is formed by a yellow light lithography process or a patterned etching method. The yellow light lithography process and the patterned etching process are commonly known semiconductor processes. The material of the adhesive medium 4 includes organic materials, such as acrylic acid, unsaturated polyester epoxy resin (Unsaturated polyester), epoxy resin (Epoxy), oxetane (Oxetane), vinyl ether (Vinyl ether) , nylon (Nylon), polypropylene (PP), polybutylene terephthalate (PBT), polyphenylene ether (PPO), polycarbonate (PC), acrylonitrile-butadiene-styrene (ABS) ), polyvinyl chloride (PVC), benzocyclobutene (BCB), etc.; or inorganic materials, such as metals including titanium (Ti), gold (Au), beryllium (Be), tungsten (W), aluminum (Al) , germanium (Ge), copper (Cu) or combinations thereof, oxides including indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide , zinc oxide (ZnO), silicon oxide (SiOx), or nitrides including silicon nitride (SiNx) and the like.

接續如第9E圖所示,圖形化半導體磊晶疊層3及半導體層304並露出成長基板102的表面1021以形成互相隔開的複數個半導體磊晶疊層,其中複數 個半導體磊晶疊層包含至少一個第一半導體磊晶疊層31及至少一個第二半導體磊晶疊層32,在每一個第一半導體磊晶疊層31上具有黏著介質4,而每一個第二半導體磊晶疊層32的表面3011上則無黏著介質4。圖形化半導體磊晶疊層3及黏著結構2的方法包含乾蝕刻或濕蝕刻,在本實施例中使用乾蝕刻製成使第一半導體磊晶疊層31及第二半導體磊晶疊層32之間的間隔寬度w盡量縮小,以避免蝕刻過多的半導體磊晶疊層3造成浪費,本實施例的間隔寬度w介於1μm及10μm,較佳的為5μm。在本實施例中,由於第一半導體磊晶疊層31與成長基板102之間具有犧牲層601,而第二半導體磊晶疊層32係直接成長在成長基板102上,因此控制半導體層304磊晶製程的參數條件,或利用犧牲層601材料與半導體層304材料性質的差異,例如犧牲層601的材料為氧化物,使半導體層304與犧牲層601之間的附著力小於半導體層304與成長基板102之間的附著力。 Continuing as shown in FIG. 9E, the semiconductor epitaxial stack 3 and the semiconductor layer 304 are patterned and the surface 1021 of the growth substrate 102 is exposed to form a plurality of semiconductor epitaxial stacks separated from each other, wherein a plurality of semiconductor epitaxial stacks are formed. Each of the semiconductor epitaxial stacks includes at least one first semiconductor epitaxial stack 31 and at least one second semiconductor epitaxial stack 32 , each of the first semiconductor epitaxial stacks 31 has an adhesive medium 4 , and each of the first semiconductor epitaxial stacks 31 is provided with an adhesive medium 4 . There is no adhesive medium 4 on the surface 3011 of the two semiconductor epitaxial stacks 32 . The method of patterning the semiconductor epitaxial stack 3 and the adhesive structure 2 includes dry etching or wet etching. In the present embodiment, dry etching is used to form the gap between the first semiconductor epitaxial stack 31 and the second semiconductor epitaxial stack 32. The interval width w between them is as small as possible to avoid waste caused by etching too much semiconductor epitaxial stack 3 . The interval width w in this embodiment is between 1 μm and 10 μm, preferably 5 μm. In this embodiment, since there is a sacrificial layer 601 between the first semiconductor epitaxial stack 31 and the growth substrate 102, and the second semiconductor epitaxial stack 32 is directly grown on the growth substrate 102, the control semiconductor layer 304 is epitaxial The parameter conditions of the crystal process, or the difference between the material properties of the sacrificial layer 601 and the semiconductor layer 304, for example, the material of the sacrificial layer 601 is oxide, so that the adhesion between the semiconductor layer 304 and the sacrificial layer 601 is smaller than that of the semiconductor layer 304 and the growth Adhesion between substrates 102 .

接續如第9F圖所示,所示提供一擷取元件103藉由加溫、加壓或者利用擷取元件103本身具有之黏性,與黏著介質4黏結。擷取元件103包含導電材料,例如導電基板或印刷電路板,其中導電基板的材料包含矽(Si)、砷化鎵(GaAs)、碳化矽(SiC)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)或金屬材料之一種或其組合;印刷電路板包含單面印刷電路板、雙面印刷電路板、多層印刷電路板或軟性電路板;或非導電材料,例如包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)、壓克力(Acryl)、氧化鋅(ZnO)、氮化鋁(AlN)、氧化二鋁鋰(LiAlO2)、陶瓷基板或發泡聚苯乙烯(EPS)膠帶等。 Continuing as shown in FIG. 9F , a capturing element 103 is provided to adhere to the adhesive medium 4 by heating, pressing or utilizing the viscosity of the capturing element 103 itself. The extraction element 103 includes a conductive material, such as a conductive substrate or a printed circuit board, wherein the material of the conductive substrate includes silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), zinc oxide (ZnO), gallium nitride ( GaN), Aluminum Nitride (AlN), or one or a combination of metallic materials; printed circuit boards including single-sided, double-sided, multilayer, or flexible circuit boards; or non-conductive materials such as those containing Sapphire (Sapphire), Diamond (Diamond), Glass (Glass), Quartz (Quartz), Acrylic (Acryl), Zinc Oxide (ZnO), Aluminum Nitride (AlN), Lithium Aluminum Oxide (LiAlO2), Ceramic Substrate Or expanded polystyrene (EPS) tape, etc.

在另一實施例中,如第11A圖所示,擷取元件103可進一步包含一軟性基板1032及一支撐結構1031,其中軟性基板1032的材料包含聚酯樹脂(polyester resin;PET)、聚萘二甲酸乙二醇酯(polyethylene naphthalate;PEN)或聚醯亞胺(polyimide;PI),支撐結構的材料包含藍寶石(Sapphire)、鑽石(Diamond)、 玻璃(Glass)、石英(Quartz)或壓克力(Acryl)等硬質的基板,用以支撐軟性基板1032。 In another embodiment, as shown in FIG. 11A , the capturing element 103 may further include a flexible substrate 1032 and a supporting structure 1031 , wherein the material of the flexible substrate 1032 includes polyester resin (PET), polynaphthalene Polyethylene naphthalate (PEN) or polyimide (polyimide; PI), the material of the support structure includes sapphire (Sapphire), diamond (Diamond), A hard substrate such as glass (Glass), quartz (Quartz) or acrylic (Acryl) is used to support the flexible substrate 1032 .

在另一實施例中,可以先將圖形化的黏著介質4形成在擷取元件103上,使用對位黏合的技術,將黏著介質4與第一半導體磊晶疊層31對齊後,藉由加溫及加壓的方式,使黏著介質4與第一半導體磊晶疊層31黏結。 In another embodiment, the patterned adhesive medium 4 can be formed on the capture element 103 first, and the adhesive medium 4 can be aligned with the first semiconductor epitaxial layer 31 by using the alignment bonding technique. The adhesive medium 4 is bonded to the first semiconductor epitaxial stack 31 in a warm and pressurized manner.

接續如第9G圖所示,若犧牲層601為氧化物(SiOx)或者砷化鋁(AlAs),可使用濕蝕刻或者蒸氣蝕刻的方式,移除犧牲層601,再分別施以反方向的力量於擷取元件103及成長基板102,使得第一半導體磊晶疊層31與犧牲層601分離,本實施例中,濕蝕刻使用的蝕刻液包含氫氟酸,蒸氣蝕刻使用的化學材料包含氟化氫(HF)蒸氣。或者如第9H圖及第9I圖所示,當犧牲層601的材料為非半導體材料,例如氧化物(SiOx)時,控制半導體層304磊晶製程中橫向磊晶階段的溫度與壓力,例如控制溫度介於1000℃與1100℃之間及壓力介於400mbr與600mbar之間,在半導體層304與犧牲層601之間形成一孔隙602,使半導體層304與犧牲層601之間的接觸面積減少,且由於半導體層304與第二半導體層303的接觸面積大於與成長基板102的接觸面積,此時即可施以反方向的力量於擷取元件103及成長基板102,直接分離第一半導體磊晶疊層31與犧牲層601,使第一半導體磊晶疊層31從成長基板102分離。本實施例中,半導體層304包含一過渡層(未顯示)。所述之過渡層可當作一緩衝層介於成長基板102及後續形成的第二半導體層303之間,過渡層係為了減少二層材料間的晶格不匹配。另一方面,所述之過渡層可以為單層、多層、二種材料的結合或二分開的結構,其中所述之過渡層的材料可為有機金屬、無機金屬或半導體中的任一種。所述之過渡層也可作為反射層、熱傳導層、電傳導層、歐姆接觸層、抗形變層、應力釋放層、應力調整層、接合層、波長轉換層或固定結構等。在本實施例中,如第9H圖及第9I圖所示,第二半導體層303具有一第一下表面303s與半導體層304接觸,半導體層304 具有一第二下表面304s朝向成長基板102,第二下表面304s不平行於第一下表面303s,且第二下表面304s為一弧面。 Continuing as shown in Figure 9G, if the sacrificial layer 601 is oxide (SiOx) or aluminum arsenide (AlAs), wet etching or vapor etching can be used to remove the sacrificial layer 601, and then apply force in the opposite direction respectively. In the extraction element 103 and the growth substrate 102, the first semiconductor epitaxial stack 31 is separated from the sacrificial layer 601. In this embodiment, the etchant used for wet etching includes hydrofluoric acid, and the chemical material used for vapor etching includes hydrogen fluoride ( HF) vapor. Or as shown in FIGS. 9H and 9I, when the material of the sacrificial layer 601 is a non-semiconductor material, such as oxide (SiOx), the temperature and pressure of the lateral epitaxial stage in the epitaxial process of the semiconductor layer 304 are controlled, such as controlling When the temperature is between 1000°C and 1100°C and the pressure is between 400mbr and 600mbar, a void 602 is formed between the semiconductor layer 304 and the sacrificial layer 601, so that the contact area between the semiconductor layer 304 and the sacrificial layer 601 is reduced, And since the contact area between the semiconductor layer 304 and the second semiconductor layer 303 is larger than the contact area with the growth substrate 102 , a force in the opposite direction can be applied to the extraction element 103 and the growth substrate 102 to directly separate the first semiconductor epitaxy. The stack 31 and the sacrificial layer 601 separate the first semiconductor epitaxial stack 31 from the growth substrate 102 . In this embodiment, the semiconductor layer 304 includes a transition layer (not shown). The transition layer can be used as a buffer layer between the growth substrate 102 and the second semiconductor layer 303 formed subsequently. The transition layer is used to reduce the lattice mismatch between the two layers of materials. On the other hand, the transition layer can be a single layer, a multi-layer, a combination of two materials or a two-separate structure, wherein the material of the transition layer can be any one of organic metals, inorganic metals or semiconductors. The transition layer can also be used as a reflective layer, a thermal conduction layer, an electrical conduction layer, an ohmic contact layer, an anti-deformation layer, a stress release layer, a stress adjustment layer, a bonding layer, a wavelength conversion layer, or a fixed structure. In this embodiment, as shown in FIG. 9H and FIG. 9I, the second semiconductor layer 303 has a first lower surface 303s in contact with the semiconductor layer 304, and the semiconductor layer 304 There is a second lower surface 304s facing the growth substrate 102, the second lower surface 304s is not parallel to the first lower surface 303s, and the second lower surface 304s is an arc surface.

在另一實施例中,如第11A圖所示,擷取元件103可進一步包含一軟性基板1032及一支撐結構1031,其中軟性基板1032的材料包含聚酯樹脂(polyester resin;PET)、聚萘二甲酸乙二醇酯(polyethylene naphthalate;PEN)或聚醯亞胺(polyimide;PI),支撐結構的材料包含藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、石英(Quartz)或壓克力(Acryl)等硬質的基板,用以支撐軟性基板1032。 In another embodiment, as shown in FIG. 11A , the capturing element 103 may further include a flexible substrate 1032 and a supporting structure 1031 , wherein the material of the flexible substrate 1032 includes polyester resin (PET), polynaphthalene Polyethylene naphthalate (PEN) or polyimide (polyimide; PI), the material of the support structure includes sapphire (Sapphire), diamond (Diamond), glass (Glass), quartz (Quartz) or acrylic A hard substrate such as Acryl is used to support the flexible substrate 1032 .

第十實施例 Tenth Embodiment

第10A圖至第10C圖係分別為依本發明第十實施例之製程方法於各步驟之對應結構示意圖。如第10A圖至第10C圖所示,第十實施例與前述第九實施例差異在於黏著介質4位於第二半導體磊晶疊層32上,而第一半導體磊晶疊層31露出表面3011。如第10C圖所示,當半導體層304的材料為氮化鎵(GaN),犧牲層601的材料為氮化鋁(AlN),且成長基板102為透明基板時,可使用一雷射光7從成長基板102的另一表面1022射入用以照射半導體層304及犧牲層601,其中雷射光7的能量大於氮化鎵(GaN)的能隙且小於氮化鋁(AlN)的能隙,用以分離每一個第二半導體磊晶疊層32中的半導體層304與成長基板102,接著再施以反方向的力量於擷取元件103及成長基板102,分離第二半導體磊晶疊層32與成長基板102。 FIG. 10A to FIG. 10C are schematic diagrams of corresponding structures in each step of the manufacturing method according to the tenth embodiment of the present invention, respectively. As shown in FIGS. 10A to 10C , the difference between the tenth embodiment and the ninth embodiment is that the adhesive medium 4 is located on the second semiconductor epitaxial stack 32 , while the surface 3011 of the first semiconductor epitaxial stack 31 is exposed. As shown in FIG. 10C, when the material of the semiconductor layer 304 is gallium nitride (GaN), the material of the sacrificial layer 601 is aluminum nitride (AlN), and the growth substrate 102 is a transparent substrate, a laser beam 7 can be used to The other surface 1022 of the growth substrate 102 is incident for irradiating the semiconductor layer 304 and the sacrificial layer 601, wherein the energy of the laser light 7 is greater than the energy gap of gallium nitride (GaN) and smaller than the energy gap of aluminum nitride (AlN), using To separate the semiconductor layer 304 and the growth substrate 102 in each of the second semiconductor epitaxial stacks 32, and then apply a force in the opposite direction to the extraction element 103 and the growth substrate 102 to separate the second semiconductor epitaxial stack 32 from the growth substrate 102. Growth substrate 102 .

101:黏結基板 101: Bonding the substrate

103:擷取元件 103: Capture Components

201:犧牲層 201: Sacrificial Layer

202:黏結層 202: Bonding layer

31:第一半導體磊晶疊層 31: The first semiconductor epitaxial stack

32:第二半導體磊晶疊層 32: Second semiconductor epitaxial stack

4:黏著介質 4: Adhesive medium

Claims (9)

一半導體元件,包含:一基板;一半導體磊晶疊層位於該基板上,具有一第一厚度,包含:一第一半導體層;一第二半導體層,與該第一半導體層電性相異,且具有一第一下表面;及一轉換單元,位於該第一半導體層與該第二半導體層之間;以及一過渡層,位於該半導體磊晶疊層之下且與該基板接觸;其中,該過渡層與該第二半導體層的接觸面積大於與該基板的接觸面積。 A semiconductor device, comprising: a substrate; a semiconductor epitaxial stack located on the substrate with a first thickness, including: a first semiconductor layer; a second semiconductor layer, electrically different from the first semiconductor layer , and has a first lower surface; and a conversion unit located between the first semiconductor layer and the second semiconductor layer; and a transition layer located under the semiconductor epitaxial stack and in contact with the substrate; wherein , the contact area of the transition layer with the second semiconductor layer is larger than the contact area with the substrate. 如請求項1所述的半導體元件,其中,該過渡層直接接觸該第二半導體層。 The semiconductor element of claim 1, wherein the transition layer directly contacts the second semiconductor layer. 如請求項1所述的半導體元件,其中,該過渡層的材料包含接合材料。 The semiconductor element according to claim 1, wherein the material of the transition layer contains a bonding material. 如請求項1所述的半導體元件,其中,該過渡層的材料包含半導體材料。 The semiconductor element according to claim 1, wherein the material of the transition layer contains a semiconductor material. 如請求項1所述的半導體元件,其中,該過渡層具有一第二下表面朝向該基板,不平行於該第一下表面。 The semiconductor device of claim 1, wherein the transition layer has a second lower surface facing the substrate and not parallel to the first lower surface. 如請求項1所述的半導體元件,其中,該半導體元件不包含成長基板。 The semiconductor element according to claim 1, wherein the semiconductor element does not include a growth substrate. 如請求項1所述的半導體元件,其中,該過渡層具有一不均勻的厚度。 The semiconductor device of claim 1, wherein the transition layer has a non-uniform thickness. 如請求項1所述的半導體元件,更包含一孔隙位於該過渡層與該基板之間。 The semiconductor device of claim 1, further comprising a void located between the transition layer and the substrate. 如請求項5所述的半導體元件,其中,該第二下表面包含一弧面。 The semiconductor device of claim 5, wherein the second lower surface includes an arc surface.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
TW200739759A (en) * 2006-03-10 2007-10-16 Freescale Semiconductor Inc Semiconductor device packaging
US20100283074A1 (en) * 2007-10-08 2010-11-11 Kelley Tommie W Light emitting diode with bonded semiconductor wavelength converter
TW201232811A (en) * 2010-11-18 2012-08-01 3M Innovative Properties Co Light emitting diode component comprising polysilazane bonding layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200739759A (en) * 2006-03-10 2007-10-16 Freescale Semiconductor Inc Semiconductor device packaging
US20100283074A1 (en) * 2007-10-08 2010-11-11 Kelley Tommie W Light emitting diode with bonded semiconductor wavelength converter
TW201232811A (en) * 2010-11-18 2012-08-01 3M Innovative Properties Co Light emitting diode component comprising polysilazane bonding layer

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