TWI745351B - Method for decomposing semiconductor layout pattern - Google Patents

Abstract

A method for a semiconductor layout pattern decomposition includes following steps. (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition to the semiconductor layout pattern to obtain a grille pattern and a non-grille pattern; (c) recognizing a plurality of intersection regions in the grille pattern and alternately marking the intersection regions with a first region and a second region; (4) performing a second separation/decomposition to the grille pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns perpendicular to each other, the first sub-patterns including the first regions, the second sub-patterns including the second regions; and (e) introducing a plurality of first assistance features on the first regions in the first sub-patterns and on the second regions on the second regions in the second sub-patterns, respectively. The step (a) to the step (e) are implemented using a computer.

Description

Semiconductor layout pattern dividing method

The present invention relates to a method for dividing a semiconductor layout pattern, in particular to a method for dividing a semiconductor layout pattern for multiple patterning technology.

In the manufacturing process of semiconductor integrated circuits, the manufacturing of the microstructure of the integrated circuit requires the use of suitable substrates or material layers such as semiconductor substrate/film layer, dielectric material layer, or metal material layer. Processes such as shadowing and etching form tiny patterns with precise dimensions. To achieve this goal, in traditional semiconductor technology, a mask layer is formed on the target material layer, so that these tiny patterns are formed/defined in the mask layer, and then these patterns are transferred to Target film. Generally speaking, the mask layer may include a patterned photoresist layer formed by a lithography process, and/or a patterned mask layer formed by using the patterned photoresist layer. With the complexity of integrated circuits, the size of these tiny patterns continues to decrease, so the equipment used to generate characteristic patterns must meet the strict requirements of process resolution and overlay accuracy. At this point, resolution is regarded as a measure of the ability to pattern images of the smallest size under predetermined manufacturing conditions.

However, with the continuous advancement of semiconductor technology to 85 nanometers (nanometer, nm) Hereinafter, a single patterning method can no longer meet the resolution requirements or manufacturing process requirements for manufacturing micro-line-width patterns. Therefore, the semiconductor industry now adopts multiple patterning methods, such as double patterning processes, as a way to overcome the resolution limit of lithographic exposure devices. Generally speaking, in the multi-patterning process, the dense patterns (the size of individual patterns and/or the spacing between patterns are lower than the resolution limit of the lithography device) are first disassembled into different masks. Then the patterns on the masks are transferred to the photoresist layer/mask layer, so the patterns on different masks can be combined into the original target pattern.

It can be seen that the multi-patterning method is a precise and highly demanding process method for process control. Therefore, the use of the multi-patterning method inevitably increases the complexity of the process.

Therefore, one object of the present invention is to provide a method for dividing a semiconductor layout pattern, which can efficiently divide the layout pattern and form it on different photomasks, so that the subsequent multiple patterning process can be performed smoothly.

According to the scope of the patent application of the present invention, a method for dividing a semiconductor layout pattern is provided, which includes the following steps: (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition step on the semiconductor layout pattern To obtain a grille pattern and a non-grille pattern; (c) recognizing a plurality of intersection regions of the grid pattern, and alternating these intersecting regions (alternately) mark as the first area and the second area; (d) perform a first on the grid pattern Two division steps to obtain a plurality of first sub-patterns (sub-patterns) and a plurality of second sub-patterns, the first sub-patterns extend along a first direction and include the first regions, the second The sub-patterns extend along a second direction and include the second regions, and the first direction and the second direction are perpendicular to each other; and (e) the first regions and the first regions in the first sub-patterns and A first assistance feature is provided in the second regions in the second sub-patterns. In addition, the above steps (a) to (e) are performed in a computer device.

According to the scope of the patent application of the present invention, a method for dividing a semiconductor layout pattern is further provided, which includes the following steps: (a) receiving a semiconductor layout pattern; (b) performing a first dividing step on the semiconductor layout pattern to obtain a grid A grid pattern and a non-grid pattern; and (c) arranging a plurality of first auxiliary features in the non-grid pattern. In addition, the above steps (a) to (c) are performed in a computer device.

According to the semiconductor layout pattern segmentation method provided by the present invention, the steps of disassembling and adding auxiliary features according to different types of patterns: according to the disassembly of the grid pattern and the addition of auxiliary features, and the addition of auxiliary features to non-grid patterns Features and other steps can ensure that all patterns output to any single mask can be clearly imaged, and can be accurately and faithfully transferred to the target material film layer. Therefore, the semiconductor layout pattern dividing method provided by the present invention has the effect of improving the results of multiple patterning processes.

100: Semiconductor layout pattern division method

102~110: Step

200: Semiconductor layout pattern

202G: Grill pattern

204a: The first sub-pattern

204b: The second sub-pattern

206: The third sub-pattern

202N: non-grid pattern

210: Auxiliary Features

220: auxiliary features

230, 230’, 230”, 230''': the first mask

232, 232’, 232”, 232''': second mask

234: Third Mask

250: Patterned material layer

252, 252’: Grid pattern layer

254, 254’: Non-lattice gate pattern layer

0: first area

1: The second area

D1: First direction

D2: second direction

W: auxiliary feature width

W’: the width of the first sub-pattern, the width of the second sub-pattern

d: Auxiliary feature spacing

ds: The sum of the width of the first sub-pattern and the spacing between both sides, the sum of the width of the second sub-pattern and the spacing between both sides

Figure 1 is a preferred embodiment of a method for dividing a semiconductor layout pattern provided by the present invention The flow chart.

2 to 8 are schematic diagrams of the method for dividing the semiconductor layout pattern provided by the preferred embodiment.

Figure 9 is a schematic diagram of a variation of the above-mentioned preferred embodiment.

FIG. 10 to FIG. 11 are schematic diagrams of other preferred embodiments of the method for dividing a semiconductor layout pattern provided by the present invention.

FIG. 12 is a schematic diagram of a patterned film layer finally formed by the method of dividing the semiconductor layout pattern provided by the present invention.

Those familiar with the art should understand that a number of different embodiments are provided below to reveal different features of the present invention, but are not limited thereto. In addition, the figures disclosed below are simplified to express the features of the present invention more clearly, so the figures disclosed below do not show all elements of a specified element (or device). In addition, the diagrams disclosed below are idealized schematic diagrams according to the present invention, so the variations of these schematic diagrams, such as the differences caused by manufacturing technology and or allowable errors, are predictable. Therefore, the disclosure of the present invention should not be limited to the specific shape disclosed in the following drawings, and should include the deviation of the shape caused by the manufacturing technology.

In addition, those familiar with the art should understand that in the following description, when a component, such as a region, a layer, a part, etc., is referred to as being "on" another component, it means that component It is directly disposed on the other constituent element, or it may refer to or have other constituent elements in between. However, when a component is called straight and is formed on another component, it means that there is no more between the two components. Other constituent elements exist. In addition, when a component is "formed" on another component as disclosed in the present invention, the component can be grown (growth), deposited (deposition), etched (etch), attached (attach), connected ( connect), such as coupling and other methods, or other methods are prepared or manufactured on the component.

In addition, the terms used in the present invention, such as "bottom", "below", "above", "top", etc., are used to describe the relative positions of different components in the illustration. However, when the schema is turned upside down, the aforementioned "above" becomes "below". It can be seen that the relative description term used in the present invention can be determined according to the orientation of the element or device.

Please refer to FIG. 1 to FIG. 8. FIG. 1 is a flowchart of a preferred embodiment of the semiconductor layout pattern dividing method provided by the present invention, and FIG. 2 to FIG. 8 are the preferred embodiment. A schematic diagram of the provided semiconductor layout pattern dividing method. As shown in FIG. 1, the method 100 for dividing a semiconductor layout pattern provided by the present invention includes: Step 102: Receive a semiconductor layout pattern; please refer to FIG. 2 at the same time. As shown in Figure 2, the preferred embodiment first receives a semiconductor layout pattern 200. The semiconductor layout pattern 200 may include a circuit pattern to be formed in any layer of an integrated circuit, which may be a back-end process. The circuit pattern in the end-of-line (BEOL) process, such as the interconnect layer pattern, can also be the circuit pattern in the front-end-of-line (FEOL) process. In addition, the size and ratio of the semiconductor layout pattern 200 shown in FIG. 2 are simplified to facilitate the clear description of the content of this embodiment. It is not drawn based on the actual product ratio.

Next, the method 100 for dividing a semiconductor layout pattern provided by the present invention is performed: Step 104: Perform a first dividing step on the semiconductor layout pattern to obtain a grid pattern and a non-grid pattern; please also refer to section 3. picture. As shown in FIG. 3, next, the first dividing step is performed on the semiconductor layout pattern 200. In detail, the semiconductor layout pattern 200 is identified. When the feature pattern in the semiconductor layout pattern 200 includes both extending in a first direction D1 and extending in a second direction D2, and includes intersecting regions When it is characteristic, it is defined as a grid pattern 202G. And as shown in Figure 3, the first direction D1 and the second direction D2 are perpendicular to each other. In addition, the semiconductor layout pattern 200 only extends in a single direction, for example, only extends in the second direction D2, and the feature patterns parallel to each other arranged in the first direction D1 are defined as a non-grid pattern 202N. After the grid pattern 202G and the non-grid pattern 202N are defined according to the above conditions, the present invention directly divides the grid pattern 202G and the non-grid pattern 202N to perform the subsequent steps separately.

Next, the present invention performs the following steps respectively on the grid pattern 202G and the non-grid pattern 202N. First, please refer to step 106a: Step 106a: Identify a plurality of interlaced regions of the grid pattern, and alternate these interlaced regions Marked as the first area and the second area; Please also refer to Figure 4. As mentioned above, the grid pattern 202G includes a plurality of characteristic patterns extending along the first direction D1 and a plurality of extending along the second direction D2, which are interlaced with each other. Therefore, in the present invention, after the grid pattern 202G is divided, the staggered area included in the grid pattern 202G is identified, and as shown in FIG. 4, the staggered area is alternately marked as the first area "0" and the second area. Area "1". Therefore, in the present invention, a plurality of first regions "0" and a plurality of second regions "1" are marked in the grid pattern 202G, and any first region "0" is related to a second region "1". Adjacent and vice versa.

After marking the first area "0" and the second area "1", the present invention performs the following steps on the grid pattern 202G: Step 106b: Perform a second segmentation step on the grid pattern to obtain a plurality of first regions A sub-pattern and a plurality of second sub-patterns, the first sub-patterns extend along the first direction and include the first regions, and the second sub-patterns extend along the second direction and include the second regions ; Please also refer to Figure 5. Next, the present invention is to perform a second division step on the grid pattern 202G. As shown in FIG. 5, the second division step is to divide the grid pattern 202G into a plurality of first sub-patterns 204a and a plurality of second sub-patterns 204b. In this preferred embodiment, the first sub-pattern 204a and the second sub-pattern 204b may include the same width W', but it is not limited thereto. The first sub-patterns 204a extend along the first direction D1 and are arranged along the second direction D2. More importantly, the first sub-pattern 204a includes a plurality of first regions "0". The second sub-patterns 204b extend along the second direction D2 and are arranged along the first direction D1. More importantly, the second The sub-pattern 204b includes a plurality of second regions "1". In other words, the first sub-pattern 204a and the second sub-pattern 204b are perpendicular to each other, and the present invention assigns the first area "0" and the second area "1" to the first sub-pattern 204a and the first sub-pattern 204a and the second area respectively. The two sub-patterns 204b are as shown in Fig. 5.

After the second segmentation step, the present invention performs the following steps: Step 106c: setting an auxiliary in the first regions in the first sub-patterns and the second regions in the second sub-patterns, respectively Features; please also refer to Figure 6. Next, in the present invention, an auxiliary feature 210 is respectively provided in the first area "0" in the first sub-pattern 204a and the second area "1" in the second pattern 204b. It is worth noting that in the present preferred embodiment, the auxiliary features 210 arranged in the first sub-pattern 204a and the second sub-pattern 204b are void patterns. In other words, due to the arrangement of the auxiliary features 210 , A plurality of equidistant gaps are formed in the first sub-pattern 204a and the second sub-pattern 204b. It should be noted that the width W of the auxiliary feature 210 is smaller than the width W'of the first sub-pattern 204a and the width W'of the second sub-pattern 204b. In other words, the auxiliary feature 210 does not cut off the first sub-pattern 204a and the second sub-pattern 204b. As shown in Figure 6, the distance d between any two adjacent auxiliary features 210 in the first sub-pattern 204a is greater than the sum d of the width of a second sub-pattern 204b and the two distances on both sides of the second sub-pattern 204b. _S , similarly, the distance d between any two adjacent auxiliary features 210 in the second sub-pattern 204b is greater than the sum d _S of the width of a first sub-pattern 204a and the two distances on both sides of the first sub-pattern 204a.

Please refer to Figure 1 again. In addition to the above steps for the grid pattern 202G In addition to step 106a to step 106c, the present invention further includes the following steps: step 108: setting a plurality of auxiliary features in the non-grid pattern; please refer to FIG. 3 and FIG. 7 at the same time. As shown in FIG. 3, the non-grid pattern 202N includes a plurality of third sub-patterns 206, which are respectively arranged along the first direction D1 and extend along the second direction D2. In this preferred embodiment, step 108 may be performed while performing the above-mentioned steps 106a to 106c, so as to form a plurality of auxiliary features 220 in the non-grid pattern 202N, as shown in FIG. 7. It should be noted that the auxiliary features 220 extend along the first direction D1 and are arranged along the second direction D2. In other words, the extending direction of the auxiliary feature 220 is perpendicular to the third sub-pattern 206, and the arrangement direction of the auxiliary feature 220 is also perpendicular to the third sub-pattern 206. It is worth noting that the auxiliary features 220 arranged in the non-grid pattern 202N are solid patterns, and the auxiliary features 210 arranged in the first sub-pattern 204a and the second sub-pattern 204b are not space patterns.

It should also be noted that the above steps 102 to 106c and step 108 can all be performed in a computer device. After step 106c and/or step 108, the present invention further proceeds: step 110: output to the photomask, please refer to FIG. 8. After completing the division of the grid pattern 202G and the non-grid pattern 202N, the division of the grid pattern 202G and the setting of the auxiliary feature 210, and the setting of the auxiliary feature 220 in the non-grid pattern 202N, the preferred embodiment can further The first sub-pattern 204a, the auxiliary feature 210, the non-grid pattern 202N (including the third sub-pattern 206) and the auxiliary The feature 220 is output to a first photomask 230, and the second sub-pattern 204b and the auxiliary feature 210 are output to a second photomask 232, as shown in FIG. 8. Please also refer to Figure 9, which is a schematic diagram of a variation of the preferred embodiment. In this variation, the first sub-pattern 204a and the auxiliary feature 210 can be output to a first mask 230', and the non-grid pattern 202N (including the third sub-pattern 206) and the auxiliary feature 220, and the second The two sub-patterns 204b and auxiliary features 210 are output to a second mask 232'. In other words, the non-grid pattern 202N (including the third sub-pattern 206) and the auxiliary feature 220 can be output to the same mask as the first sub-pattern 204a and the auxiliary feature 210, or with the second sub-pattern 204b according to the process requirements. Output to the same mask as the auxiliary feature 210. In addition, in other embodiments of the present invention, step 108 is an optional step. In other words, any auxiliary features may not be provided in the non-grid pattern 202N. Therefore, in these embodiments, the present invention can output the first sub-pattern 204a, the auxiliary feature 210, and the third sub-pattern 206 of the non-grid pattern 202N to the first mask (not shown), and at the same time, the second sub-pattern (not shown) The sub-pattern 204b and the auxiliary feature 210 are output to a second mask.

Please also refer to FIG. 10, which is a schematic diagram of another preferred embodiment of the method for dividing a semiconductor layout pattern provided by the present invention. It should be noted that the steps and components in this preferred embodiment that are the same as those in the foregoing preferred embodiment are the same as those in the foregoing embodiment, so they will not be repeated here. The difference between this preferred embodiment and the previous preferred embodiments lies in the completion of the division of the grid pattern 202G and the non-grid pattern 202N, the division of the grid pattern 202G, the provision of auxiliary features 210, and the completion of the division of the grid pattern 202G and the non-grid pattern 202N. After the auxiliary feature 220 is provided in 202N, the present invention can further output the first sub-pattern 204a and auxiliary feature 210 to a first mask 230", and output the second sub-pattern 204b and auxiliary feature 210 to a second mask 232 ", simultaneously output the non-grid pattern 202N (including the third sub-pattern 206) and the auxiliary features 220 to a third mask 234, as shown in FIG. 10.

Please also refer to FIG. 11. FIG. 11 is a schematic diagram of another preferred embodiment of the semiconductor layout pattern dividing method provided by the present invention. It should be noted that the steps and components in this preferred embodiment that are the same as those in the foregoing preferred embodiment are the same as those in the foregoing embodiment, so they will not be repeated here. The difference between this preferred embodiment and the foregoing preferred embodiments is that in this embodiment, step 106a to step 106c are optional steps. In other words, the grid pattern 202G may not accept the second segmentation step, and any auxiliary features may not be provided in the grid pattern 202G. Therefore, in this preferred embodiment, the present invention can output the grid pattern 202G to a first mask 230"', while combining the non-grid pattern 202N (including the third sub-pattern 206) and the auxiliary feature 220 Output to a second mask 232''', as shown in Figure 11.

Please refer to Figure 12. After the above-mentioned photomask is obtained according to different embodiments of the present invention, multiple patterning processes can be performed to transfer the pattern contained in the above-mentioned photomask to a material layer. In some embodiments of the present invention, the material layer may be a metal layer. For example, according to the embodiment shown in Figure 8, Figure 9, and Figure 11, a dual patterning process can be used, such as a 2P2E method of developing-etching-developing-etching or developing-developing-etching. In the 2P1E method, the first sub-pattern 204a, the auxiliary feature 210, the non-grid pattern 202N (including the third sub-pattern 206) and the auxiliary feature 220 of the first mask are transferred to the material layer, and the first sub-pattern of the second mask is transferred The two sub-patterns 204b and the auxiliary features 220 are transferred to the material layer to form a patterned material layer 250, and the patterned material layer 250 includes the semiconductor layout pattern shown in FIG. Alternatively, according to the embodiment shown in FIG. 10, the first sub-pattern 204a of the first photomask 230' and the auxiliary feature 210, and the second sub-pattern 204b of the second photomask 232' can be combined by a multiple patterning process. The non-grid pattern 202N (including the third sub-pattern 206) and the auxiliary feature 220 of the auxiliary feature 210, the third mask 234, and the auxiliary feature 220 are transferred to a material layer to form a pattern The patterned material layer 250 and the patterned material layer 250 include the semiconductor layout pattern shown in FIG. 2. Therefore, the patterned material layer 250 itself may include a grid pattern layer 252 and a plurality of non-lattice pattern layers 254.

Please still refer to Figure 12. In other embodiments of the present invention, the material layer may also be a semiconductor layer or a dielectric layer. For example, the above-mentioned double patterning process or multiple patterning process can be used to transfer the sub-patterns and auxiliary features on the mask to the material layer according to the embodiments shown in Figs. 8-11 to form a The patterned material layer 250 ′, and the patterned material layer 250 ′ includes the semiconductor layout pattern shown in FIG. 2. More importantly, at this time, the semiconductor layout pattern included in the patterned material layer 250' is a trench pattern. After that, the required material, for example, a metal material or an insulating material, can be filled into the trench pattern, and a planarization process is performed as required, and a pattern complementary to the patterned material layer 250' is formed in the trench pattern . Therefore, a grid pattern layer 252' and a plurality of non-grid pattern layers 254' can be formed in the patterned material layer 250', and as described above, the grid pattern layer 252' and the non-grid pattern layer 254' It may contain metallic materials or insulating materials.

It is worth noting that in the double/multiple patterning process, the interlaced area of the first sub-pattern 204a and the second sub-pattern 204b becomes an overlapping area, and the interlaced area of the first sub-pattern 204a and the second sub-pattern 204b is arranged The auxiliary feature 210 of is a void pattern, and during the etching process, the auxiliary feature 210 of the void type can avoid the problem of over-etching in the interlaced/overlapped area. Therefore, the finally formed patterned material layer 250 can be the same as the desired semiconductor layout pattern 200. In addition, it should be noted that although the auxiliary feature 220 provided in the non-grid pattern 202N is a solid feature, the auxiliary feature 220 is set to prevent the third sub-pattern 206 from shrinking at the end of the line during lithography. shortening) Therefore, the size of the auxiliary feature 220 may not be transferred to the material layer in the end. For example, it may be a feature that cannot be etched during the lithography process, or even if the size is lower than the resolution limit of the mask output machine. Non-printable features that are transferred to the photomask. Therefore, it can be ensured that the finally obtained patterned material layer 250 is the same as the desired semiconductor layout pattern 200.

According to the semiconductor layout pattern segmentation method provided by the present invention, the steps of disassembling and adding auxiliary features according to different types of patterns: according to the disassembly of the grid pattern and the addition of auxiliary features, and the addition of auxiliary features to non-grid patterns Features and other steps can ensure that all patterns output to any single mask can be clearly imaged, and can be accurately and faithfully transferred to the target material film layer to form the required physical pattern or trench pattern. Therefore, the semiconductor layout pattern dividing method provided by the present invention has the effect of improving the results of multiple patterning processes.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Semiconductor layout pattern division method

102~110: Step

Claims (19)

A semiconductor layout pattern decomposition method includes the following steps: (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition step on the semiconductor layout pattern to obtain a grid ( grille pattern and a non-grille pattern; (c) recognize (recognizing) a plurality of intersection areas of the grille pattern, and alternately mark the intersection areas as the first Area and second area; (d) performing a second segmentation step on the grid pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns, the first sub-patterns are along A first direction extends and includes the first regions, the second sub-patterns extend along a second direction and include the second regions, and the first direction and the second direction are perpendicular to each other; and (e ) Respectively set a first auxiliary feature (assistance feature) in the first areas in the first sub-patterns and the second areas in the second sub-patterns, wherein the steps (a) to the Step (e) is performed in a computer device. According to the method for dividing a semiconductor layout pattern described in the first item of the patent application, the width of the first auxiliary features is smaller than the width of the first sub-patterns and the width of the second sub-patterns. According to the method for dividing a semiconductor layout pattern described in the first item of the scope of patent application, the width of the first sub-patterns is the same as the width of the second sub-patterns. According to the method for dividing a semiconductor layout pattern according to the first item of the patent application, the distance between any two adjacent first auxiliary features in the first sub-patterns is greater than the width of the second sub-pattern and the width of the second sub-pattern. The sum of the two spacings on both sides of the two sub-patterns. According to the method for dividing a semiconductor layout pattern according to the first item of the patent application, the distance between any two adjacent first auxiliary features in the second sub-patterns is greater than a width of the first sub-pattern and the first sub-pattern The sum of two spaces on both sides of a sub-pattern. According to the method for dividing a semiconductor layout pattern according to the first item of the scope of patent application, the non-grid pattern includes a plurality of third sub-patterns, which are respectively arranged along the first direction and extend along the second direction. The method for dividing the semiconductor layout pattern described in claim 6 further includes a step of arranging a plurality of second auxiliary features in the non-grid pattern, and the second auxiliary features extend along the first direction. For example, the semiconductor layout pattern dividing method described in the scope of the patent application further includes a step of outputting the first sub-patterns, the first auxiliary features, and the non-grid pattern to a first mask, and outputting the And so on the second sub-pattern and the first auxiliary features to a second mask. For example, the semiconductor layout pattern dividing method described in the scope of patent application further includes a step of: the first sub-patterns and the first auxiliary The features and the non-grid pattern and the second sub-patterns and the first auxiliary features of the second mask are transferred to a material layer to form a patterned material layer, and the patterned material layer includes the semiconductor layout pattern. For example, the semiconductor layout pattern dividing method described in the scope of the patent application further includes a step of outputting the first sub-patterns and the first auxiliary features to a first mask, and outputting the second sub-patterns and The first auxiliary features are sent to a second mask, and the non-grid pattern is output to a third mask. For example, the method for dividing a semiconductor layout pattern described in claim 10 further includes a step of: the first sub-patterns of the first mask, the first auxiliary features, and the second mask The second sub-pattern, the first auxiliary features, and the non-grid pattern of the third mask are transferred to a material layer to form a patterned material layer, and the patterned material layer includes the semiconductor layout pattern. A method for dividing a semiconductor layout pattern includes the following steps: (a) receiving a semiconductor layout pattern; (b) performing a first dividing step on the semiconductor layout pattern to obtain a grid pattern and a non-grid pattern, wherein The non-grid pattern includes a plurality of third sub-patterns respectively extending in a second direction and arranged in parallel along a first direction, the second direction and the first direction being perpendicular to each other; and (c) arranged in the non-grid pattern A plurality of first auxiliary features, wherein the plurality of first auxiliary features are adjacent to the ends of the third sub-patterns, and the plurality of first auxiliary features respectively extend along the first direction and are arranged in parallel along the second direction, The steps (a) to (c) are performed in a computer device. As described in item 12 of the scope of patent application, the method for dividing a semiconductor layout pattern further includes the following steps: (d) identifying a plurality of interlaced areas of the grid pattern, and alternately marking the interlaced areas as the first area and the first area Two regions; (e) performing a second division step on the grid pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns, the first sub-patterns extending along the first direction and including the The first area, the second sub-patterns extend along the second direction and include the second areas; and (f) the first areas and the second areas in the first sub-patterns A second auxiliary feature is arranged in the second areas in the sub-pattern, wherein the step (d) to the step (f) are performed in a computer device. For example, in the method for dividing a semiconductor layout pattern described in the scope of patent application, the width of the second auxiliary features is smaller than the width of the first sub-patterns and the width of the second sub-patterns. According to the method for dividing a semiconductor layout pattern according to claim 13, wherein the distance between any two adjacent first auxiliary features in the first sub-pattern is greater than the width of the second sub-pattern and the width of the second sub-pattern The sum of the two spacings on both sides of the two sub-patterns. According to the method for dividing the semiconductor layout pattern described in the scope of patent application, the distance between any two adjacent first auxiliary features in the second sub-patterns is large The sum of the width of the first sub-pattern and the two spacings on both sides of the first sub-pattern. For example, the method for dividing the semiconductor layout pattern described in the scope of the patent application includes a step of outputting the first sub-patterns, the second auxiliary features, the non-grid pattern, and the first auxiliary features to a second A mask, and output the second sub-patterns and the second auxiliary features to a second mask. For example, the method for dividing a semiconductor layout pattern described in the scope of patent application includes a step of outputting the first sub-patterns and the second auxiliary features to a first mask, and outputting the second sub-patterns and The second auxiliary features are output to a second mask, and the non-grid pattern and the first auxiliary features are output to a third mask. For example, the method for dividing a semiconductor layout pattern described in the scope of patent application 12 further includes a step of outputting the grid pattern to a first mask, and outputting the non-grid pattern and the first auxiliary features to a first mask. Two masks.

Images