JP2006276491A - Mask pattern correcting method and photomask manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pattern correcting method with which a mask pattern transferred onto a stepped pattern can be corrected in a short time with high precision. <P>SOLUTION: A layer extraction section extracts a design mask pattern of an object layer and the level difference pattern to be formed below the object layer from a correction information database and an intersection detection section detects a plurality of intersections of a transfer image of the design mask pattern and the stepped pattern; and a distance calculation section calculates intersection distances between the plurality of intersections, a region setting section sets a first processing region including the plurality of intersections at the respective intersections on an arrangement surface of the design mask pattern based upon the intersection distances, and a shape calculation section calculates a first transfer image of the design mask pattern to be transferred in the first processing region based upon the level difference pattern. Then a correction section corrects the design mask pattern based upon the first transfer image. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a mask pattern correction method for a photomask used in photolithography, and a photomask manufacturing method.

  Recent progress in semiconductor manufacturing technology is very remarkable, and semiconductor devices such as large-scale integrated circuits (LSIs) having a pattern with a minimum processing dimension of 0.09 μm are mass-produced. Miniaturization of LSI patterns has been realized by dramatic progress in fine pattern formation technologies such as mask process technology, optical lithography technology, and etching technology. In a generation in which the pattern size of a semiconductor device is sufficiently large, a photomask having a mask pattern faithful to the design pattern is produced using the planar shape of the LSI pattern to be formed on the wafer as it is as the design pattern. By transferring the mask pattern of the photomask onto the wafer by the projection optical system and processing the base layer on the wafer, a pattern almost as designed can be formed on the wafer. However, as the LSI pattern becomes finer, it is difficult to faithfully form the pattern in each process. Therefore, there is a problem that the final finished dimension of the LSI pattern on the wafer does not match the design pattern. In order to solve such a problem, in consideration of a conversion difference in each process, means for creating mask pattern data having a shape different from the design pattern so that the final finished dimension is equal to the design pattern dimension (hereinafter, referred to as the following) This is called mask data processing).

    For mask data processing, mask data preparation (MDP) processing for changing a mask pattern by using graphic operation processing, design rule checker (DRC), or the like, and optical proximity effect correction for correcting optical proximity effect (OPE) ( OPC) processing and the like. By performing mask data processing, the mask pattern is appropriately corrected so as to have a desired final finished size. As the pattern is miniaturized, the process coefficient k1 value in photolithography decreases. As a result, since the OPE tends to increase, the load of the OPC process is very large.

  Until now, rule-based correction methods and model-based correction methods have been proposed as OPC techniques. In the rule-based correction method, the correction amount corresponding to the mask pattern arrangement is determined based on the rules tabulated in advance. The rule-based correction has a simple correction procedure, but it is difficult to make all the actual circuit pattern variations into a rule table, and sufficient correction accuracy cannot be obtained. In the model-based correction method, a mask pattern is corrected by predicting a shape transferred onto a wafer based on mask pattern information and wafer process conditions. For this reason, the model-based correction requires a longer time than the rule-based correction method, but can be corrected with high accuracy.

  In order to achieve high accuracy of OPC processing, model-based OPC, which is equipped with a light intensity simulator capable of accurately predicting OPE and can calculate an appropriate correction value for each mask pattern, has become mainstream.

  However, model-based OPC cannot be corrected completely. In model-based OPC, the finished shape is determined in consideration of only the layer where the target pattern exists. When a pattern is actually formed on a wafer, the surface of the processed wafer is not flat but has a step. That is, the finished shape is affected by the level difference on the processed wafer. The current model-based OPC does not consider the influence of the step on the processed wafer on the finished shape. For this reason, there is a limit to high accuracy only with the current model-based OPC.

  In order to obtain the finished shape of the pattern in consideration of the effect of the step on the processing wafer, it is necessary to correct the mask pattern by performing a lithography simulation in consideration of the three-dimensional structure. However, the lithography simulation considering the three-dimensional structure takes a long time and is difficult to apply to actual manufacturing of a semiconductor device.

There is a technique in which an overlapping portion between a target pattern and a step pattern formed on a base layer is extracted, and a mask pattern is corrected only for the overlapping portion (see, for example, Patent Document 1). By limiting the correction target pattern, the amount of data processing can be suppressed and the mask pattern can be efficiently corrected. However, in the correction process of Patent Document 1, the three-dimensional structure of the step pattern is not considered. Further, the correction process is performed by reducing and enlarging the correction target pattern by a predetermined amount, and thus there is a problem in correction accuracy.
JP 2001-133958 A

  The present invention provides a mask pattern correction method and a photomask manufacturing method capable of correcting a mask pattern transferred onto a step pattern with high accuracy in a short time.

  According to the first aspect of the present invention, (b) the layer extraction unit extracts the design mask pattern of the target layer and the step pattern formed in the lower layer of the target layer from the correction information database; The detection unit detects a plurality of intersections where the transfer image of the design mask pattern and the step pattern intersect, (c) the distance calculation unit calculates the intersection distances between the plurality of intersections, and (d) the region setting unit Based on the intersection distance, a first processing region including an intersection at each of the plurality of intersections is set on the arrangement surface of the design mask pattern, and (e) the shape calculation unit calculates the first processing area based on the step pattern. A mask pattern correction method comprising: calculating a first transfer image of a design mask pattern transferred in a processing region; and (f) correcting a design mask pattern based on the first transfer image by a correction unit. It is provided.

  According to the second aspect of the present invention, (b) the design mask pattern of the target layer and the step pattern formed in the lower layer of the target layer are extracted, and (b) the transfer image of the design mask pattern, the step pattern, (C) calculating intersection distances between the plurality of intersections, and (d) including intersections at each of the plurality of intersections on the arrangement surface of the design mask pattern based on the intersection distances. A first processing area and a second processing area excluding the first processing area are set, and (e) a first transfer of a design mask pattern transferred in the first processing area based on the step pattern. And (f) calculating a second transfer image of the design mask pattern transferred in the second processing region based on the planar shape of the design mask pattern, and (g) first and second transfer. The design mask pattern is corrected based on the image. Create a corrected mask pattern, based on the drawing data (h) correcting the mask pattern, a photomask manufacturing method comprising a photomask is provided.

  According to the present invention, it is possible to provide a mask pattern correction method and a photomask manufacturing method capable of correcting a mask pattern transferred onto a step pattern with high accuracy in a short time.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  As shown in FIG. 1, the mask pattern correction system according to the embodiment of the present invention includes a correction processing unit 10, a correction information database 12, a drawing data storage unit 16, and a program storage unit connected to the correction processing unit 10. 18. An input device 40 and an output device 42 are connected to the correction processing unit 10. A manufacturing management system 46 is connected to the correction information database 12. A drawing system 44 is connected to the drawing data storage unit 16. The correction processing unit 10 includes a layer extraction unit 22, an intersection detection unit 24, a distance calculation unit 26, a region division unit 28, a shape calculation unit 30, a correction unit 32, a data conversion unit 34, an internal storage unit 38, and the like.

  The layer extraction unit 22 of the correction processing unit 10 extracts a three-dimensional shape including the design mask pattern of the target layer and the step pattern formed below the target layer from the correction information database 12. The intersection detection unit 24 detects a plurality of intersections where the transfer image of the design mask pattern and the step pattern intersect. The distance calculation unit 26 calculates intersection distances between a plurality of intersections. Based on the calculated intersection distance, the region setting unit 28 includes a first processing region that includes an intersection at each of the plurality of intersections on the arrangement surface of the design mask pattern, and a second process that excludes the first processing region. Set the area. The shape calculation unit 30 calculates a first transfer image of the design mask pattern transferred in the first processing region based on the step pattern. In addition, the shape calculation unit 30 calculates a second transfer image of the design mask pattern transferred in the second processing region based on the planar shape of the design mask pattern. The correction unit 32 corrects the design mask pattern based on the first and second transfer images to create a correction mask pattern. The data conversion unit 34 converts the correction mask pattern into drawing data and stores it in the drawing data storage unit 16.

  The correction processing unit 10 may be configured as a part of a central processing unit (CPU) of a normal computer system. The layer extraction unit 22, the intersection detection unit 24, the distance calculation unit 26, the region division unit 28, the shape calculation unit 30, the correction unit 32, the data conversion unit 34, and the like may each be configured with dedicated hardware, The CPU may be configured as a functional means having a substantially equivalent function by software.

  The correction information database 12 stores correction information acquired by the correction processing unit 10. The correction information includes the design specifications of the circuit pattern of the semiconductor device, the three-dimensional shape of the transferred image by a plurality of manufacturing processes, and the like. The drawing data storage unit 16 stores mask pattern drawing data. The program storage unit 18 stores program instructions for each process executed by the correction processing unit 10. Program instructions are read into the CPU as necessary, and arithmetic processing is executed by the correction processing unit 10 in the CPU. At the same time, data such as numerical information generated at each stage of a series of arithmetic processing is stored in the internal storage unit 38 or the drawing data storage unit 16.

  The design information database 12, the drawing data storage unit 16, and the program storage unit 18 are configured by external storage devices such as semiconductor memory devices such as semiconductor ROM and semiconductor RAM, magnetic disk devices, magnetic drum devices, and magnetic tape devices, respectively. Alternatively, it may be constituted by a main storage device inside the CPU.

  The input device 40 refers to devices such as a keyboard and a mouse. When an input operation is performed from the input device 40, corresponding key information is transmitted to the correction processing unit 10. The output device 42 indicates a screen such as a monitor, and a liquid crystal display (LCD), a light emitting diode (LED) panel, an electroluminescence (EL) panel, or the like can be used. The output device 42 displays a mask pattern processed by the correction processing unit 10, a correction pattern obtained, and the like.

  For example, the correction information database 12 stores design specifications of a plurality of layers of photomasks corresponding to metal, oxide film, and semiconductor (MOS) transistor manufacturing processes. In the design mask pattern 50 of the first layer, as shown in FIG. 2, element region patterns 51 to 53 are arranged. As shown in FIG. 3, gate patterns 55 to 59 are arranged in the second layer design mask pattern 54. The gate pattern 55 includes thin line portions 555a to 555c that are parallel to each other. As shown in FIG. 4, ion implantation region patterns 61 to 63 are arranged in the third layer design mask pattern 60.

  As shown in FIG. 5, the element region patterns 51 to 53 are overlaid so as to be covered by the ion implantation region patterns 61 to 63, respectively. The thin line portions 555 a to 555 c of the gate pattern 55 are overlapped so as to intersect the opposing sides of the element region pattern 51 and the ion implantation region pattern 61. Similarly, the thin line portions of the gate patterns 56 and 57 intersect the opposing sides of the element region pattern 52 and the ion implantation region pattern 62, respectively. The thin line portions of the gate patterns 58 and 59 intersect the opposing sides of the element region pattern 53 and the ion implantation region pattern 63, respectively.

  A MOS transistor manufacturing process performed using the design mask patterns 50, 54, and 60 will be described with reference to process cross-sectional views in FIGS. 6 to 9, taking the AA cross section in FIG. 5 as an example. The manufacturing process is performed using a manufacturing apparatus (not shown) connected to the manufacturing management system 46 shown in FIG.

  By transferring the design mask pattern 50 onto the surface of the semiconductor substrate 100, an element region 151 surrounded by the element isolation 150 is formed as shown in FIG. As shown in FIG. 7, the design mask pattern 54 is transferred to form a gate electrode 155 having a gate insulating film (not shown) for dividing the element region 151 and thin line portions 255a to 255c. The design mask pattern 60 is transferred, and a resist pattern 160 is formed on the element isolation 150 so as to surround the element region 151 as shown in FIG.

  Thereafter, using the resist pattern 160 and the fine line portions 255a to 255c as a mask, impurities are implanted into the element region 151 separated by the fine line portions 255a to 255c by ion implantation. The resist pattern 160 is removed, and as shown in FIG. 9, impurity implantation regions 162a to 162j are formed between the element isolation 150 and the thin line portions 255a to 255c.

  As a result, as shown in FIG. 10, impurity implantation regions 162 a to 162 j divided by the thin line portions 255 a to 255 c of the gate electrode 155 are formed in the element region 151 defined by the element isolation 150. In the element region 152, impurity implantation regions 162e to 162g separated by the gate electrodes 156 and 157 are formed. In the element region 153, impurity implantation regions 162h to 162j divided by the gate electrodes 158 and 159 are formed.

  However, in an actual photolithography process, a shape change occurs in the transfer image of the resist pattern 160 due to the influence of the OPE and the step pattern in the lower layer. For example, as shown in FIG. 11, a round 162 is generated at the corner of the resist pattern 160 to which the ion implantation region pattern 61 of the design mask pattern 60 is transferred. In addition, tailings 164 are generated at corners of intersections 170a to 170f where the resist pattern 160 and the ends of the thin line portions 255a to 255c of the gate electrode 155 intersect. As shown in FIG. 12, the round 162 is a planar shape change of the resist pattern 160, and the tailing 164 is a three-dimensional shape change. That is, “rounding” is a shape change due to normal OPE caused by the planar shape of the mask pattern in the exposure process. The “tailing” is a shape change by OPE in a broad sense resulting from the planar shape of the mask pattern and the three-dimensional shape of the gate electrode. Hereinafter, in the embodiments of the present invention, “ordinary OPE” is simply referred to as “OPE”, and “broadly defined OPE” is referred to as “three-dimensional OPE”.

  When ion implantation is performed on the surface of the semiconductor substrate 100 in the element region 151 where the round 162 or the bottom 164 is generated using the resist pattern 160 as a mask, the ion concentration implanted into the round 162 or the bottom 164 is reduced. As a result, the amount of ion implantation designed for the semiconductor substrate 100 in the element region 151 is not performed, and the design performance of the semiconductor device cannot be obtained.

  OPE can be suppressed by OPC that corrects a mask pattern dimension by predicting a dimensional variation from a lithography simulation that takes into account the pattern arrangement of a neighboring region of several μm around the target pattern. However, the current OPC technique does not consider a three-dimensional shape such as a step pattern on the semiconductor substrate 100 before the resist pattern 160 is formed. Therefore, it is difficult to correct the tailing 164 generated at the corners of the intersections 170a to 170f by OPC that corrects the mask pattern from the lithography simulation based on the planar shape.

  The widths Wx and Wy of the skirt 164 shown in FIG. 11 depend on the intersection distances Dp and Ds, the step Hp of the gate electrode 155 shown in FIG. In the embodiment of the present invention, a manufacturing process verification test such as trial manufacture or lithography simulation is performed in advance under the control of the manufacturing management system 46. The manufacturing management system 46 acquires the relationship between the widths Wx, Wy, the intersection distances Dp, Ds, and the step Hp from the manufacturing process verification test, and stores them in the correction information database 12 as correction information.

  The layer extraction unit 22 of the correction processing unit 10 extracts, for example, the third layer shown in FIG. 3 as the target layer from the correction information database 12, and the first and second layers formed below the third layer. Extract 3D shape.

  The intersection detection unit 24 detects an intersection between the design mask pattern 60 of the third layer and the step pattern of the lower layer of the third layer. For example, on the arrangement surface of the design mask pattern 60, as shown in FIG. 13, intersections 70a to 70f corresponding to the intersections 170a to 170c shown in FIG. 11 are detected.

  The distance calculation unit 26 calculates the intersection distance between the intersections at each of the intersections 70a to 70f. The area setting unit 28 acquires the widths Wx and Wy of the tailing corresponding to the intersection distances of the intersections 70a to 70f from the correction information database 12, and sets a processing area for each of the intersections 70a to 70f. The processing area is, for example, a rectangle having a width twice as large as the bottom widths Wx and Wy so that the bottom edge is included in the processing area. Note that the size and shape of the processing region are not limited, and any shape in which tailing is included in the processing region is applicable. As shown in FIG. 14, the overlapping processing areas of the processing areas are combined to form the first processing areas 72 a to 72 c by the graphic processing of the logical sum of the processing areas set at the intersections 70 a to 70 f. Further, the second processing area 74 is set on the arrangement surface of the design mask pattern 60 except for the first processing areas 72a to 72c.

  In the first processing regions 72a to 72c, the shape calculation unit 30 performs lithography simulation based on the three-dimensional shape of the lower layer of the third layer and the planar shape of the design mask pattern 60, and the resist to which the design mask pattern 60 is transferred The shape of the pattern (first transfer image) is calculated. In addition, the shape calculation unit 30 performs a lithography simulation based on the planar shape of the design mask pattern 60 in the second processing region 74, and the shape of the resist pattern (second transfer image) to which the design mask pattern 60 is transferred. Is calculated.

  The correction unit 32 combines the resist pattern shapes calculated in the first and second processing regions 72a to 72c and 74, and corrects the design mask pattern 60 by OPC. For example, in the ion implantation region pattern 61a of the correction mask pattern 60a, as shown in FIG. 15, the first correction figure 80a and the ion implantation region pattern 61 are arranged around the positions corresponding to the intersections 70a and 70b of the thin line portion 555a. A second correction figure 82 is added to each corner.

  The figure added to the correction mask pattern 60a by OPC is not limited. For example, as shown in FIG. 16, in the ion implantation region pattern 61a, the first correction figure 80a is arranged in a region corresponding to each intersection of the thin line portions 555a to 555c of the gate pattern 55. In the ion implantation region pattern 62a, the first correction figure 80b is arranged so as to include a region corresponding to the intersection with the gate patterns 56 and 57. In the ion implantation region pattern 63a, first correction figures 80c and 80d are arranged in the vicinity of the region corresponding to the intersection with the gate patterns 58 and 59. The width of the first correction figures 80c and 80d in the short direction is equal to or less than the resolution limit of the exposure apparatus that transfers the mask pattern, and the first correction figures 80c and 80d are not transferred onto the semiconductor substrate. A second correction figure 82 is arranged at each corner of the ion implantation region patterns 61a to 63a.

  The data conversion unit 34 converts the correction mask pattern 60 a into drawing data and stores it in the drawing data storage unit 16. The drawing system 44 acquires the drawing data of the correction mask pattern 60a from the drawing data storage unit 16, and draws the correction mask pattern 60a on the mask blank by the drawing apparatus arranged in the drawing system 44.

  According to the mask pattern correction method according to the embodiment of the present invention, the intersection of the transfer image of the target design mask pattern and the lower step pattern is detected, and the first processing region is set based on the intersection distance. In the first processing region, the shape of the transferred image is calculated based on the lower three-dimensional shape. In the second processing area not including the intersection, the shape of the transfer image is calculated based on the planar shape of the target design pattern. Therefore, the mask pattern transferred onto the step pattern can be corrected with high accuracy in a short time.

  In the above description, the correction unit 32 combines the resist pattern shapes calculated in the first and second processing regions 72a to 72c and 74, and corrects the design mask pattern 60 by OPC. . However, OPC correction may be performed on each of the resist pattern shapes calculated in the first and second processing regions 72 a to 72 c and 74. For example, as shown in FIG. 17, in the first processing region 72a shown in FIG. 14, the first correction figure 80a is added to the periphery of the position corresponding to the intersections 70a and 70b in the ion implantation region pattern 61b. The In the second processing region 74, the second correction figure 82 is added to the corner of the ion implantation region pattern 61c. By the graphic processing, the ion implantation region patterns 61b and 61c are synthesized to obtain the correction mask pattern 60a shown in FIG.

  Next, a photomask manufacturing method using the mask pattern correction method according to the embodiment of the present invention will be described with reference to the flowchart of FIG. The correction information database 12 illustrated in FIG. 1 stores correction information such as a design mask pattern of a plurality of layers and a three-dimensional shape including a step pattern formed below each layer. In the manufacturing management system 46, the test mask pattern is transferred to the test step pattern, the test shape of the transferred image at the intersection of the test mask pattern intersecting the test step pattern is obtained, and the relationship between the intersection distance and the tailing Is stored in the correction information database 12.

  (A) In step S101, the layer extraction unit 22 of the correction processing unit 10 extracts the design mask pattern of the target layer from the correction information database 12. In step S102, a step pattern formed in the lower layer of the target layer is extracted. For example, the third layer is designated as the target layer, and the design mask pattern 60 shown in FIG. 4 is extracted. Further, the gate patterns 55 to 59 shown in FIG. 3 are extracted as the step patterns.

  (B) In step S103, the intersection detection unit 24 detects a plurality of intersections where the transfer image of the design mask pattern 60 and the transfer images of the gate patterns 55 to 59 intersect. For example, as illustrated in FIG. 13, intersections 70 a to 70 f are detected with respect to the gate pattern 55 on the arrangement surface of the design mask pattern 60.

  (C) In step S104, the distance calculation unit 26 calculates intersection distances between the plurality of intersections 70a to 70f.

  (D) In step S105, based on the intersection distance, the region setting unit 28 sets intersection points 70a to 70f at the plurality of intersection points 70a to 70f on the arrangement surface of the design mask pattern 60, as shown in FIG. The first processing areas 72a to 72c to be included are set. In addition, a second processing area 74 excluding the first processing areas 72a to 72c is set.

  (E) In step S <b> 106, the shape calculation unit 30 causes the design mask pattern 60 to be transferred in the first processing regions 72 a to 72 c based on the three-dimensional shape of the gate pattern 55 and the planar shape of the design mask pattern 60. One transfer image is calculated. Further, based on the planar shape of the design mask pattern 60, a second transfer image of the design mask pattern 60 transferred in the second processing region 74 is calculated.

  (F) In step S107, as shown in FIG. 16, the correction unit 32 corrects the design mask pattern 60 based on the first and second transfer images to create a correction mask pattern 60a.

  (H) In step S108, the correction mask pattern 60a is converted into drawing data by the data conversion unit 34 and stored in the drawing data storage unit 16.

  (I) In step S109, a photomask is produced by the drawing apparatus of the drawing system 44 based on the drawing data of the correction mask pattern 60a.

  According to the photomask manufacturing method according to the embodiment of the present invention, the photomask can be manufactured by correcting the mask pattern transferred onto the step pattern with high accuracy in a short time.

(Other embodiments)
Although the embodiments of the present invention have been described as described above, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the embodiment of the present invention, the ion implantation region is used as the target layer. However, the target layer is not limited to the ion implantation region. For example, it may be a layer including a mask pattern in which a lower step pattern and a transfer image intersect.

  As described above, the present invention naturally includes various embodiments that are not described herein. Accordingly, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is the schematic which shows an example of the mask pattern correction | amendment system which concerns on embodiment of this invention. It is the schematic which shows an example of the mask pattern used for description of embodiment of this invention. It is the schematic which shows an example of the mask pattern used for description to embodiment of this invention. It is the schematic which shows an example of the mask pattern used for description to embodiment of this invention. It is the schematic which shows the superimposition of the mask pattern shown in FIGS. It is process sectional drawing (the 1) which shows an example of the manufacturing process of the semiconductor device used for description of the mask pattern correction method which concerns on embodiment of this invention. It is process sectional drawing (the 2) which shows an example of the manufacturing process of the semiconductor device used for description of the mask pattern correction method which concerns on embodiment of this invention. It is process sectional drawing (the 3) which shows an example of the manufacturing process of the semiconductor device used for description of the mask pattern correction method which concerns on embodiment of this invention. It is process sectional drawing (the 4) which shows an example of the manufacturing process of the semiconductor device used for description of the mask pattern correction method which concerns on embodiment of this invention. It is a plane schematic diagram showing an example of a semiconductor device used for explanation of a mask pattern correction method concerning an embodiment of the invention. It is a plane schematic diagram showing an example of a transfer image used for explanation of a mask pattern correction method concerning an embodiment of the invention. It is the schematic which shows an example of the BB cross section of the transfer image shown in FIG. It is a plane schematic diagram which shows an example of the intersection used for description of the mask pattern correction method which concerns on embodiment of this invention. It is a plane schematic diagram showing an example of a processing field used for explanation of a mask pattern correction method concerning an embodiment of the invention. It is a plane schematic diagram showing an example of a mask pattern correction method according to an embodiment of the present invention. It is a plane schematic diagram showing an example of a correction mask pattern used for explanation of a mask pattern correction method concerning an embodiment of the invention. It is a plane schematic diagram which shows the other example of the mask pattern correction method which concerns on embodiment of this invention. It is a plane schematic diagram which shows the other example of the mask pattern correction method which concerns on embodiment of this invention. It is a flowchart which shows an example of the photomask manufacturing method which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Correction processing unit 12 Correction information database 12 Design information database 16 Drawing data storage part 18 Program storage part 22 Layer extraction part 24 Intersection detection part 26 Distance calculation part 28 Area division part 28 Area setting part 30 Shape calculation part 32 Correction part 34 Data Conversion unit 38 Internal storage unit 40 Input device 42 Output device 44 Drawing system 50, 54, 60 Design mask pattern 51-53 Element region pattern 55-59 Gate pattern 60a Correction mask pattern 61-63, 61a-63a Ion implantation region pattern 70a ˜70f, 170a˜170f Intersections 72a˜72c First treatment region 74 Second treatment region 100 Semiconductor substrate 150 Element isolation 151˜153 Element region 155˜159 Gate electrode 160 Resist pattern 162a˜16 j impurity implantation region 255a~255c, 555a~555c fine line portion

Claims (5)

A mask pattern correction method using a mask pattern correction system including a layer extraction unit, an intersection detection unit, a distance calculation unit, a region setting unit, a shape calculation unit, a correction unit, and a correction information database,
The layer extraction unit extracts, from the correction information database, a design mask pattern of a target layer and a step pattern formed in a lower layer of the target layer,
The intersection detection unit detects a plurality of intersections where the transfer image of the design mask pattern and the step pattern intersect,
The distance calculation unit calculates an intersection distance between the plurality of intersections;
The area setting unit sets a first processing area including the intersection at each of the plurality of intersections on the layout surface of the design mask pattern based on the intersection distance,
The shape calculation unit calculates a first transfer image of the design mask pattern transferred in the first processing region based on the step pattern,
The correction part includes correcting the design mask pattern based on the first transfer image. A mask pattern correction method comprising: The region setting unit sets a second processing region excluding the first processing region,
The shape calculating unit calculates a second transfer image of the design mask pattern transferred in the second processing region based on the planar shape of the target design mask pattern,
The mask pattern correction method according to claim 1, further comprising: correcting the design mask pattern based on the first and second transfer images.   The mask pattern correction method according to claim 1, wherein the first transfer image is a resist pattern.   4. The mask pattern correction method according to claim 3, wherein the first processing region is set based on a relationship between the intersection distance and a tailing of the resist pattern generated around the intersection. . Transfer the test mask pattern to the test step pattern, obtain the test shape of the transferred image of the test mask pattern intersecting the test step pattern,
Extracting a design mask pattern of the target layer and a step pattern formed in a lower layer of the target layer, detecting a plurality of intersections where the transfer image of the design mask pattern and the step pattern intersect, A step of calculating an intersection distance between intersections, a first processing region including the intersection at each of the plurality of intersections on the arrangement surface of the design mask pattern based on the intersection distance and the test shape; and A step of setting a second processing region excluding one processing region, a step of calculating a first transfer image of the design mask pattern transferred in the first processing region based on the step pattern, and the design A step of calculating a second transfer image of the design mask pattern transferred in the second processing region based on the planar shape of the mask pattern. , Said process including the step of correcting the design mask pattern by executing the mask pattern correction system based on the first and second transfer image, to create a corrected mask pattern,
A photomask production method comprising producing a photomask based on the drawing data of the correction mask pattern.

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