TWI649841B - High frequency module and manufacturing method thereof - Google Patents
High frequency module and manufacturing method thereof Download PDFInfo
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- TWI649841B TWI649841B TW102126185A TW102126185A TWI649841B TW I649841 B TWI649841 B TW I649841B TW 102126185 A TW102126185 A TW 102126185A TW 102126185 A TW102126185 A TW 102126185A TW I649841 B TWI649841 B TW I649841B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 338
- 239000004065 semiconductor Substances 0.000 claims abstract description 182
- 229920005989 resin Polymers 0.000 claims abstract description 140
- 239000011347 resin Substances 0.000 claims abstract description 140
- 239000002184 metal Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 14
- 238000002360 preparation method Methods 0.000 claims description 7
- 230000017525 heat dissipation Effects 0.000 abstract description 21
- 239000010410 layer Substances 0.000 description 103
- 235000012431 wafers Nutrition 0.000 description 34
- 229910000679 solder Inorganic materials 0.000 description 16
- 239000004020 conductor Substances 0.000 description 8
- 238000005498 polishing Methods 0.000 description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
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Abstract
目的在於提供一種散熱特性優異之模組及此模組之製造方法。 The purpose is to provide a module with excellent heat dissipation characteristics and a manufacturing method of the module.
模組2，具備：配線基板11；半導體基板9，構裝在配線基板11之一主面11a；柱狀之連接端子8，豎設在一主面11a；以及樹脂層13a，設在一主面11a，以半導體基板9之下面9a側之端部與連接端子8之下端部露出之方式被覆半導體基板9及連接端子8分別之側面之一部分，藉此，熱傳導率較樹脂層13a之樹脂高之半導體基板9之下面9a側之端部及連接端子8之下端部從樹脂層13a表面露出，因此可獲得散熱特性優異之模組2。 The module 2 includes a wiring board 11 , a semiconductor board 9 that is mounted on one main surface 11 a of the wiring board 11 , a columnar connection terminal 8 that is erected on a main surface 11 a, and a resin layer 13 a that is provided in a main body. The surface 11a is covered with a portion of the side surfaces of the semiconductor substrate 9 and the connection terminal 8 so that the end portion on the lower surface 9a side of the semiconductor substrate 9 and the lower end portion of the connection terminal 8 are exposed, whereby the thermal conductivity is higher than that of the resin layer 13a. The end portion on the lower surface 9a side of the semiconductor substrate 9 and the lower end portion of the connection terminal 8 are exposed from the surface of the resin layer 13a, so that the module 2 excellent in heat dissipation characteristics can be obtained.
Description
本發明係關於一種在配線基板之一主面上配置有半導體基板與連接端子之模組及此模組之製造方法。 The present invention relates to a module in which a semiconductor substrate and a connection terminal are disposed on one main surface of a wiring substrate, and a method of manufacturing the module.
近年來，隨著行動電話等行動終端裝置之小型、薄型化，要求搭載於此之模組之小型化。因此，在以往，如圖5所示，提案有具備在構成模組100之配線基板101之一主面上以面朝下構裝(覆晶構裝)之半導體基板102、與該半導體基板102配置在同一主面上之柱狀之連接端子103、及被覆半導體基板102及柱狀之連接端子103之樹脂層104之模組(專利文獻1)。 In recent years, with the miniaturization and thinning of mobile terminal devices such as mobile phones, it is required to miniaturize the modules mounted thereon. Therefore, as shown in FIG. 5, a semiconductor substrate 102 having a face-down configuration (flip-chip mounting) on one main surface of the wiring substrate 101 constituting the module 100 is proposed, and the semiconductor substrate 102 is provided. A columnar connection terminal 103 disposed on the same main surface, and a module covering the resin substrate 104 of the semiconductor substrate 102 and the columnar connection terminal 103 (Patent Document 1).
此情形，在模組100之一主面上形成有柱狀之連接端子103後，覆晶構裝半導體基板102，接著，形成被覆該半導體基板102及連接端子103之樹脂層104。接著，以連接端子103之端面從樹脂層104上面露出之方式，研磨樹脂層104與半導體基板102之上面而形成模組100。 In this case, after the columnar connection terminals 103 are formed on one main surface of the module 100, the semiconductor substrate 102 is flip-chip mounted, and then the resin layer 104 covering the semiconductor substrate 102 and the connection terminals 103 is formed. Next, the resin layer 104 and the upper surface of the semiconductor substrate 102 are polished so that the end faces of the connection terminals 103 are exposed from the upper surface of the resin layer 104 to form the module 100.
覆晶構裝之半導體基板102，在與配線基板101之對向面形成有電路，藉由研磨半導體基板102之上面(與配線基板之非對向面)，不改變半導體基板102之特性即可使模組100之高度變低，因此藉由研磨樹脂層104及半導體基板102直到連接端子103之端面露出為止，可使模組100之高度變低。又，熱傳導率較樹脂層104之樹脂高之半導體基板102之上面從 樹脂層104之表面露出，因此模組100之散熱特性亦提升。 In the flip-chip mounted semiconductor substrate 102, a circuit is formed on the surface opposite to the wiring substrate 101, and the upper surface of the semiconductor substrate 102 (the non-opposing surface of the wiring substrate) is polished, and the characteristics of the semiconductor substrate 102 are not changed. Since the height of the module 100 is made low, the height of the module 100 can be lowered by polishing the resin layer 104 and the semiconductor substrate 102 until the end faces of the connection terminals 103 are exposed. Further, the upper surface of the semiconductor substrate 102 having a thermal conductivity higher than that of the resin layer 104 is The surface of the resin layer 104 is exposed, so that the heat dissipation characteristics of the module 100 are also improved.
專利文獻1：日本特開2002-343904號(參照段落0013、圖1等) Patent Document 1: JP-A-2002-343904 (refer to paragraph 0013, FIG. 1 and the like)
然而，在上述習知技術，由於僅半導體基板102之上面從樹脂層104露出，因此在構裝發熱性高之半導體基板(例如，在高頻模組等使用之功率放大器IC等)之情形，會有散熱不足、半導體基板102產生誤動作等缺陷之虞。 However, in the above-described conventional technique, since only the upper surface of the semiconductor substrate 102 is exposed from the resin layer 104, there is a case where a semiconductor substrate having high heat generation (for example, a power amplifier IC used in a high frequency module or the like) is mounted. Defects such as insufficient heat dissipation and malfunction of the semiconductor substrate 102.
本發明係有鑑於上述問題而構成，其目的在於提供一種散熱特性優異之模組及此模組之製造方法。 The present invention has been made in view of the above problems, and an object thereof is to provide a module having excellent heat dissipation characteristics and a method of manufacturing the same.
為了達成上述目的，本發明之模組，具備：配線基板；半導體基板，構裝在該配線基板之一主面；以及樹脂層，設在該一主面，以該半導體基板之一面側之端部露出之方式被覆該半導體基板之側面之一部分。 In order to achieve the above object, a module of the present invention includes: a wiring substrate; a semiconductor substrate which is mounted on one main surface of the wiring substrate; and a resin layer provided on the main surface and on a side of the semiconductor substrate A portion of the side surface of the semiconductor substrate is covered in a manner of being exposed.
藉由以上述方式構成，不僅熱傳導率較樹脂層高之半導體基板之一面從樹脂層表面露出，側面之一部分亦從樹脂層表面露出，因此與僅半導體基板之一面從樹脂層露出之習知模組相較，可提升模組之散熱特性。 According to the above configuration, not only one surface of the semiconductor substrate having a higher thermal conductivity than the resin layer is exposed from the surface of the resin layer, but also one of the side surfaces is exposed from the surface of the resin layer, so that the conventional module is exposed from the resin layer only on one side of the semiconductor substrate. In comparison, the heat dissipation characteristics of the module can be improved.
又，在該配線基板之該一主面，以一端部從該樹脂層露出之方式豎設有柱狀之連接端子亦可。藉由以上述方式構成，藉由連接端子可連接模組與外部之母基板等。又，由於熱傳導率高之連接端子從樹脂層表面露出，因此亦可使從模組產生之熱從連接端子散熱，藉此，能進一步提 升模組之散熱特性。 Further, on one main surface of the wiring board, a columnar connection terminal may be vertically provided so that one end portion is exposed from the resin layer. According to the above configuration, the module and the external mother substrate can be connected by the connection terminal. Further, since the connection terminal having a high thermal conductivity is exposed from the surface of the resin layer, heat generated from the module can be dissipated from the connection terminal, thereby further improving The heat dissipation characteristics of the module.
又，由於連接端子之側面從樹脂層之表面露出，藉由焊料連接模組與母基板時，焊料形成濕潤至連接端子側面為止之狀態之圓角形狀，因此模組與母基板之連接強度提升。 Moreover, since the side surface of the connection terminal is exposed from the surface of the resin layer, when the solder is connected to the mother substrate, the solder forms a rounded shape in a state of being wetted to the side surface of the connection terminal, so that the connection strength between the module and the mother substrate is improved. .
又，該連接端子之該一端部側之端面離該配線基板之該一主面之高度較該半導體基板之該一面側之端面離該一主面之高度高亦可。如此，將模組連接於外部之母基板等時，半導體基板不會成為妨礙，可容易地進行模組與母基板之連接。 Further, the end surface on the one end side of the connection terminal may be higher than the height of the one main surface of the wiring substrate from the one end surface side of the semiconductor substrate. As described above, when the module is connected to the external mother substrate or the like, the semiconductor substrate is not hindered, and the connection between the module and the mother substrate can be easily performed.
又，該半導體基板之該一面側之端面離該配線基板之該一主面之高度較該連接端子之該一端部側之端面離該一主面之高度高亦可。此情形，將模組連接於母基板等時，半導體基板之一面與母基板之距離變短，因此從模組產生之熱容易透過形成在母基板之面狀之接地電極等散熱，模組之散熱特性進一步提升。 Further, a height of the one end surface of the semiconductor substrate from the one main surface of the wiring substrate may be higher than a height of the one end surface side of the connection terminal from the one main surface. In this case, when the module is connected to the mother substrate or the like, the distance between one surface of the semiconductor substrate and the mother substrate is shortened, so that heat generated from the module is easily transmitted through the ground electrode formed on the surface of the mother substrate, and the module is cooled. The heat dissipation characteristics are further improved.
又，藉由焊料連接母基板與連接端子時，母基板與連接端子之距離較母基板與半導體基板之距離大，因此可在母基板與連接端子之間形成間隙。如此，連接母基板與連接端子之焊料不會被擠壓，焊料不易從連接部分露出，因此可防止焊料與相鄰端子(例如，相鄰之連接端子)之短路。 Further, when the mother substrate and the connection terminal are connected by solder, the distance between the mother substrate and the connection terminal is larger than the distance between the mother substrate and the semiconductor substrate, so that a gap can be formed between the mother substrate and the connection terminal. In this way, the solder connecting the mother substrate and the connection terminal is not pressed, and the solder is not easily exposed from the connection portion, so that the short circuit of the solder and the adjacent terminal (for example, the adjacent connection terminal) can be prevented.
又，較佳為，該樹脂層表面與該半導體基板之接觸部，從該半導體基板側面在該一面側之端緣朝向樹脂層形成為展開之圓角狀。如此，施加於樹脂層表面與半導體基板之接觸部之應力係藉由形成為圓角狀之樹脂分散，因此可防止樹脂層之樹脂從半導體基板剝離。 Moreover, it is preferable that the contact portion between the surface of the resin layer and the semiconductor substrate is formed in a rounded shape from the end surface of the side surface of the semiconductor substrate toward the resin layer toward the resin layer. As described above, the stress applied to the contact portion between the surface of the resin layer and the semiconductor substrate is dispersed by the resin formed in a rounded shape, so that the resin of the resin layer can be prevented from being peeled off from the semiconductor substrate.
又，該半導體基板從該樹脂層表面突出之部分之角部被去角 亦可。藉由以上述方式構成，可抑制半導體基板之裂開或破裂。 Further, the corner portion of the semiconductor substrate protruding from the surface of the resin layer is chamfered Also. By configuring in the above manner, cracking or cracking of the semiconductor substrate can be suppressed.
又，在該半導體基板之該一主面形成有凹凸亦可。若在從樹脂層露出之半導體基板之一面形成有凹凸，則熱傳導率高之半導體基板之表面積(露出部分)增加，因此可謀求散熱特性進一步提升。 Further, irregularities may be formed on the one main surface of the semiconductor substrate. When irregularities are formed on one surface of the semiconductor substrate exposed from the resin layer, the surface area (exposed portion) of the semiconductor substrate having high thermal conductivity increases, and thus heat dissipation characteristics can be further improved.
又，在從樹脂層露出之該半導體基板之該一面之至少一部分形成有金屬膜亦可。此情形，藉由熱傳導率較半導體基板高之金屬膜，使模組之散熱特性進一步提升。又，藉由將金屬膜利用為與外部之母基板等之連接用之電極，能以連接端子與金屬膜進行模組與母基板之連接，因此可謀求母基板與模組之連接強度之提升。 Further, a metal film may be formed on at least a part of the one surface of the semiconductor substrate exposed from the resin layer. In this case, the heat dissipation characteristics of the module are further improved by the metal film having a higher thermal conductivity than the semiconductor substrate. Further, since the metal film is used as an electrode for connection to an external mother substrate or the like, the connection between the module and the mother substrate can be performed by the connection terminal and the metal film, so that the connection strength between the mother substrate and the module can be improved. .
又，在該金屬膜之表面形成有凹凸亦可。此情形，由於金屬膜之表面積增加，因此模組之散熱特性進一步提升。又，將金屬膜利用為與母基板之連接用之電極之情形，連接面積亦增加，因此可謀求模組與母基板之連接強度之提升。 Further, irregularities may be formed on the surface of the metal film. In this case, since the surface area of the metal film is increased, the heat dissipation characteristics of the module are further improved. Further, in the case where the metal film is used as an electrode for connection to the mother substrate, the connection area is also increased, so that the connection strength between the module and the mother substrate can be improved.
又，模組之製造方法，具備：準備步驟，準備具備配線基板、構裝在該配線基板之一主面之半導體基板、及被覆該半導體基板之設在該一主面之樹脂層之模組坯體；以及除去步驟，以該半導體基板之一面側之端部從該樹脂層表面露出之方式，研磨或研削該模組坯體之該樹脂層之表面以除去一部分。 Further, the method of manufacturing a module includes a preparation step of preparing a semiconductor substrate including a wiring substrate, a main surface of the wiring substrate, and a resin layer provided on the main surface of the semiconductor substrate And a removing step of polishing or grinding the surface of the resin layer of the module blank to remove a part of the surface of the surface of the resin substrate so as to be exposed from the surface of the resin layer.
藉由以上述方式製造模組，以半導體基板之一面側之端部露出之方式，可形成被覆半導體基板側面之一部分之樹脂層，因此可製造散熱特性優異之模組。 By manufacturing the module as described above, the resin layer covering one of the side faces of the semiconductor substrate can be formed so that the end portion on the one side of the semiconductor substrate is exposed. Therefore, a module having excellent heat dissipation characteristics can be manufactured.
又，在該準備步驟，準備進一步具備在被該樹脂層被覆之狀 態下豎設在該配線基板之該一主面之柱狀之連接端子之該模組坯體；在該除去步驟，以該半導體基板之該一面側之端部及該連接端子之一端部露出之方式除去該樹脂層之一部分亦可。 Further, in the preparation step, the preparation is further provided to be covered by the resin layer. The module blank erected on the columnar connection terminal of the one main surface of the wiring substrate; in the removing step, the end portion of the one side of the semiconductor substrate and one end of the connection terminal are exposed It is also possible to remove a part of the resin layer.
藉由以上述方式構成，可製造散熱特性優異且能與外部之母基板連接之模組。又，藉由使連接端子之一端部(包含側面)從樹脂層表面露出，藉由焊料連接模組與母基板時，該焊料濕潤至連接端子側面為止，因此可製造與母基板之連接強度高之模組。 According to the above configuration, it is possible to manufacture a module which is excellent in heat dissipation characteristics and can be connected to an external mother substrate. Further, by exposing one end portion (including the side surface) of the connection terminal from the surface of the resin layer, the solder is wetted to the side surface of the connection terminal by soldering the module and the mother substrate, so that the connection strength with the mother substrate can be made high. The module.
又，在該除去步驟，以該連接端子之該一端部側之端面離該配線基板之該一主面之高度較該半導體基板之該一面側之端面離該一主面之高度高之方式製造模組亦可。如此，可製造與外部之母基板之連接容易之模組。 Further, in the removing step, the end surface on the one end side of the connection terminal is manufactured such that the height of the one main surface of the wiring substrate is higher than the height of the one main surface of the one end surface of the semiconductor substrate. Modules are also available. In this way, it is possible to manufacture a module that is easy to connect to an external mother substrate.
又，在該除去步驟，以該半導體基板之該一面側之端面離該配線基板之該一主面之高度較該連接端子之該一端部側之端面離該一主面之高度高之方式製造模組亦可。如此，將母基板與模組(連接端子)加以連接時，由於母基板與半導體基板之距離變短，因此可製造從模組產生之熱容易透過母基板之接地電極等散熱之模組。 Further, in the removing step, the end surface on the one surface side of the semiconductor substrate is manufactured such that the height of the one main surface of the wiring substrate is higher than the height of the one main surface of the connection terminal from the one end side. Modules are also available. As described above, when the mother substrate and the module (connection terminal) are connected, since the distance between the mother substrate and the semiconductor substrate is shortened, it is possible to manufacture a module in which heat generated from the module is easily transmitted through the ground electrode of the mother substrate or the like.
又，由於母基板與連接端子之距離較母基板與半導體基板之距離大，因此可在母基板與連接端子之間形成間隙。如此，接合母基板與連接端子之焊料不會被擠壓，焊料不易從接合部分露出，因此可製造可防止與相鄰端子之短路之模組。 Further, since the distance between the mother substrate and the connection terminal is larger than the distance between the mother substrate and the semiconductor substrate, a gap can be formed between the mother substrate and the connection terminal. In this way, the solder for bonding the mother substrate and the connection terminal is not pressed, and the solder is not easily exposed from the joint portion, so that a module capable of preventing short-circuiting with the adjacent terminal can be manufactured.
根據本發明，以配置在配線基板之一主面之半導體基板之一面側之端部露出之方式，形成被覆半導體基板及連接端子分別之側面之一 部分之樹脂層，藉此，與以往般僅半導體基板之一面露出之模組相較，可謀求模組之散熱特性之提升。 According to the present invention, one of the sides of the covered semiconductor substrate and the connection terminal is formed so as to be exposed at the end portion on the one surface side of the semiconductor substrate on one main surface of the wiring substrate In part, the resin layer can improve the heat dissipation characteristics of the module as compared with the conventional module in which only one of the semiconductor substrates is exposed.
2‧‧‧模組 2‧‧‧ modules
8‧‧‧連接端子 8‧‧‧Connecting terminal
9‧‧‧半導體基板 9‧‧‧Semiconductor substrate
10‧‧‧金屬膜 10‧‧‧Metal film
11‧‧‧配線基板 11‧‧‧Wiring substrate
13a,13b‧‧‧樹脂層 13a, 13b‧‧‧ resin layer
18‧‧‧模組坯體 18‧‧‧Modular body
圖1係構裝有本發明一實施形態之模組之模組搭載裝置之剖斷前視圖。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional front view showing a module mounting device incorporating a module according to an embodiment of the present invention.
圖2係圖1之A區域之放大圖。 Figure 2 is an enlarged view of the area A of Figure 1.
圖3(a)~(c)係圖1之模組之製造方法之說明圖。 3(a) to (c) are explanatory views of a method of manufacturing the module of Fig. 1.
圖4(a)、(b)係圖1之模組之製造方法之說明圖。 4(a) and 4(b) are explanatory views of a method of manufacturing the module of Fig. 1.
圖5係習知模組之剖面圖。 Figure 5 is a cross-sectional view of a conventional module.
(模組搭載裝置之構成) (Composition of module mounting device)
參照圖1說明搭載有本發明一實施形態之模組2之模組搭載裝置1。此外，圖1係搭載有模組2之模組搭載裝置1之剖斷前視圖。 A module mounting device 1 on which a module 2 according to an embodiment of the present invention is mounted will be described with reference to Fig. 1 . In addition, FIG. 1 is a cutaway front view of the module mounting device 1 on which the module 2 is mounted.
搭載有本實施形態之模組2之模組搭載裝置1，如圖1所示，具備母基板3、構裝在該母基板3之模組2、及用以保護母基板3與模組2之連接部之由樹脂形成之底填樹脂層4，搭載於例如行動電話等使用高頻之電子機器。 As shown in FIG. 1 , the module mounting device 1 equipped with the module 2 of the present embodiment includes a mother substrate 3 , a module 2 mounted on the mother substrate 3 , and a mother substrate 3 and a module 2 . The underfill resin layer 4 formed of a resin in the connection portion is mounted on an electronic device using a high frequency such as a mobile phone.
母基板3，在內部形成有接地用之接地電極5與構成各種電路之配線圖案(未圖示)，接地電極5及配線圖案係藉由通孔導體6等連接於既定配線圖案或形成在母基板3之表面背面之構裝用電極7等。本實施形態中，形成在母基板3之接地電極5係透過通孔導體6連接於構裝電極7，該構裝電極7係連接於形成在後述模組2之柱狀之連接端子8及半導體基 板9之下面9a之金屬膜10。又，母基板3由玻璃環氧樹脂、陶瓷等材料形成。 The mother substrate 3 is internally formed with a grounding electrode 5 for grounding and a wiring pattern (not shown) constituting various circuits, and the ground electrode 5 and the wiring pattern are connected to a predetermined wiring pattern or formed in the mother via the via hole conductor 6 or the like. The electrode 7 for mounting on the front and back surfaces of the substrate 3 or the like. In the present embodiment, the ground electrode 5 formed on the mother substrate 3 is connected to the package electrode 7 through the via hole conductor 6, and the structure electrode 7 is connected to the columnar connection terminal 8 and the semiconductor base formed in the module 2 to be described later. The metal film 10 of the lower surface 9a of the board 9. Further, the mother substrate 3 is formed of a material such as glass epoxy resin or ceramic.
又，底填樹脂層4由例如環氧樹脂構成，以將在母基板3上構裝有模組2時之母基板3與模組2之間之間隙填埋之方式填充樹脂而形成。此外，無底填樹脂層4亦可。 Further, the underfill resin layer 4 is made of, for example, an epoxy resin, and is formed by filling a resin so as to fill a gap between the mother substrate 3 and the module 2 when the module 2 is mounted on the mother substrate 3. Further, the bottomless resin layer 4 may also be used.
(模組2之構成) (Composition of Module 2)
接著，參照圖1及圖2說明本實施形態之模組2。此外，圖2係圖1中A區域之放大圖。 Next, the module 2 of the present embodiment will be described with reference to Figs. 1 and 2 . In addition, FIG. 2 is an enlarged view of the area A in FIG.
模組2，如圖1所示，係具備配線基板11、構裝在該配線基板11之一主面11a之半導體基板9及豎設之柱狀之連接端子8、構裝在配線基板11之另一主面11b之晶片零件12a,12b,12c、被覆配線基板11之一主面11a之半導體基板9與連接端子8之樹脂層13a、被覆配線基板11之另一主面11b之晶片零件12a~12c之樹脂層13b之模組，作為其例，可舉出Bluetooth(註冊商標)模組、無線LAN模組、配置在行動電話之緊鄰天線下方之天線開關模組等。 As shown in FIG. 1, the module 2 includes a wiring board 11, a semiconductor substrate 9 that is mounted on one main surface 11a of the wiring board 11, and a columnar connection terminal 8 that is vertically disposed, and is mounted on the wiring board 11. The wafer part 12a, 12b, 12c of the other main surface 11b, the semiconductor substrate 9 of the main surface 11a of the wiring substrate 11 and the resin layer 13a of the connection terminal 8, and the wafer part 12a of the other main surface 11b of the covered wiring board 11 The module of the resin layer 13b of the ~12c is exemplified by a Bluetooth (registered trademark) module, a wireless LAN module, and an antenna switch module disposed under the antenna immediately adjacent to the mobile phone.
配線基板11由玻璃環氧樹脂基板、低溫同時燒成陶瓷(LTCC)基板、玻璃基板等形成，在其兩主面11a,11b形成構裝用電極15、連接端子8形成用之電極15a、配線圖案(未圖示)等，且在內部形成接地用之接地電極14、其他配線圖案(未圖示)、通孔導體(未圖示)等。此外，配線基板11使用單層基板及多層基板之任一者皆可。 The wiring board 11 is formed of a glass epoxy resin substrate, a low temperature simultaneous firing ceramic (LTCC) substrate, a glass substrate, or the like, and the electrode 15 for forming, the electrode 15a for forming the connection terminal 8, and the wiring are formed on the both main surfaces 11a and 11b. A ground electrode 14 for grounding, another wiring pattern (not shown), a via conductor (not shown), and the like are formed inside the pattern (not shown) or the like. Further, the wiring board 11 may be either a single layer substrate or a multilayer substrate.
例如，配線基板11為LTCC多層基板之情形之製造方法，形成氧化鋁及玻璃等之混合粉末與有機結合劑及溶劑等一起混合後之漿料 片化後之陶瓷坯片，在此陶瓷坯片之既定位置藉由雷射加工等形成通孔，將含有Ag或Cu等之導體糊填充於已形成之通孔，形成層間連接用之通孔導體，藉由使用導體糊之印刷形成各種電極圖案。之後，藉由將各陶瓷坯片積層、壓接形成陶瓷積層體，在約1000℃前後之低溫進行燒成、所謂低溫燒成而製造。 For example, in the case where the wiring board 11 is a LTCC multilayer substrate, a slurry in which a mixed powder of alumina, glass, or the like is mixed with an organic binder and a solvent is formed. After the diced ceramic green sheet is formed, a through hole is formed by laser processing or the like at a predetermined position of the ceramic green sheet, and a conductor paste containing Ag or Cu is filled in the formed through hole to form a through hole for interlayer connection. The conductor is formed into various electrode patterns by printing using a conductor paste. Thereafter, each ceramic green sheet is laminated and pressure-bonded to form a ceramic laminate, which is produced by firing at a low temperature of about 1000 ° C and so-called low-temperature firing.
又，在配線基板11之兩主面11a,11b，作為構裝零件，構裝半導體基板9與晶片零件12a~12c。半導體基板9，藉由在與配線基板11之一主面11a對向之表面形成既定電路，構成例如處理RF訊號或基頻訊號之系統IC，面朝下構裝(覆晶構裝)於配線基板11之一主面11a。又，晶片零件12a~12c由晶片電容器、晶片電感器、晶片電阻構成，藉由周知之表面構裝技術構裝在配線基板11之另一主面11b。又，柱狀(銷狀)之連接端子8以例如Cu為主成分，透過焊料構裝在形成在配線基板11之一主面之電極15a。 Further, on both main surfaces 11a and 11b of the wiring board 11, the semiconductor substrate 9 and the wafer components 12a to 12c are mounted as a component. The semiconductor substrate 9 is formed with a predetermined circuit on the surface facing the main surface 11a of the wiring substrate 11, and is configured, for example, to form a system IC for processing an RF signal or a fundamental signal, and to face down (flip-chip) for wiring. One of the main faces 11a of the substrate 11. Further, the wafer components 12a to 12c are composed of a wafer capacitor, a chip inductor, and a chip resistor, and are mounted on the other main surface 11b of the wiring substrate 11 by a known surface mounting technique. Further, the columnar (pin-shaped) connection terminal 8 is mainly composed of, for example, Cu, and is soldered to the electrode 15a formed on one main surface of the wiring substrate 11.
此情形，在配線基板11之一主面11a僅配置覆晶構裝之半導體基板9與連接端子8，在配線基板11之另一主面11b配置半導體基板9以外之其他構裝零件(晶片零件12a~12c)。又，在半導體基板9之下面9a(相當於本發明之一面)與連接端子8之下端面8a形成金屬膜10。此金屬膜10為例如在半導體基板9之下面9a(或連接端子8之下端面8a)形成Ni層且從該Ni層之上形成有Au層之Ni/Au膜。 In this case, only the semiconductor substrate 9 and the connection terminal 8 of the flip chip are disposed on one main surface 11a of the wiring substrate 11, and the other components (wafer parts) other than the semiconductor substrate 9 are disposed on the other main surface 11b of the wiring substrate 11. 12a~12c). Further, a metal film 10 is formed on the lower surface 9a of the semiconductor substrate 9 (corresponding to one surface of the present invention) and the lower end surface 8a of the connection terminal 8. This metal film 10 is, for example, a Ni/Au film in which an Ni layer is formed on the lower surface 9a of the semiconductor substrate 9 (or the lower end surface 8a of the connection terminal 8) and an Au layer is formed on the Ni layer.
又，在構裝在配線基板11之另一主面11b之晶片零件12a~12c之中，在分別被構裝之狀態下，有離配線基板11之另一主面11b之高度不同者，本實施形態中，如圖1所示，晶片零件12a在所有晶片零件12a~12c之中離配線基板11之另一主面11b之高度最低。又，半導體基板9 與連接端子8分別在構裝或豎設之狀態下，形成為離配線基板11之一主面11a之高度相同。 Further, in the wafer components 12a to 12c which are mounted on the other main surface 11b of the wiring board 11, in the state in which they are respectively mounted, the height of the other main surface 11b of the wiring board 11 is different. In the embodiment, as shown in FIG. 1, the wafer component 12a has the lowest height from the other main surface 11b of the wiring substrate 11 among all the wafer components 12a to 12c. Also, the semiconductor substrate 9 The connection terminal 8 is formed to be the same height as one main surface 11a of the wiring substrate 11 in a state of being mounted or erected, respectively.
再者，在配線基板11之一主面11a，以離配線基板11之一主面11a之高度最高之半導體基板9(或連接端子8)之高度Ht較配線基板11之另一主面11b之晶片零件12a(在另一主面11b高度最低之晶片零件)離該另一主面11b之高度H0低之方式形成有半導體基板9(或連接端子8)。 Further, in one main surface 11a of the wiring substrate 11, the height Ht of the semiconductor substrate 9 (or the connection terminal 8) having the highest height from one main surface 11a of the wiring substrate 11 is smaller than the other main surface 11b of the wiring substrate 11. Part wafer 12a (11b the height of the lowest part on the other main surface of the wafer) from a low height H 0 of the mode of the other main surface 11b of the semiconductor substrate 9 is formed (connection terminal 8).
又，使用分別俯視各構裝零件9,12a~12c之情形，半導體基板9較其他構裝零件(各晶片零件12a~12c)之任一者面積(橫剖面積)皆較大者。 Further, in the case where the respective components 9 and 12a to 12c are viewed in plan, the semiconductor substrate 9 has a larger area (cross-sectional area) than any of the other components (the respective wafer components 12a to 12c).
此外，以連接端子8之下端面8a(一面側之端面)離配線基板11之一主面11a之高度較半導體基板9之下面9a(一面側之端面)離一主面11a之高度高之方式形成連接端子8亦可。藉由以上述方式形成連接端子8，將模組2構裝於外部之母基板3時，半導體基板9不會成為妨礙，可提升模組2之構裝性。 Further, the height of one main surface 11a of the wiring substrate 11 from the lower end surface 8a (the end surface on the one surface side) of the connection terminal 8 is higher than the height of the main surface 11a of the lower surface 9a (the end surface on the one surface side) of the semiconductor substrate 9 The connection terminal 8 may be formed. When the connection terminal 8 is formed as described above and the module 2 is mounted on the external mother substrate 3, the semiconductor substrate 9 does not become an obstacle, and the mountability of the module 2 can be improved.
又，以半導體基板9之下面9a離配線基板11之一主面11a之高度較連接端子8之下端面8a離一主面11a之高度高之方式形成半導體基板9亦可。此情形，將模組2連接於母基板3時，半導體基板9之下面9a與母基板3之距離變短，因此從模組2產生之熱容易透過形成在母基板3之面狀之接地電極5散熱，模組2之散熱特性提升。 Further, the semiconductor substrate 9 may be formed such that the height of the lower surface 9a of the semiconductor substrate 9 from the main surface 11a of the wiring substrate 11 is higher than the height of the lower surface 8a of the connection terminal 8 from the main surface 11a. In this case, when the module 2 is connected to the mother substrate 3, the distance between the lower surface 9a of the semiconductor substrate 9 and the mother substrate 3 is shortened, so that heat generated from the module 2 is easily transmitted through the ground electrode formed on the surface of the mother substrate 3. 5 heat dissipation, module 2's heat dissipation characteristics are improved.
又，藉由焊料連接母基板3與連接端子8時，母基板與連接端子8之距離較母基板與半導體基板9之距離大，因此可在母基板與連接端子8之間形成間隙。如此，連接母基板與連接端子8之焊料不會被擠壓， 焊料不易從連接部分露出，因此可防止與和連接端子8相鄰之其他端子之短路。 Moreover, when the mother substrate 3 and the connection terminal 8 are connected by solder, the distance between the mother substrate and the connection terminal 8 is larger than the distance between the mother substrate and the semiconductor substrate 9, so that a gap can be formed between the mother substrate and the connection terminal 8. Thus, the solder connecting the mother substrate and the connection terminal 8 is not squeezed. The solder is not easily exposed from the connection portion, so that short-circuiting with other terminals adjacent to the connection terminal 8 can be prevented.
配線基板11之一主面11a之樹脂層13a由例如環氧樹脂構成，如圖1所示，以半導體基板9之下面9a側之端部與連接端子8之下端部(相當於本發明之一端部)露出之方式，被覆半導體基板9及連接端子8分別之側面之一部分而形成。半導體基板9之下面9a側之端部係包含半導體基板9之下面9a及與半導體基板9之下面9a相鄰之側面之一部分之部分。亦即，以半導體基板9之下端部與連接端子8之下端部分別從樹脂層13a表面突出之方式形成樹脂層13a。 The resin layer 13a of one main surface 11a of the wiring substrate 11 is made of, for example, an epoxy resin, and as shown in FIG. 1, the end portion on the lower surface 9a side of the semiconductor substrate 9 and the lower end portion of the connection terminal 8 (corresponding to one end of the present invention) The portion is formed to cover one of the side faces of the semiconductor substrate 9 and the connection terminal 8, respectively. The end portion on the lower surface 9a side of the semiconductor substrate 9 includes a portion of the lower surface 9a of the semiconductor substrate 9 and a portion of the side surface adjacent to the lower surface 9a of the semiconductor substrate 9. In other words, the resin layer 13a is formed so that the lower end portion of the semiconductor substrate 9 and the lower end portion of the connection terminal 8 protrude from the surface of the resin layer 13a, respectively.
此時，樹脂層13a表面與半導體基板9之接觸部16，如圖2所示，從半導體基板9側面9b在該半導體基板9下面側之端緣朝向樹脂層13a形成為展開之圓角狀。又，半導體基板9從樹脂層13a表面突出之部分之角部9c被去角。此等形狀可藉由後述除去樹脂之除去步驟形成。 At this time, as shown in FIG. 2, the contact portion 16 between the surface of the resin layer 13a and the semiconductor substrate 9 is formed in a rounded shape from the end surface 9b of the semiconductor substrate 9 on the lower surface side of the semiconductor substrate 9 toward the resin layer 13a. Further, the corner portion 9c of the portion of the semiconductor substrate 9 that protrudes from the surface of the resin layer 13a is chamfered. These shapes can be formed by the removal step of removing the resin described later.
配線基板11之另一主面11b之樹脂層13b由例如與一主面11a之樹脂層13a同種之環氧樹脂構成，如圖1所示，以各晶片零件12a~12c不露出之方式在被覆各晶片零件全部之狀態下形成。 The resin layer 13b of the other main surface 11b of the wiring board 11 is made of, for example, the same type of epoxy resin as the resin layer 13a of the main surface 11a, and is covered as shown in Fig. 1 so that the wafer parts 12a to 12c are not exposed. Each wafer component is formed in all states.
此外，在樹脂層13b側之厚度相對於樹脂層13a側之厚度充分厚之情形等，模組2之彎曲較大時，為了抑制該彎曲，較佳為，形成樹脂層13b之樹脂係使用線膨脹係數較形成樹脂層13a之樹脂小者。 Further, when the thickness of the resin layer 13b side is sufficiently thick with respect to the thickness of the resin layer 13a side or the like, when the bending of the module 2 is large, in order to suppress the bending, it is preferable to form the resin-based use line of the resin layer 13b. The coefficient of expansion is smaller than that of the resin forming the resin layer 13a.
(模組2之製造方法) (Manufacturing method of module 2)
接著，參照圖3及圖4說明本實施形態之模組2之製造方法。此外，圖3係顯示製造模組2之各步驟之一部分，圖4係顯示接續圖3之各步驟。 Next, a method of manufacturing the module 2 of the present embodiment will be described with reference to Figs. 3 and 4 . In addition, FIG. 3 shows a part of each step of manufacturing the module 2, and FIG. 4 shows the steps of the subsequent FIG.
首先，如圖3(a)所示，準備配線基板11，該配線基板11，在其內部形成面狀之接地用接地電極14與配線圖案，且在其兩主面11a,11b形成有半導體基板9與各晶片零件12a~12c之構裝用電極15及連接端子形成用之電極15a(配線基板準備步驟)。 First, as shown in FIG. 3(a), a wiring board 11 is formed in which a planar grounding ground electrode 14 and a wiring pattern are formed, and a semiconductor substrate is formed on both main surfaces 11a, 11b. 9 and the electrode 15 for forming the respective wafer parts 12a to 12c and the electrode 15a for forming a connection terminal (wiring substrate preparation step).
接著，如圖3(b)所示，在配線基板11之構裝用電極15分別對應之位置構裝半導體基板9、連接端子8及各晶片零件12a~12c(零件、連接端子構裝步驟)。此時，將半導體基板9面朝下構裝(覆晶構裝)在配線基板11之一主面11a，將各晶片零件12a~12c藉由周知之表面構裝技術構裝在配線基板11之另一主面11b。又，在配線基板11之連接端子形成用之電極15透過焊料構裝銷狀之連接端子8。作為連接端子8，可使用例如Cu或由以Cu為主成分之合金構成之柱狀之金屬。 Then, as shown in FIG. 3(b), the semiconductor substrate 9, the connection terminal 8, and each of the wafer components 12a to 12c are mounted at positions corresponding to the electrode 15 for the wiring substrate 11 (parts and connection terminal mounting steps). . At this time, the semiconductor substrate 9 is placed face down on the main surface 11a of the wiring substrate 11, and the wafer components 12a to 12c are mounted on the wiring substrate 11 by a known surface mounting technique. The other main face 11b. Moreover, the electrode 15 for forming the connection terminal of the wiring substrate 11 is transmitted through the solder-connected pin-shaped connection terminal 8. As the connection terminal 8, for example, Cu or a columnar metal composed of an alloy containing Cu as a main component can be used.
接著，如圖3(c)所示，在配線基板11之一主面11a，形成被覆半導體基板9及連接端子8之樹脂層13a，且在另一主面11b形成被覆各晶片零件12a~12c之樹脂層13b(樹脂層形成步驟)。此時，使用分配方式或印刷方式等在兩主面11a,11b上塗布或印刷樹脂，放入設定成既定硬化溫度(例如，若為環氧樹脂則為180℃程度)之烤爐，使樹脂硬化而形成兩樹脂層13a,13b。 Then, as shown in FIG. 3(c), the resin layer 13a covering the semiconductor substrate 9 and the connection terminal 8 is formed on one main surface 11a of the wiring substrate 11, and the respective wafer parts 12a to 12c are formed on the other main surface 11b. The resin layer 13b (resin layer forming step). At this time, the resin is applied or printed on the both main surfaces 11a and 11b by a distribution method or a printing method, and an oven set to a predetermined curing temperature (for example, 180 ° C in the case of an epoxy resin) is placed in the oven to make the resin. The two resin layers 13a, 13b are formed by hardening.
以上述方式，製造模組坯體18，該模組坯體18具備構裝在配線基板11之一主面11a之半導體基板9及柱狀之連接端子8、設在配線基板11之一主面11a之被覆半導體基板9及連接端子8之樹脂層13a、構裝在配線基板11之另一主面11b之晶片零件12a~12c、及設在配線基板11之另一主面11b之被覆各晶片零件12a~12c之樹脂層13b。 In the above-described manner, the module blank 18 is provided, and the module blank 18 includes the semiconductor substrate 9 and the columnar connection terminal 8 which are formed on one main surface 11a of the wiring substrate 11, and is provided on one main surface of the wiring substrate 11. The resin layer 13a covering the semiconductor substrate 9 and the connection terminal 8 of 11a, the wafer components 12a to 12c which are mounted on the other main surface 11b of the wiring substrate 11, and the respective wafers provided on the other main surface 11b of the wiring substrate 11 The resin layer 13b of the parts 12a to 12c.
此外，如上述作為連接端子8使用銷狀之金屬，則在半導體基板9之構裝步驟可容易構裝連接端子8，但連接端子8之形成方法除了上述方法外，在配線基板11之一主面11a構裝半導體基板9前，藉由鍍敷處理形成柱狀之連接端子8亦可。此情形，在連接端子8形成後構裝半導體基板9，藉由樹脂被覆構裝在一主面11a上之半導體基板9及連接端子8而形成樹脂層13a即可。根據此方法，與構裝上述銷狀之連接端子8之情形不同，即使研磨或研削連接端子8，用以連接連接端子之焊料亦不會如上述從樹脂層13a露出。是以，可在配線基板11之一主面11a上高精度地形成細微徑之連接端子8，能使連接端子8狹間距化。 Further, as described above, the pin-shaped metal is used as the connection terminal 8, and the connection terminal 8 can be easily assembled in the assembly step of the semiconductor substrate 9, but the method of forming the connection terminal 8 is one of the wiring substrates 11 in addition to the above method. Before the surface 11a is mounted on the semiconductor substrate 9, the columnar connection terminals 8 may be formed by plating. In this case, the semiconductor substrate 9 is formed after the connection terminal 8 is formed, and the resin layer 13a is formed by coating the semiconductor substrate 9 and the connection terminal 8 on the main surface 11a with a resin. According to this method, unlike the case where the pin-shaped connecting terminal 8 is constructed, even if the connecting terminal 8 is ground or ground, the solder for connecting the connecting terminal is not exposed from the resin layer 13a as described above. Therefore, the connection terminals 8 having the fine diameter can be formed on the main surface 11a of one of the wiring boards 11 with high precision, and the connection terminals 8 can be narrowed.
又，在構裝半導體基板9後、形成連接端子8前，形成樹脂層13a，藉由對樹脂層13a之表面照射雷射等，以連接端子形成用電極15a之表面露出之方式在樹脂層13a形成連接端子形成用之凹部，使用印刷技術對該凹部填充導電糊(例如，Ag糊或Cu糊)、或藉由鍍敷處理等形成導體(例如，Cu)、或在配線基板11之一主面11a形成柱狀之連接端子8亦可。 In addition, after the semiconductor substrate 9 is formed, the resin layer 13a is formed, and the surface of the resin layer 13a is irradiated with a laser or the like, and the surface of the terminal forming electrode 15a is exposed in the resin layer 13a. A recess for forming a connection terminal is formed, and the recess is filled with a conductive paste (for example, an Ag paste or a Cu paste) by a printing technique, or a conductor (for example, Cu) is formed by a plating process or the like, or one of the wiring substrates 11 is formed. The surface 11a may be formed as a columnar connection terminal 8.
此外，圖3(a)~圖3(c)之步驟(配線基板準備步驟~樹脂層形成步驟)相當於本發明之準備步驟。 Further, the steps (the wiring board preparation step to the resin layer forming step) of FIGS. 3(a) to 3(c) correspond to the preparation steps of the present invention.
接著，如圖4(a)所示，以半導體基板9之下面9a與連接端子8之下端部從樹脂層13a表面露出之方式，研磨或研削模組坯體18之樹脂層13a表面以除去一部分(除去步驟)。 Next, as shown in FIG. 4(a), the lower surface 9a of the semiconductor substrate 9 and the lower end portion of the connection terminal 8 are exposed from the surface of the resin layer 13a, and the surface of the resin layer 13a of the module blank 18 is ground or ground to remove a part. (Remove the steps).
例如，藉由研磨除去樹脂層13a之樹脂之情形，較佳為，藉由使用游離磨粒之拋光研磨、噴砂等進行。藉由調整游離磨粒之粒徑或材質等，可優先地除去樹脂層13a之樹脂，因此能以半導體基板9之下面9a 側之端部及連接端子8之下端部露出之方式，容易形成被覆半導體基板9及連接端子8分別之側面之一部分之樹脂層13a。此外，在此步驟，除去半導體基板9及連接端子8之下端部之一部分亦可。 For example, in the case where the resin of the resin layer 13a is removed by polishing, it is preferably carried out by polishing, blasting or the like using free abrasive grains. By adjusting the particle size, material, and the like of the free abrasive grains, the resin of the resin layer 13a can be preferentially removed, so that the lower surface 9a of the semiconductor substrate 9 can be used. The resin layer 13a covering one of the side faces of the semiconductor substrate 9 and the connection terminal 8 is easily formed so that the end portion of the side and the lower end portion of the connection terminal 8 are exposed. Further, in this step, the semiconductor substrate 9 and a portion of the lower end portion of the connection terminal 8 may be removed.
又，藉由除去步驟，半導體基板9之從樹脂層13a表面突出之部分之角部9c被去角，且樹脂層13a表面與半導體基板9(側面9b)之接觸部16，從半導體基板9側面9b之該半導體基板9之下面9a側之端緣朝向樹脂層13a形成為展開之圓角狀(參照圖2)。此外，藉由調整游離磨粒之粒徑或材質等，角部9c不被去角亦可，使接觸部16不為圓角狀亦可。再者，以在半導體基板9之下面9a亦可形成凹凸之方式進行研磨或研削。如上述，若在半導體基板9之下面9a形成凹凸，則在該下面9a形成金屬膜10時，在該金屬膜10亦可形成凹凸，可增加熱傳導率高之金屬膜10之表面積。 Further, by the removing step, the corner portion 9c of the portion of the semiconductor substrate 9 protruding from the surface of the resin layer 13a is chamfered, and the contact portion 16 between the surface of the resin layer 13a and the semiconductor substrate 9 (side surface 9b) is flanked from the side of the semiconductor substrate 9. The edge of the lower surface 9a side of the semiconductor substrate 9 of 9b is formed in a rounded shape toward the resin layer 13a (see Fig. 2). Further, the corner portion 9c may not be chamfered by adjusting the particle diameter or material of the free abrasive grains, and the contact portion 16 may not be rounded. Further, polishing or grinding may be performed so as to form irregularities on the lower surface 9a of the semiconductor substrate 9. As described above, when irregularities are formed on the lower surface 9a of the semiconductor substrate 9, when the metal film 10 is formed on the lower surface 9a, irregularities can be formed in the metal film 10, and the surface area of the metal film 10 having high thermal conductivity can be increased.
此外，若半導體基板9之下面9a之平均粗度(Ra)之值過小，則不易在半導體基板9之下面9a藉由鍍敷處理等形成金屬膜10，若平均粗度(Ra)之值過大，則有半導體基板9破損之虞，因此較佳為，形成在半導體基板9之下面9a之凹凸以表面平均粗度(Ra)為0.1μm~15μm之範圍形成。 Further, when the value of the average thickness (Ra) of the lower surface 9a of the semiconductor substrate 9 is too small, it is difficult to form the metal film 10 by plating treatment or the like on the lower surface 9a of the semiconductor substrate 9, and if the value of the average roughness (Ra) is too large In the case where the semiconductor substrate 9 is damaged, it is preferable that the unevenness formed on the lower surface 9a of the semiconductor substrate 9 is formed in a range of a surface average roughness (Ra) of 0.1 μm to 15 μm.
又，本實施形態中，在除去步驟，以半導體基板9及連接端子8分別離配線基板11之一主面11a之高度相同之方式，與樹脂層13a表面一起研磨或研削半導體基板9及連接端子8。再者，以離配線基板11之一主面11a之高度最高之半導體基板9(或連接端子8)之高度Ht較離配線基板11之另一主面11b之高度最低之晶片零件12a之高度H0低之方式，研磨或研削半導體基板9(或連接端子8)。 Further, in the present embodiment, in the removal step, the semiconductor substrate 9 and the connection terminal are ground or ground together with the surface of the resin layer 13a so that the height of the semiconductor substrate 9 and the connection terminal 8 are the same as the height of one of the main surfaces 11a of the wiring substrate 11 8. Further, the height Ht of the semiconductor substrate 9 (or the connection terminal 8) having the highest height from one main surface 11a of the wiring substrate 11 is lower than the height H of the wafer part 12a having the lowest height from the other main surface 11b of the wiring substrate 11. The semiconductor substrate 9 (or the connection terminal 8) is ground or ground in a low- zero manner.
此外，如上述，半導體基板9與連接端子8分別離配線基板 11之一主面11a之高度不一定要一致，以其中一方較高之方式研磨或研削半導體基板9(或連接端子8)亦可。此情形，例如，藉由調整研磨時使用之游離磨粒之粒徑或材質等，可調整半導體基板9及連接端子8之高度。 Further, as described above, the semiconductor substrate 9 and the connection terminal 8 are respectively separated from the wiring substrate The height of one of the main faces 11a is not necessarily uniform, and the semiconductor substrate 9 (or the connection terminal 8) may be ground or ground in such a manner that one of them is higher. In this case, for example, the height of the semiconductor substrate 9 and the connection terminal 8 can be adjusted by adjusting the particle size or material of the free abrasive grains used for polishing.
接著，如圖4(b)所示，在從樹脂層13表面露出之半導體基板9之下面9a及連接端子8之下端面8a形成金屬膜10(金屬膜形成步驟)，製造模組2。此時，金屬膜10係使用鍍敷處理或印刷技術等形成。例如，鍍敷處理之情形，在半導體基板9之下面9a及連接端子8之下端面8a使Ni層成長，從其上使Au層成長以形成金屬膜10。此外，半導體基板9之下面9a之金屬膜10無需形成在半導體基板9之下面9a之整面，只要形成在至少一部分即可。 Next, as shown in FIG. 4(b), the metal film 10 (metal film forming step) is formed on the lower surface 9a of the semiconductor substrate 9 exposed from the surface of the resin layer 13 and the lower end surface 8a of the connection terminal 8, and the module 2 is manufactured. At this time, the metal film 10 is formed using a plating process, a printing technique, or the like. For example, in the case of the plating treatment, the Ni layer is grown on the lower surface 9a of the semiconductor substrate 9 and the lower end surface 8a of the connection terminal 8, and the Au layer is grown thereon to form the metal film 10. Further, the metal film 10 of the lower surface 9a of the semiconductor substrate 9 need not be formed on the entire surface of the lower surface 9a of the semiconductor substrate 9, as long as it is formed in at least a part.
此外，製造模組搭載裝置1之情形，以藉由上述模組2之製造方法製造之模組2之配線基板11之一主面11a與母基板3對向之方式，透過焊料等將形成在半導體基板9之下面9a及連接端子8之下端面8a之金屬膜10與形成在母基板3之表面之構裝電極7加以連接而製造。 In the case of manufacturing the module mounting device 1, the main surface 11a of the wiring substrate 11 of the module 2 manufactured by the manufacturing method of the module 2 is opposed to the mother substrate 3, and is formed by solder or the like. The lower surface 9a of the semiconductor substrate 9 and the metal film 10 on the lower end surface 8a of the connection terminal 8 are connected to the constituent electrode 7 formed on the surface of the mother substrate 3 to be manufactured.
此外，在母基板3與模組2之連接不使用焊料，例如，在使用導電性接著劑之情形，在半導體基板9及連接端子8不形成金屬膜10亦可連接母基板3與模組2。 In addition, solder is not used for the connection between the mother substrate 3 and the module 2. For example, in the case where a conductive adhesive is used, the mother substrate 3 and the module 2 may be connected to the semiconductor substrate 9 and the connection terminal 8 without forming the metal film 10. .
是以，根據上述實施形態，在配線基板11之一主面11a僅配置覆晶構裝之半導體基板9與連接端子8，且在另一主面11b配置晶片電容器等之晶片零件12a~12c。 According to the above-described embodiment, only the semiconductor substrate 9 and the connection terminal 8 of the flip chip are disposed on one main surface 11a of the wiring substrate 11, and the wafer components 12a to 12c of the wafer capacitor or the like are disposed on the other main surface 11b.
為了使模組2小型化(使配線基板11之構裝面積變小)，在配線基板11之兩主面11a,11b配置構裝零件較有效。又，如圖6所示之習 知技術，藉由將半導體基板9之下面9a與連接端子8一起研磨等而高度變低，對謀求模組2之小型化亦有效。然而，例如，若在配線基板11之相同主面上構裝半導體基板9與各晶片零件12a~12c，則不易研磨半導體基板9之下面9a而謀求使模組2高度變低。其原因在於，若藉由研磨晶片電容器或晶片電感器即各晶片零件12a~12c而研削，則會有特性劣化之虞。因此，若以上述方式構成，則無法使半導體基板9離該相同主面之高度較構裝在相同主面上之各晶片零件12a~12c之高度低。 In order to reduce the size of the module 2 (to reduce the mounting area of the wiring board 11), it is effective to arrange the components on the both main surfaces 11a and 11b of the wiring board 11. Also, as shown in Figure 6, In the prior art, the lower surface 9a of the semiconductor substrate 9 and the connection terminal 8 are polished together to be highly lowered, which is also effective for miniaturizing the module 2. However, for example, when the semiconductor substrate 9 and the respective wafer components 12a to 12c are formed on the same main surface of the wiring substrate 11, the lower surface 9a of the semiconductor substrate 9 is less likely to be polished, and the height of the module 2 is lowered. The reason for this is that if the wafer capacitors or the wafer inductors, that is, the wafer components 12a to 12c, are ground and ground, the characteristics are deteriorated. Therefore, according to the above configuration, the height of the semiconductor substrate 9 from the same main surface cannot be made lower than the height of each of the wafer components 12a to 12c mounted on the same main surface.
因此，本實施形態中，如上述，在配線基板11之一主面11a僅配置即使研磨該下面9a特性亦不會劣化之覆晶構裝之半導體基板9與連接端子8，且在另一主面11b配置晶片電容器或晶片電感器等之各晶片零件12a~12c，將配線基板11之一主面11a之樹脂層13a之表面與半導體基板9及連接端子8一起研磨或研削，藉此成為可謀求模組2高度變低之模組構成。 Therefore, in the present embodiment, as described above, only one of the main surface 11a of the wiring board 11 is provided with the flip-chip semiconductor substrate 9 and the connection terminal 8 which are not deteriorated even if the lower surface 9a is polished, and the other main Each of the wafer components 12a to 12c such as a wafer capacitor or a chip inductor is placed on the surface 11b, and the surface of the resin layer 13a of one of the main surfaces 11a of the wiring substrate 11 is ground or ground together with the semiconductor substrate 9 and the connection terminal 8, thereby making it possible to The module structure of the module 2 is lowered in height.
又，以離配線基板11之一主面11a之高度最高之半導體基板9(或連接端子8)之高度Ht較離配線基板11之另一主面11b之高度最低之晶片零件12a之高度H0低之方式研磨或研削半導體基板9(或連接端子8)，因此可確實地謀求模組2高度變低。 Further, the height Ht to one of the wiring board 11 from the main surface of the semiconductor substrate 9 of the maximum height (or terminals 8) of the lowest 11a of the wiring board than from the other main surface 11 of the part 11b of the wafer height of the height H 0 12a Since the semiconductor substrate 9 (or the connection terminal 8) is ground or ground in a low manner, the height of the module 2 can be surely lowered.
又，半導體基板9之下面9a從樹脂層13之表面露出，因此與半導體基板9之下面9a被樹脂層13a被覆之模組構成相較，在母基板3構裝有模組2時，半導體基板9之下面9a與形成在母基板3之面狀之接地電極5之距離變短，藉此，使半導體基板9之屏蔽特性提升。又，若半導體基板9之下面9a與母基板3之接地電極5之距離變短，則容易使從模組 2產生之熱透過接地電極5散熱，可提升模組2之散熱特性。 Further, since the lower surface 9a of the semiconductor substrate 9 is exposed from the surface of the resin layer 13, the semiconductor substrate is formed when the module 2 is mounted on the mother substrate 3 in comparison with the module structure in which the lower surface 9a of the semiconductor substrate 9 is covered with the resin layer 13a. The distance between the lower surface 9a of the 9 and the ground electrode 5 formed on the surface of the mother substrate 3 is shortened, whereby the shielding property of the semiconductor substrate 9 is improved. Further, if the distance between the lower surface 9a of the semiconductor substrate 9 and the ground electrode 5 of the mother substrate 3 is shortened, it is easy to make the slave module 2 The generated heat is dissipated through the ground electrode 5 to improve the heat dissipation characteristics of the module 2.
又，藉由研磨或研削樹脂層13a之表面，能使連接於母基板3之接地電極5之連接端子8之長度(離配線基板11之一主面11a之高度)變短，因此可降低起因於連接端子8之寄生電感，藉此可謀求接地之強化。 Further, by polishing or grinding the surface of the resin layer 13a, the length of the connection terminal 8 connected to the ground electrode 5 of the mother substrate 3 (the height from one main surface 11a of the wiring substrate 11) can be shortened, so that the cause can be reduced. The parasitic inductance of the connection terminal 8 can thereby enhance the grounding.
又，如上述，若研磨配線基板11之一主面11a之樹脂層13a，則形成樹脂層13a之樹脂之量較另一主面11b之樹脂層13b之樹脂之量少，因此在兩樹脂層13a,13b分別產生之收縮應力失去均衡，會有配線基板11彎曲之虞，但在較形成兩樹脂層13a,13b之樹脂硬之半導體基板9使用構裝在配線基板11之兩主面11a,11b之各構裝零件9,12a~12c中之俯視下面積(橫剖面積)最大者，因此可抑制因上述兩樹脂層13a,13b之收縮應力失去均衡產生之配線基板11之彎曲。 Further, as described above, when the resin layer 13a of one main surface 11a of the wiring substrate 11 is polished, the amount of the resin forming the resin layer 13a is smaller than the amount of the resin of the resin layer 13b of the other main surface 11b, so that the resin layer is present in both resin layers. The shrinkage stresses generated by the respective 13a and 13b are unbalanced, and the wiring substrate 11 is bent. However, the resin-hardened semiconductor substrate 9 having the two resin layers 13a and 13b is formed on the two main faces 11a of the wiring substrate 11, In the respective components 9 and 12a to 12c of the 11b, the area (cross-sectional area) in the plan view is the largest, so that the bending of the wiring substrate 11 caused by the loss of the contraction stress of the two resin layers 13a and 13b can be suppressed.
又，形成樹脂層13b之樹脂係使用線膨脹係數較形成樹脂層13a之樹脂小者，因此可進一步抑制配線基板11之彎曲。 Further, since the resin forming the resin layer 13b is smaller than the resin forming the resin layer 13a, the bending of the wiring substrate 11 can be further suppressed.
又，在配線基板11之一主面11a側，由於以半導體基板9之下面9a側之端部與連接端子8之下端部露出之方式形成被覆半導體基板9及連接端子8分別之側面之一部分之樹脂層13a，因此包含熱傳導率較樹脂層13a之樹脂高之半導體基板9之下面9a之下端部露出，藉此，與以往般僅半導體基板9之下面9a露出之模組相較，可謀求模組2之散熱特性之提升。 Further, on one side of the main surface 11a of the wiring board 11, one end portion of the side surface of the semiconductor substrate 9 and the connection terminal 8 is formed so that the end portion on the lower surface 9a side of the semiconductor substrate 9 and the lower end portion of the connection terminal 8 are exposed. Since the resin layer 13a is exposed, the lower end portion of the lower surface 9a of the semiconductor substrate 9 having a higher thermal conductivity than the resin of the resin layer 13a is exposed, whereby the module can be formed as compared with the conventional module in which the lower surface 9a of the semiconductor substrate 9 is exposed. The improvement of the heat dissipation characteristics of Group 2.
又，如圖2所示，由於樹脂層13a表面與半導體基板9(側面9b)之接觸部16，從半導體基板9側面9b在該半導體基板9之下面9a側之端緣朝向樹脂層13a形成為展開之圓角狀，因此施加於樹脂層13a表面與半 導體基板9之接觸部16之應力係藉由形成為圓角狀之樹脂分散，可防止樹脂層13a之樹脂從半導體基板9剝離。 Further, as shown in FIG. 2, the contact portion 16 of the surface of the resin layer 13a and the semiconductor substrate 9 (side surface 9b) is formed from the side edge 9b of the semiconductor substrate 9 on the side of the lower surface 9a side of the semiconductor substrate 9 toward the resin layer 13a. Expanded rounded shape, thus applied to the surface and half of the resin layer 13a The stress of the contact portion 16 of the conductor substrate 9 is dispersed by the resin formed in a rounded shape, and the resin of the resin layer 13a can be prevented from being peeled off from the semiconductor substrate 9.
又，如圖2所示，半導體基板9從樹脂層13a表面突出之部分之角部9c係藉由研磨或研削去角，因此可抑制半導體基板9之裂開或破裂。 Further, as shown in FIG. 2, the corner portion 9c of the portion of the semiconductor substrate 9 that protrudes from the surface of the resin layer 13a is polished or ground, so that cracking or cracking of the semiconductor substrate 9 can be suppressed.
又，由於在半導體基板9之下面9a形成有凹凸，因此熱傳導率高之半導體基板9之表面積(從樹脂層13a露出之部分)增加，可提升模組2之散熱特性。 Further, since the unevenness is formed on the lower surface 9a of the semiconductor substrate 9, the surface area of the semiconductor substrate 9 having a high thermal conductivity (the portion exposed from the resin layer 13a) is increased, and the heat dissipation characteristics of the module 2 can be improved.
又，在從樹脂層13a露出之半導體基板9之下面9a之至少一部分形成有金屬膜10，因此，藉由熱傳導率較半導體基板9高之金屬膜10，使模組2之散熱特性提升。又，藉由將形成在半導體基板9之下面9a之金屬膜10利用為與母基板3之連接用之電極，能以連接端子8與金屬膜10進行母基板3與模組2之連接，可謀求母基板3與模組2之連接強度之提升。 Further, since the metal film 10 is formed on at least a part of the lower surface 9a of the semiconductor substrate 9 exposed from the resin layer 13a, the heat dissipation characteristics of the module 2 are improved by the metal film 10 having a higher thermal conductivity than the semiconductor substrate 9. Further, by using the metal film 10 formed on the lower surface 9a of the semiconductor substrate 9 as an electrode for connection to the mother substrate 3, the connection between the mother substrate 3 and the module 2 can be performed by the connection terminal 8 and the metal film 10. The connection strength between the mother substrate 3 and the module 2 is improved.
又，在形成在半導體基板9之下面9a之金屬膜10之表面形成有凹凸，因此金屬膜10之表面積增加，可進一步提升模組2之散熱特性。又，將金屬膜10利用為與母基板3之連接用之電極之情形，連接面積亦增加，因此可謀求模組2與母基板3之連接強度之提升。 Further, since irregularities are formed on the surface of the metal film 10 formed on the lower surface 9a of the semiconductor substrate 9, the surface area of the metal film 10 is increased, and the heat dissipation characteristics of the module 2 can be further improved. Moreover, when the metal film 10 is used as an electrode for connection to the mother substrate 3, the connection area is also increased, so that the connection strength between the module 2 and the mother substrate 3 can be improved.
又，藉由半導體基板9之下面9a側之端部與連接端子8之下端部從樹脂層13a表面突出，將模組2構裝在母基板3時之底填樹脂層4與模組2之接觸面積增加，因此母基板3與模組2之連接可靠性提升。 Further, the end portion of the lower surface 9a of the semiconductor substrate 9 and the lower end portion of the connection terminal 8 protrude from the surface of the resin layer 13a, and the underfill resin layer 4 and the module 2 are assembled when the module 2 is mounted on the mother substrate 3. As the contact area increases, the reliability of the connection between the mother substrate 3 and the module 2 is improved.
又，金屬膜10係以Ni/Au膜形成，因此可提升藉由焊料連 接模組2與母基板3時之焊料之濕潤性。 Moreover, the metal film 10 is formed of a Ni/Au film, so that it can be improved by soldering The wettability of the solder when the module 2 and the mother substrate 3 are connected.
又，藉由在半導體基板9之下面9a形成金屬膜10，半導體基板9之下面9a受到保護，因此可抑制半導體基板9因外部應力等而破損。 Moreover, since the metal film 10 is formed on the lower surface 9a of the semiconductor substrate 9, the lower surface 9a of the semiconductor substrate 9 is protected, so that the semiconductor substrate 9 can be prevented from being damaged by external stress or the like.
此外，本發明並不限於上述各實施形態，只要不脫離其趣旨，除了上述以外可進行各種變更。 The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.
例如，上述各實施形態中，覆晶構裝在配線基板11之一主面11a之半導體基板9為複數個亦可。又，半導體基板9在俯視下之面積較其他構裝零件之任一者之面積小亦可。此外，若為構裝後之高度較研磨或研削後之半導體基板9之高度低之構裝零件，則配置在配線基板11之一主面11a亦可。亦即，只要為在配線基板11之一主面11a構裝或配置可研磨或研削該下面9a之半導體基板9之構成即可，此外，為了縮小配線基板11構裝面積，適當地設計各構裝零件之配置即可。 For example, in each of the above embodiments, the number of the semiconductor substrates 9 laminated on one main surface 11a of the wiring substrate 11 may be plural. Further, the area of the semiconductor substrate 9 in a plan view may be smaller than the area of any of the other components. Further, the component which is lower in height after the mounting and the height of the semiconductor substrate 9 after polishing or grinding may be disposed on one main surface 11a of the wiring substrate 11. In other words, the semiconductor substrate 9 on which the lower surface 9a can be polished or ground may be disposed or disposed on one main surface 11a of the wiring substrate 11. Further, in order to reduce the layout area of the wiring substrate 11, the structures are appropriately designed. The configuration of the loaded parts is sufficient.
又，在配線基板11之另一主面11b僅構裝晶片電容器或晶片電感器等之晶片零件12a~12c，但在另一主面11b構裝與構裝在一主面11a之半導體基板9相同或不同之其他半導體基板9亦可。 Further, only the wafer components 12a to 12c such as a wafer capacitor or a chip inductor are mounted on the other main surface 11b of the wiring substrate 11, but the semiconductor substrate 9 is mounted and mounted on the main surface 11a on the other main surface 11b. Other semiconductor substrates 9 which are the same or different may also be used.
又，形成在配線基板11之一主面11a之連接端子8之個數為任意亦可，又，將連接端子8配置在配線基板11之另一主面11b亦可。又，連接端子8並不一定要配置在配線基板11之一主面11a。亦即，連接端子8與半導體基板9配置在配線基板11之不同主面亦可。 Further, the number of the connection terminals 8 formed on one main surface 11a of the wiring substrate 11 may be any, and the connection terminal 8 may be disposed on the other main surface 11b of the wiring substrate 11. Further, the connection terminal 8 does not have to be disposed on one main surface 11a of the wiring substrate 11. In other words, the connection terminal 8 and the semiconductor substrate 9 may be disposed on different main faces of the wiring substrate 11.
又，在樹脂層13a、樹脂層13b之至少一方形成由金屬膜構成之保護膜亦可。 Further, a protective film made of a metal film may be formed on at least one of the resin layer 13a and the resin layer 13b.
又，不設置樹脂層13b亦可。 Further, the resin layer 13b may not be provided.
又，上述各實施形態中，為在配線基板11之另一主面11b未構裝各晶片零件12a~12c之構成亦可。 Further, in each of the above embodiments, the respective wafer components 12a to 12c may not be mounted on the other main surface 11b of the wiring board 11.
Claims (11)
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| JP2018120823A (en) * | 2017-01-27 | 2018-08-02 | 株式会社ジャパンディスプレイ | Method for manufacturing display panel |
| WO2018168653A1 (en) | 2017-03-14 | 2018-09-20 | 株式会社村田製作所 | High frequency module |
| US10439586B2 (en) | 2017-07-19 | 2019-10-08 | Murata Manufacturing Co., Ltd. | Electronic module having a filler in a sealing resin |
| US11387400B2 (en) | 2017-07-19 | 2022-07-12 | Murata Manufacturing Co., Ltd. | Electronic module with sealing resin |
| JP6981537B2 (en) | 2018-03-20 | 2021-12-15 | 株式会社村田製作所 | High frequency module |
| CN213936168U (en) * | 2018-05-08 | 2021-08-10 | 株式会社村田制作所 | High frequency module |
| JP2020120185A (en) | 2019-01-21 | 2020-08-06 | 株式会社村田製作所 | Front-end module and communication device |
| WO2022220000A1 (en) * | 2021-04-16 | 2022-10-20 | 株式会社村田製作所 | High-frequency module and communication device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2003007931A (en) * | 2001-06-20 | 2003-01-10 | Sony Corp | Semiconductor device and manufacturing method therefor |
| JP2005203633A (en) * | 2004-01-16 | 2005-07-28 | Matsushita Electric Ind Co Ltd | Semiconductor device, semiconductor device mount and method for manufacturing the semiconductor device |
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| JP3432749B2 (en) * | 1998-07-23 | 2003-08-04 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| JP2005175113A (en) * | 2003-12-10 | 2005-06-30 | Fdk Corp | Printed wiring board for mounting flip chip |
| JP2010080699A (en) * | 2008-09-26 | 2010-04-08 | Panasonic Corp | High-frequency module and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003007931A (en) * | 2001-06-20 | 2003-01-10 | Sony Corp | Semiconductor device and manufacturing method therefor |
| JP2005203633A (en) * | 2004-01-16 | 2005-07-28 | Matsushita Electric Ind Co Ltd | Semiconductor device, semiconductor device mount and method for manufacturing the semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201405726A (en) | 2014-02-01 |
| WO2014017159A1 (en) | 2014-01-30 |
| JP6282589B2 (en) | 2018-02-21 |
| JPWO2014017159A1 (en) | 2016-07-07 |
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