TWI635391B - Flash memory and management method thereof - Google Patents

Abstract

Flash memory and its management method. The management method includes: setting a buffer so that the buffer stores a plurality of written data, wherein each written data has a unit size; and when the total size of the written data stored in the buffer reaches a preset critical value, The data written in the buffer is written to one of the plurality of physical memory pages of the flash memory.

Description

Flash memory and management method thereof

The invention relates to a flash memory and a memory management method thereof, and in particular to a memory management method for reducing a write amplification phenomenon.

In the performance evaluation of flash memory, random access to flash memory is of certain importance in the evaluation indicators. Among them, the write amplification phenomenon and the integration of memory space are already flash memory. There have been important issues in use for a long time.

However, regarding the write amplification phenomenon, the factors that cause the write amplification phenomenon mainly include two: one is that the size of the written data is not aligned with the mapping method adopted by the memory conversion layer, and the other is to consider the life and space availability Memory space integration. The foregoing two ultimately result in repeated writing operations on the flash memory, and then affect the writing performance. In addition, because random writing has certain characteristics, the unit size of the characteristic data of the written data is mostly 4K. At this time, when the memory conversion layer uses page or block mapping (size greater than 4K), the problem of write amplification is even more serious. As obvious.

The invention provides a flash memory and a management method thereof, which can effectively reduce the write amplification phenomenon.

The flash memory management method of the present invention includes: setting a buffer so that the buffer stores a plurality of written data, wherein each written data has a unit size; and calculating the total size of the written data stored in the buffer When the preset threshold is reached, the data written in the buffer is written into one of the plurality of physical memory pages of the flash memory.

In an embodiment of the present invention, the flash memory management method further includes: establishing a plurality of partial page address mapping tables corresponding to a plurality of logical page addresses, respectively. The partial page address mapping table includes a plurality of partial area information. Each partial area information is divided into a plurality of section fields, and each section field includes a mapping entity page address and a mapping entity memory group.

The flash memory of the present invention includes a memory cell module and a controller. The memory cell module includes a plurality of physical memory groups. Each physical memory group includes a plurality of physical memory pages. The controller is coupled to the memory cell module for: setting a buffer so that the buffer stores a plurality of written data, each of which has a unit size; and calculating a total of the written data stored in the buffer When the size reaches a predetermined threshold, the data written in the buffer is written into one of the plurality of physical memory pages of the flash memory.

Based on the above, the present invention provides a buffer, and write data having a unit size is written into the buffer first, and when the total size of the data in the buffer reaches a preset critical value, the data in the buffer is Each written data is written into the physical memory page. In this way, the write amplification phenomenon of the flash memory can be reduced, which effectively improves the use efficiency of the flash memory.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a flowchart of a flash memory management method according to an embodiment of the present invention. In step S110, a buffer is set, and the buffer is used to store a plurality of written data. Each of the written data has a unit size. Here, the buffer has a data storage capacity larger than a unit size. Please refer to FIG. 2 for a schematic diagram of the flash memory according to the embodiment of the present invention. In FIG. 2, the buffer 210 has a data storage capacity larger than a unit size, and receives the written data WD and temporarily stores the written data WD in the buffer 210. For example, the unit size of each write data WD is 4K, and the data storage capacity of the buffer 210 can be an integer multiple (for example, 4 times) of the unit size of each write data WD, that is, In other words, the data storage capacity of the buffer 210 can be 16K. Therefore, the buffer 210 can store multiple write data.

In step S120, the total size of the written data WD1 to WD4 stored in the buffer 210 is calculated, and when the total size of the written data WD1 to WD4 in the buffer 210 reaches a preset critical value, The writing data WD1 to WD4 in the buffer 210 are written into one of the plurality of physical memory pages 221 of the flash memory 220. Specifically, the capacity of a single physical memory page in the flash memory 220 may be equal to N times the unit size of a single write data WD, where N is an integer greater than 1. The preset critical value at this time can be set to N times the unit size. In other words, when there are N pieces of written data stored in the buffer 210, the total size in the buffer 210 can reach a preset critical value. At this time, the written data WD1 stored in the buffer 210 can be stored. ~ WD4 is written to the physical memory page 221 at one time.

For example, when the storage capacity of the physical memory page 221 is 16K, and the unit size of the write data WD is 4K, the default threshold can be set to 16K, and when the buffer 210 is filled with 4 write data When WD1 ~ WD4, write data WD1 ~ WD4 can be written into the physical memory page 221.

From the above description, it can be known that the proportion of the 16K memory area in the physical memory page 221 for storing written data can be maximized. In contrast, the write magnification can be effectively reduced and the flash memory 220 can be improved. Performance.

In addition, the data stored in a single physical memory page can be divided into several paragraphs. Taking the 16K physical memory page 221 as an example, it can include 4 segments of written data (each written data unit size is 4K ).

It is worth mentioning that the logical addresses corresponding to the plurality of write data WD1-WD4 stored in the buffer 210 may be continuous, may be partially continuous, or may be discontinuous and distributed in random numbers.

Regarding the address mapping, please refer to FIG. 3. FIG. 3 is a schematic diagram of a flash memory mapping method according to an embodiment of the present invention. Taking the unit size of each write data as 4K as an example, the establishment of the mapping relationship between the logical address and the physical address can be called a 4K partial page mapping write operation, and it is compared with the known full page. The mapping is different.

In FIG. 3, an embodiment of the present invention provides a logical page address mapping table 301. The logical page address mapping table 301 provides information about a page address mapping of a plurality of logical page addresses. The logical page address mapping table 301 has a plurality of fields 3011 and 3012. Fields 3011 and 3012 correspond to different logical page addresses. The field write flag F1 is recorded in field 3011, and because the field write flag F1 recorded in field 3011 is equal to 0, it indicates that the logical page address corresponding to field 3011 is mapped to the physical page through the full page address mapping. Address mapping. Therefore, the field 3011 also records the mapping entity memory group corresponding to the entity memory group L through the sub-field MT1. In contrast, the partial write flag F2 recorded in field 3012, and because the partial write flag F2 recorded in field 3012 is equal to 1, it indicates that the logical page address corresponding to field 3012 is mapped to the entity through partial address mapping. Page addresses are mapped. Therefore, the field 3012 also uses the partial page address mapping table corresponding to the sub-field MT2 record as the partial page address mapping table A.

The embodiment of the present invention further provides a partial page address mapping table. According to the partial page address mapping table A 302 shown in FIG. 3, the partial page address mapping table A 302 includes section fields SE1 to SE4. Each section field includes a record mapping entity page address, a mapping segment, and a mapping entity memory group. Taking section field SE1 as an example, the mapped entity memory group 3021 recorded in section field SE1 is entity memory group M, and the mapped entity page address 3022 recorded in section field SE1 is 2 (indicating page 2), and the section The mapping segment 3023 recorded in the field SE1 is 1 (indicating the first segment data therein).

According to the content recorded in the section fields SE1 ~ SE4, the data in the logical page address corresponding to the field 3012 can be obtained, which are respectively stored in: (1) the first segment of the second page in the physical memory group M; (2) The second segment on page 2 in the physical memory group M; (3) The second segment on page 0 in the physical memory group N; (4) The first page on page 1 in the physical memory group N 4 segments.

Referring to FIG. 4, FIG. 4 is a schematic diagram of the page address mapping and the content of the physical memory group according to the embodiment of FIG. 3 of the present invention. Among them, according to the field 3011, the data in the logical page address corresponding to the field 3011 can be learned from the first page page1 in the physical memory group L through the full page address mapping. The four segmented data in the logical page address corresponding to field 3012 are stored in the first segment (data 401) of page 2 of page 2 of the physical memory group M respectively; page 2 of page 2 of the physical memory group M Subsection 2 (Source 402); Subsection 2 (Page 403) of page 0 of the physical memory group N; Subsection 4 (Page 404) of page 1 of the physical memory group N .

Please refer to FIG. 5 below, which illustrates a schematic diagram of a flash memory according to an embodiment of the present invention. The flash memory 500 includes a memory cell module 520 and a controller 510. The memory cell module 520 includes a plurality of memory cells, and the memory cells are arranged in an array manner. The controller 510 is coupled to the memory cell module 520. The controller 510 can set a buffer. In the data writing operation, the buffer is used to store write data having a unit size, and when the total size of the write data stored in the buffer reaches a preset threshold, the data in the buffer is written. Data is written to one of the many physical memory pages of flash memory. The buffer can be set in a cache memory or other data storage well known to those with ordinary knowledge in the art, and there is no specific limitation.

In addition, the controller 510 can perform various management actions on the memory cell module 520. Regarding the controller 510 executing the page address mapping of the memory cell module 520 and determining whether the physical page address is valid, the related sections are described in detail in the foregoing multiple embodiments and implementations. I will not repeat them here.

In summary, the present invention temporarily stores multiple written data with a unit size by setting a buffer, and the total size of the written data in the buffer is close to (or equal to) the storage space of a physical memory page. At that time, all the written data in the buffer is written into the physical memory page. In this way, the situation of write amplification can be effectively controlled, and the use efficiency of the flash memory can be improved.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

S110-S120: Flash memory management step 220: Flash memory 210: Buffer WD, WD1 ~ WD4: Write data 221: Physical memory page 301: Logical page address mapping table 3011, 3012: Field SE1 ~ SE4: Section field 401 ~ 404: Data 3021 ~ 3023: Map physical page address F1 ~ F2: Partial write flags MT1, MT2: Sub-field mapping physical memory group Page0-Page2: Physical page address 500: Flash memory 520: memory cell module 510: controller

FIG. 1 is a flowchart of a flash memory management method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a flash memory according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a flash memory mapping method according to an embodiment of the present invention. FIG. 4 is a schematic diagram of the page address mapping and the content of the physical memory group according to the embodiment of FIG. 3 of the present invention. FIG. 5 is a schematic diagram of a flash memory according to an embodiment of the invention.

Claims (8)

A flash memory management method includes: setting a buffer area so that the buffer area stores a plurality of write data, wherein each write data has a unit size; and calculating the writes stored in the buffer area When the total size of the data reaches a preset threshold, the written data in the buffer is written into one of the plurality of physical memory pages of the flash memory. The flash memory management method according to item 1 of the scope of the patent application, wherein the written data corresponds to a random majority of logical addresses or a continuous majority of logical addresses. The flash memory management method according to item 1 of the scope of patent application, further comprising: establishing a plurality of partial page address mapping tables corresponding to a plurality of logical page addresses, wherein each of the partial page bits The address mapping table includes a plurality of section fields, and each section field includes a mapped entity page address, a mapped segment, and a mapped entity memory group. According to the flash memory management method described in item 3 of the scope of patent application, the method further includes: setting up a logical page address mapping table corresponding to some partial page address mapping tables, wherein the logical page address mapping table There are a plurality of fields corresponding to a plurality of logical page addresses, respectively, each of which records a part of a write flag and a corresponding part of a page address mapping table. A flash memory includes: a memory cell module including a plurality of physical memory groups, each of which includes a plurality of physical memory pages; and a controller coupled to the memory cell module for: setting A buffer, so that the buffer stores a plurality of written data, each of which has a unit size; and when the total size of the written data stored in the buffer reaches a preset critical value, The write data in the buffer is written into one of a plurality of physical memory pages of the flash memory. The flash memory according to item 5 of the scope of patent application, wherein the written data corresponds to a random majority of logical addresses or a continuous majority of logical addresses. According to the flash memory in item 5 of the scope of patent application, the controller further establishes a plurality of partial page address mapping tables corresponding to a plurality of logical page addresses, wherein each of the partial page address mappings The table includes a plurality of section fields, each of which includes a mapped entity page address, a mapped segment, and a mapped entity memory group. The flash memory according to item 7 of the scope of the patent application, wherein the controller further sets a logical page address mapping table corresponding to some partial page address mapping tables, wherein the logical page address mapping table has Corresponding to a plurality of fields of a plurality of logical page addresses, each of which records a part of a write flag and a corresponding part of a page address mapping table.