TWI559137B - Solid storage device with mixed storage mode - Google Patents

Description

Solid state storage device with mixed storage mode

The present invention relates to a solid state storage device, and more particularly to a solid state storage device that implements two or more potential storage modes in the same flash memory.

According to the maturity of Solid-State Drive (SSD) technology, it gradually replaces the Hard Disk Drive (HDD). The solid-state storage device has the data access speed compared with the conventional hard disk device. Fast, low power consumption, light weight and so on.

Moreover, the solid state storage device mainly uses a floating gate transistor of a flash memory to store data bit data, and can be divided into single-level cells according to the number of data bits that can be stored in each transistor (Single) -Level Cell, SLC) and Multi-Level Cell (MLC) and other potential storage modes. When the single-stage unit is implemented, there are only two kinds of voltage changes, that is, each of the transistors only stores a single data bit, and when the multi-level unit is implemented, it can be used for each of the units. Two to three data bits are stored in the crystal. Therefore, when the multi-level cell implementation is used, the number of data bits that can be stored in each of the transistors is several times that of a single-stage cell, and the flash memory is implemented in a multi-level cell. The cost is relatively low, but this type of implementation has a relatively slow response rate and a low lifetime in data access. However, the flash memory implemented in a single-stage unit has the advantages of high stability, relatively fast response speed of data access, and long service life, but the capacity density of the data that can be stored is low. It makes its manufacturing cost relatively high.

Accordingly, various manufacturers have proposed a hybrid solid-state storage device including a single-stage unit type potential storage mode and a multi-stage unit type potential storage mode, as disclosed in the Patent No. I385517 of the Republic of China, which discloses a storage device. The purpose of generating a hybrid storage is to use a first flash memory and a second flash memory different from the first flash memory, but the patent requires two different kinds of purchases. The flash memory makes the manufacturing cost still limited by the price of the flash memory implemented in the single-stage cell potential storage mode, which cannot be effectively reduced.

The main object of the present invention is to solve the problem that the conventional solid-state storage device can only implement the data stability and the data storage amount generated by the single potential storage mode.

To achieve the above object, the present invention provides a solid state storage device having a mixed storage mode, the solid state storage device comprising a flash memory and a data processing module. The flash memory includes a first storage magnetic area for storing data in a first potential storage mode and a second storage magnetic field for storing data in a second potential storage mode different from the first potential storage mode. The first storage magnetic area includes M data blocks, and the second storage magnetic area includes N data blocks, each of the data blocks corresponding to a physical block address and a logical block position. Address, the physical block address of the first storage magnetic zone is P ₀ to P _M-1 , and the logical block address is L ₀ to L _M-1 , and the physical block position of the second storage magnetic zone The address is P _M to P _M+N-1 , and the logical block address is L _M to L _M+N-1 . The data processing module is coupled to the flash memory information, and has a data processing mode that accepts an instruction and interprets the logical block address included in the instruction and performs an instruction action on the corresponding physical block address.

In an embodiment, the first potential storage mode is a single-stage unit type, and the second potential storage mode is a multi-level unit type. Further, the data processing module has a data indicating that the logical block address included in the instruction is L ₀ to L _M-1 , and a potential modulation command is added to the instruction to change the original potential storage mode of the instruction. Modulation mode.

In an embodiment, the first potential storage mode is a multi-level cell type, and the second potential storage mode is a single-stage cell type. Further, the data processing module has a function of determining that the logical block address included in the instruction is L _M to L _M+N-1 , adding a potential modulation command to the instruction, and changing the original potential storage mode of the instruction. Data modulation mode.

In one embodiment, the data storage capacity of the first storage magnetic zone is different from the data storage capacity of the second storage magnetic domain.

In an embodiment, the data processing module includes a physical block address corresponding to the first storage magnetic zone as P ₀ to P _M-1 and logical block addresses L ₀ to L _M-1 . a first mapping table, and a physical block address corresponding to the second storage magnetic zone, P _M to P _M+N-1 and a logical block address L _M to L _M+N-1 The second pair is on the table.

In one embodiment, the flash memory further includes a third storage magnetic region for storing data in a third potential storage mode different from the first potential storage mode and the second potential storage mode, the third storage area. The magnetic zone includes R data blocks, the physical block address of the third storage magnetic zone is P _N to P _N+R-1 , and the logical block address is L _N to L _N+R-1 . Further, the data processing module includes a first image recording a physical block address corresponding to the first storage magnetic zone as P ₀ to P _M-1 and a logical block address L ₀ to L _M-1 For the table, a second mapping table for recording the physical block address corresponding to the second storage magnetic zone to P _M to P _M+N-1 and the logical block address L _M to L _M+N-1 And a third mapping table recording the physical block addresses corresponding to the third storage magnetic zone as P _N to P _N+R-1 and the logical block addresses L _N to L _N+R-1 .

In one embodiment, the data processing module has a number of times of eliminating each of the data blocks of the first storage magnetic zone and the second storage magnetic area when the instruction is a data write operation. The average write algorithm for the average write of the recorded block.

Through the above embodiments of the present invention, the present invention has the following features: the present invention is implemented by the flash memory of the same transistor type, and the flash memory is divided into the first storage magnetic region and the second storage. The magnetic zone is such that the first storage magnetic zone is different from the potential storage mode used by the second storage magnetic zone, thereby providing a solid state storage device with high stability and high data storage capacity.

The detailed description and technical contents of the present invention will now be described as follows:

Referring to FIG. 1 and FIG. 2 , the solid state storage device 100 of the present invention has a flash memory 1 and a data processing module 2 connected to the flash memory 1 . Further, the flash memory 1 of the present invention may be composed of a plurality of wafers, each of which has the same type of transistor. In other words, the flash memory 1 of the present invention has only a single potential storage mode, such as a Multi-Level Cell (MLC), before it is implemented. Moreover, the flash memory 1 has a plurality of data blocks 11, each of which corresponds to a physical block address (PBA) and a logical block address (LBA). Further, the present invention divides the flash memory 1 into a first storage magnetic area 12 and a second storage magnetic area 13 by using the logical block address, wherein the first storage magnetic area 12 includes M data blocks 11, the corresponding physical block addresses are P ₀ to P _M-1 , the logical block addresses are L ₀ to L _M-1 , and the second storage magnetic region 13 includes There are N data blocks 11, and the corresponding physical block address is P _M to P _M+N-1 , and the logical block address is L _M to L _M+N-1 .

It can be seen from the above that the flash memory 1 of the present invention has only a single potential storage mode when not implemented. However, in the implementation process, the present invention changes the potential storage mode of one of the storage magnetic regions through the data processing module 2 to simulate Another potential storage mode recording data, more specifically, the first storage magnetic region 12 of the present invention stores data in a first potential storage mode, and the second storage magnetic region 13 is different from the first potential. The second potential storage mode of the storage mode stores data. In an embodiment, the first potential storage mode is a single-level cell (SLC), and the second potential storage mode is a multi-level cell. However, the present invention is not limited thereto, and the first potential storage mode may be a multi-stage unit type, and the second potential storage mode is a single-stage unit type. Moreover, after the flash memory 1 of the present invention distinguishes the first storage magnetic region 12 and the second storage magnetic region 13, the potential storage mode of the first storage magnetic region 12 and the second storage magnetic region 13 are different. The data storage capacity of the first storage magnetic region 12 of the present invention is different from the data storage capacity of the second storage magnetic region 13. For example, when the first potential storage mode of the first storage magnetic region 12 is a single-stage unit type, each of the transistors in the data storage block 11 in the first storage magnetic region 12 will only The data of one bit is recorded such that the data storage capacity of the first storage magnetic zone 12 is smaller than the data storage capacity of the second storage magnetic zone 13 implemented by the multi-level cell type as the second potential storage mode.

The data processing module 2 of the present invention is connected to the flash memory 1 and has an instruction D1 and interprets the logical block address included in the instruction to correspond to the physical block address. The data processing mode for executing the instruction action. More specifically, the solid state storage device 100 of the present invention can be connected to a computer device (such as a computer) and cause the computer device 3 to perform data writing or reading, and the instruction D1 is referred to in the present invention. When the computer device 3 issues the command D1 to the solid-state storage device 100, the data processing module 2 receives the command D1, and then interprets the data of the instruction D1 that is required to execute the action. The logical block address, and the corresponding data is read according to the logical block address. Further, it can be known from the foregoing that the first potential storage mode of the present invention can be implemented in a multi-level unit manner. Therefore, the data processing module 2 further has a judgment that the logical block address included in the instruction D1 is L. _{When 0} to L _M-1 , a potential modulation command is added to the command D1 to change the data modulation mode of the original potential storage mode of the command D1. In addition, in the embodiment, when the second potential storage mode is implemented in a multi-level cell, the data modulation mode of the data processing module 2 is for the command D1. Implemented when the logical block address is L _M to L _M+N-1 . According to the invention, the data processing module 2 has the data modulation mode to simulate the potential storage mode of the original multi-level cell into a single-stage cell potential storage mode. Moreover, the potential modulation command can be a flag command or a page command.

In addition, referring to FIG. 2, the data processing module 2 of the present invention further includes a record of the physical block address corresponding to the first storage magnetic area 12 as P ₀ to P _M-1 and the logical block. The first mapping table T1 of the addresses L ₀ to L _M-1 , and the physical block address corresponding to the recording of the second storage magnetic region 13 are P _M to P _M+N-1 and the logical region The second mapping table T2 of the block address L _M to L _M+N-1 . Thereby, the data processing module 2 can quickly associate each of the logical block addresses with each of the physical block addresses by the first mapping table T1 and the second mapping table T2. Moreover, the data processing module 2 further includes a number of times of erasing the data block 11 according to the first storage magnetic area 12 and the second storage magnetic area 13 when the instruction D1 is a write data operation. The average write algorithm for the average write of the recordable block.

In addition, referring to FIG. 3, in an embodiment of the present invention, the flash memory 1 includes, in addition to the first storage magnetic region 12 and the second storage magnetic region 13, a third storage magnetic region 14 storing data corresponding to the first potential storage mode and the third potential storage mode of the second potential storage mode, the third storage magnetic region 14 including R data blocks 11 The physical block address of the three storage magnetic area 14 is P _N to P _N+R-1 , and the logical block address is L _N to L _N+R-1 . For example, in the embodiment, the first potential storage mode is a single-stage unit type, the second potential storage mode is a multi-level unit type, and the third potential storage mode may be a three-layer storage (TLC). ). Furthermore, in this embodiment, the data processing module 2 may further include a record corresponding to the third storage magnetic area 14 in addition to the first mapping table T1 and the second mapping table T2. The physical block address is P _N to P _N+R-1 and the third mapping table T3 of the logical block address L _N to L _N+R-1 .

In summary, the solid state storage device with the mixed storage mode of the present invention mainly consists of a flash memory and a data processing module connected to the flash memory. The flash memory includes a first storage magnetic region for storing data in a first potential storage mode and a second storage magnetic region for storing data in a second potential storage mode, the entity of the first storage magnetic region The block address is P ₀ to P _M-1 , the logical block address is L ₀ to L _M-1 , and the physical block address of the second storage magnetic zone is P _M to P _M+N-1 The logical block address is L _M to L _M+N-1 . The data processing module has a data processing mode for interpreting the logical block address included in an instruction and performing an instruction action on the corresponding physical block address. Accordingly, a solid storage device having high stability and high data storage capacity is provided.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

1‧‧‧flash memory
11‧‧‧Information block
12‧‧‧First storage area
13‧‧‧Second storage area
14‧‧‧ Third storage area
2‧‧‧ Data Processing Module
3‧‧‧Computer equipment
100‧‧‧Solid storage device
D1‧‧ directive
T1‧‧‧ first pair table
T2‧‧‧ second pair table
T3‧‧‧3rd party table

Figure 1 is a block diagram showing an embodiment of a solid state storage device having a mixed storage mode of the present invention. 2 is a schematic diagram of a flash memory of an embodiment of a solid state storage device with a mixed storage mode of the present invention. 3 is a schematic diagram of a flash memory of another embodiment of the solid state storage device with mixed storage mode of the present invention.

1‧‧‧flash memory

2‧‧‧ Data Processing Module

3‧‧‧Computer equipment

100‧‧‧Solid storage device

D1‧‧ directive

Claims (6)

A solid state storage device with a mixed storage mode includes: a flash memory including a first storage magnetic region for storing data in a first potential storage mode and a first one different from the first potential storage mode The second potential storage mode stores a second storage magnetic region of the data, the first storage magnetic region includes M data blocks, and the second storage magnetic region includes N data blocks, and each of the data blocks corresponds to a physical block address and a logical block address, the physical block address of the first storage magnetic zone is P ₀ to P _M-1 , and the logical block address is L ₀ to L _M-1 The physical block address of the second storage magnetic zone is P _M to P _M+N-1 , and the logical block address is L _M to L _M+N-1 ; and a data processing module, and The flash memory information connection has an instruction to receive an instruction and interpret the logical block address included in the instruction, and execute an instruction action on the corresponding physical block address; wherein the first potential storage mode is a single Level unit type, and the second potential storage mode is a multi-level unit type, and the data processing module has Analyzing the LBA included in the instruction data to change the mode of the instruction of the original modulation mode is stored potential L ₀ to L _M-1 added to this instruction a voltage modulation command. The solid state storage device with a mixed storage mode according to claim 1, wherein the data storage capacity of the first storage magnetic zone is different from the data storage capacity of the second storage magnetic zone. The solid state storage device with a mixed storage mode according to claim 1 or 2, wherein the data processing module includes a physical block address corresponding to the first storage magnetic zone as P ₀ to P _M-1 And a first mapping table of the logical block addresses L ₀ to L _M-1 , and a physical block address corresponding to the second storage magnetic zone is P _M to P _M+N-1 and a logical area A second mapping table of block addresses L _M to L _M+N-1 . The solid state storage device with a mixed storage mode according to claim 1, wherein the flash memory further comprises a third potential storage mode stored in the first potential storage mode and the second potential storage mode. a third storage magnetic zone of the data, the third storage magnetic zone includes R data blocks, and the physical storage block address of the third storage magnetic zone is P _N to P _N+R-1 , and the logical block The address is L _N to L _N+R-1 . The solid state storage device with a mixed storage mode according to claim 4, wherein the data processing module includes a physical block address corresponding to the first storage magnetic zone as P ₀ to P _M-1 and logic The first mapping table of the block addresses L ₀ to L _M-1 , the physical block address corresponding to the second storage magnetic zone is recorded as P _M to P _M+N-1 and the logical block address a second mapping table of L _M to L _M+N-1 , and a physical block address corresponding to the recording of the third storage magnetic domain is P _N to P _N+R-1 and a logical block address L The third pair of tables from _N to L _N+R-1 . The solid state storage device with a mixed storage mode according to claim 1, wherein the data processing module has a data according to the first storage magnetic region and the second storage magnetic region when the instruction is a write data operation The number of erasures of the data block finds an average write algorithm for a recordable block for average write.