TWI606458B - Operation method of non-volatile memory device - Google Patents

Description

Non-volatile memory device operation method

This invention relates to an operational method and, more particularly, to a method of operation of a non-volatile memory device.

Generally, a NAND flash memory is used as a data storage medium, such as a solid state disk (SSD), an embedded multi-media card (eMMC), or a mobile hard disk. It usually includes multiple physical blocks, and each physical block will include multiple pages. Since a filled physical block cannot be repeatedly written to the data before being erased, when a host wants to update the data in the physical block, it will first write the new data to another one that is not full. Physical block (temporary block). This other entity block will store the valid data, and the data (original data) to be updated stored in the original entity block will be invalidated and retained in the original physical block. Therefore, when the space of the temporary storage block is not enough, the reverse flash memory needs to be reconstructed from the original data and the new data.

Reorganization is the process of moving or copying valid data on one or more physical blocks. To an alternate physical block, so that a physical block filled with valid and invalid data can be erased and used to store other data. The reforming operation is well known to those skilled in the art and will not be described again. However, when these physical blocks are reorganized, if there is a power outage event, there may be pages in the spare physical block that have been written to the reorganization data but have not completed the reorganization operation, and these pages may be broken. Data corruption or error caused by electrical events. Therefore, if there is a power outage event when the physical block is reformed, the hard disk may lose some of the data.

On the other hand, in general, hard disks (such as solid state drives, eMMC, etc.) need to use an information table to record the mapping relationship between logical addresses and physical addresses. In the process of continuously executing a plurality of data access instructions or reorganization instructions of the host, since the correspondence between the logical address and the physical address can be correspondingly changed, the content of the information table can be continuously updated. However, as the amount of data written by the SSD increases, so does the content recorded on the information sheet. Therefore, traditional solid state drives require very large storage space to place this information sheet.

In addition, the above-mentioned hard disk may have a single level cell (SLC) NAND type flash memory, a multi-level cell (MLC) NAND type flash memory, and a three-layer memory cell (Triple Level). Cell, TLC) NAND flash memory or other type of flash memory. Among them, the three-layer memory cell flash memory has a higher bit error rate.

The invention provides a method for operating a non-volatile memory device, which can Take into account the correctness of data writing and data writing speed.

The embodiment of the present invention further provides a method for operating a non-volatile memory device, wherein the non-volatile memory module of the non-volatile memory device includes a plurality of physical blocks operating in a single-layer memory cell mode and a plurality of operations. A solid block of three-layer memory cell mode. The method includes: writing data to one of the physical blocks operating in the single-layer memory cell mode; and operating the physical block in the single-layer memory cell mode in the non-volatile memory module When all the pages of the three physical blocks are used, it is decided to perform internal or external re-construction on the three physical blocks according to a condition to reform the data of the three physical blocks to operate in three A selected physical block of the plurality of physical blocks of the layer memory cell mode.

Based on the above, the non-volatile memory module can select an external memory controller to correct the data of the physical block written in the three-layer memory mode, or directly through the non-volatile memory module. The internal control circuit reorganizes the data to take into account the correctness of data writing and the speed of data writing.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Non-volatile memory device

10‧‧‧Host

110‧‧‧ memory controller

120‧‧‧Non-volatile memory module

122, 124‧‧‧ physical blocks

122p, 124p‧‧‧ page

202‧‧‧Microprocessing unit

204‧‧‧Host interface

206‧‧‧ memory interface

208‧‧‧buffer memory

210‧‧‧Error checking and correction unit

D0‧‧‧First reorganization data

D1‧‧‧Reorganization data

D2‧‧‧Second reorganization

P1-0~P1-(x+1), P2-0~P2-y‧‧‧ page

N1, n1+1~n1+4, n1, n2, n3, n4, n5‧‧‧ logical page address

M1, m2, m3, m4, m5‧‧‧ physical block addresses

K1, k1+1~k1+4, k2, k3, k4, k5‧‧‧ physical page address

S302~S308‧‧‧ Non-volatile memory device operation method steps

S602~S608, S801~S806‧‧‧ steps of operation method

1 is a block diagram of a non-volatile memory device in accordance with an embodiment of the invention.

2 is a diagram of the memory controller of FIG. 1 according to an embodiment of the invention. Block diagram.

FIG. 3 is a flow chart showing an operation method of a non-volatile memory device according to an embodiment of the invention.

4 and 5A to 5D are schematic views illustrating the reforming of the non-volatile memory device.

FIG. 6 is a flow chart showing an operation method of a non-volatile memory device according to an embodiment of the invention.

FIG. 7A is a schematic diagram of logical address information and physical address information of a first reformed data according to an embodiment of the invention.

FIG. 7B is a schematic diagram of an execution length mapping table according to an embodiment of the invention.

FIG. 7C is a schematic diagram of a page mapping table according to an embodiment of the invention.

FIG. 8 is a schematic flow chart of an operation method according to an embodiment of the invention.

1 is a block diagram of a non-volatile memory device in accordance with an embodiment of the invention. Referring to FIG. 1, the non-volatile memory device 100 is, for example, a flash memory storage device using a flash memory as a storage medium, such as a solid state disk (SSD), embedded flash. A hard disk such as an Embedded MultiMediaCard (eMMC) or a mobile hard disk. In some application scenarios, the non-volatile memory device 100 can be used as a cache space for storing various cache data. In other applications In the meantime, the non-volatile memory device 100 can be used as a mass storage device. In addition, the non-volatile memory device 100 of the embodiment can be coupled to the host 10 for accessing data by the host 10. The host 10 can be a personal computer, a notebook computer, a tablet computer, a smart phone, or other computing device. Platform/device. The non-volatile memory device 100 can be disposed inside the host 10 and electrically connected to the host 10. Alternatively, the non-volatile memory device 100 can be electrically connected to the host 10 by means of an external connection, for example, electrically connected to the host 10 through various bus bars such as a universal serial bus (USB). This embodiment does not limit it.

The non-volatile memory device 100 includes a memory controller 110 and one or more non-volatile memory modules 120. The memory controller 110 is coupled to the non-volatile memory module 120. This embodiment does not limit the number of non-volatile memory modules 120. The memory controller 110 can be implemented in a hard type or a firmware type. For example, memory controller 110 may include multiple logic gates. The memory controller 110 can perform data writing, reading, erasing, reforming, and/or other operations in the non-volatile memory module 120 according to instructions issued by the host 10.

The non-volatile memory module 120 has at least one physical block to store data written by the host 10. For convenience of description, the first physical block 122 and the second physical block 124 included in the non-volatile memory module 120 are taken as an example, but the embodiment does not limit the number of physical blocks. In detail, the first physical block 122 has at least one page 122p. The second entity block 124 has at least one page 124p, wherein different pages belonging to the same entity block can be written independently and belong to all of the same physical block Pages can be erased at the same time. For example, each physical block may be composed of 128 pages, but is not limited thereto. In other embodiments, each physical block may also consist of 64 pages, 256 pages, or any other page. In this embodiment, the non-volatile memory module 120 is, for example, a single-level memory cell (SLC) NAND flash memory or a multi-level cell (MLC) NAND flash memory. , Triple-level memory (TLC) NAND flash memory or other types of flash memory. Among them, each memory cell of the SLC NAND type flash memory can store 1 bit of data, and each memory cell of the MLC NAND type flash memory can store 2 bits of data, while the TLC NAND type flashes. Each memory cell of the memory can store 3 bits of data.

FIG. 2 is a block diagram of the memory controller 110 of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2 simultaneously, the memory controller 110 includes a micro processing unit 202, a host interface 204, a memory interface 206, a buffer memory 208, and an error checking and correcting unit 210.

The micro processing unit 202 is used to control the overall operation of the memory controller 110. For example, the micro processing unit 202 can control the memory controller 110 to perform the operation method of the embodiment (described in detail later) to reform the non-volatile memory module 120 in the non-volatile memory device 100. Or write the data into the non-volatile memory module 120. In addition, the memory controller 110 maintains one or more logical to physical address information tables (or address mapping tables) to record the logical address and presence of the data on the host 10. The mapping relationship of physical addresses in the volatile memory module 120. Thereby, when the host 10 wants to access a certain When a logical address is obtained, the micro processing unit 202 can obtain a corresponding physical address according to the information table, and access the data on the physical address in the non-volatile memory module 120.

The host interface 204 is coupled to the micro processing unit 202 and is configured to receive instructions and data transmitted by the host 10. That is to say, the instructions and data transmitted by the host 10 are transmitted to the micro processing unit 202 through the host interface 204. In this embodiment, the host interface 204 is, for example, an interface circuit compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the invention is not limited thereto. For example, in other embodiments, the host interface 204 may also be compatible with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, and high-speed peripheral components. Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High II (Ultra High) Speed-II, UHS-II) interface standard, Secure Digital (SD) interface standard, Memory Stick (MS) interface standard, Multi Media Card (MMC) interface standard, small flash ( Compact Flash, CF) interface standard, integrated device electronics (IDE) standard or other suitable data transmission standard interface circuit.

The memory interface 206 is coupled to the micro processing unit 202 and used to access the non- Volatile memory module 120. The memory interface 206 can convert the data signals into a format acceptable to the non-volatile memory module 120. That is, the micro processing unit 202 can store the data to be written to the non-volatile memory module 120 to the non-volatile memory module 120 via the memory interface 206.

The buffer memory 208 is coupled to the micro processing unit 202 and used to temporarily store data and instructions from the host 10 or to store management information of the non-volatile memory module 120 by the micro processing unit 202 (for example, the above information table). ), or temporarily storing data from the non-volatile memory module 120. Here, the buffer memory 208 is, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or other volatile memory. .

The error checking and correction unit 210 is coupled to the micro processing unit 202 and is configured to perform error checking and correction procedures to ensure the correctness of the data. Specifically, when the micro processing unit 202 receives a write command from the host 10, the error check and correction unit 210 generates a corresponding error check and correction code (Error Checking and Correcting Code) for the data corresponding to the write command. ECC Code), and the micro processing unit 202 writes the data corresponding to the write command and the corresponding error check and correction code into the non-volatile memory module 120. After that, when the micro processing unit 202 reads the data from the non-volatile memory module 120, the error check and the correction code corresponding to the data are simultaneously read, and the error check and correction unit 210 performs the error check and the correction code pair according to the error check and correction code. The read data performs error checking and calibration procedures.

The present embodiment is described below with the non-volatile memory device 100 described above. Example of the method of operation. FIG. 3 is a flow chart of an operation method of the memory device 100 according to an embodiment of the invention. 4 and 5A to 5D are schematic views illustrating the reforming of the non-volatile memory device 100. Referring to FIG. 1 , FIG. 3 and FIG. 4 , in step S302 , when the memory controller 110 performs the reforming of the non-volatile memory device 100 , the memory controller 110 converts the first reformed data that has been reconstructed. At least one page 122p of the first physical block 122 is written. For example, in FIG. 4, the reformed data D0 that has been reformed is stored by the page 122p labeled P1-0~P1-1, and the page 122p labeled P1-2~P1-x is used. Stores the reformed data D1 that has been reformed. The at least one page 122p in which the reform data D0 and D1 are sequentially written, where x is a positive integer. It is worth noting that for multi-level cell (MLC) and triple-level memory (TLC) NAND-type flash memory, it has a pair of pages (Pair Page) and multiple pages. The characteristics of the same memory cell, that is, the bit data of a corresponding two pages or three pages in one memory cell. In addition, for the same physical block, these pairs of pages may be continuous or discontinuous, depending on the design. For example, in FIG. 4, it is assumed that the pages 122p labeled P1-x and P1-(x-1) correspond to the same memory cell, and this is a continuous pair of pages, and the hypotheses are labeled P1-x and P1- The page 122p of (x-2) corresponds to the same memory cell, and this is a discontinuous pair of pages.

In addition, in the present embodiment, if the power-off event does not occur, the memory controller 110 may be heavy after writing the reforming data D1 to the pages 122p labeled P1-2 to P1-x in FIG. The page connected to the last page 122p of the entire data D1, that is, starting from the page 122p labeled P1-(x+1), continue to store A reorganization of the information. It is assumed that a power down event occurs during the writing of the next round of reforming data to the first physical block 122, such that the next round of reforming data is not completely written to the first physical block 122. After power-on, the memory controller 110 can once again write the next round of reforming data to the first physical block 122, and perform subsequent data reforming operations. However, in the case that the technology described in this embodiment is not applied, in the process of writing the next piece of reformed data to the first entity block 122 again after power-on, the next piece of reforming data may be An error/loss occurred. For example, if the next reforming data is not completely written to the page 122p labeled P1-(x+1), a power-off event occurs, and after the power is turned back on, the memory controller 110 can be labeled as P1-0. The corresponding information in this page 122p of P1-x determines that the reforming data D1 has been completely written to this page 122p labeled P1-x. In the case where the technique described in this embodiment is not applied, the information of the page 122p itself and its paired page (Pair Page), which is marked as P1-(x+1) after power-on, may be erroneous/escaped.

It is worth mentioning that the memory controller 110 can provide an information table to record at least one physical address information corresponding to the first reformed material D0, wherein the physical address information indicates that the first physical block 122 is labeled as P1. The physical address of the page 122p of -0~P1-1. Therefore, when the host 10 wants to access the reforming material D0 in the first entity block 122, the memory controller 110 can access the reforming material D0 in the first entity block 122 according to the information table. In addition, when the memory controller 110 writes the reformed data D0 that has been reformed into one of the pages 122p of the first physical block 122, the memory controller 110 can use an indicator to record that the current write has been completed. The physical address of the next page 122p of the reorganized data D0. Which refers to For example, the label is stored in the buffer memory 208 (shown in FIG. 2) of the memory controller 110, and can be updated according to the page of the physical block written by the memory controller 110 to record the same or different. The physical address of the page in the entity block.

It is assumed that, in the case where the steps S304 to S308 of the present invention are not performed, when the power is supplied to the non-volatile memory device 100 again after the power-off event, the non-volatile memory device 100 may undergo a reform data D1 error/ The problem of loss. The reason why the reforming data D1 error/escape occurs in the case where the steps S304 to S308 are not performed is explained as follows.

For example, as shown in FIG. 4, if the memory controller 110 writes the reformation data D1 to the page 122p indicated as P1-x in the first physical block 122, a power-off event occurs, so that the memory controller 110 is caused. When the executed write operation is interrupted, in addition to the possible damage to the page P1-x being written, it may also affect other pairs of pages in the same memory cell (Pair Page, for example, labeled P1-( The page 122p) of x-1) or P1-(x-2) results in one or more page material errors. In other words, if a power outage event occurs during the reforming process, data errors of consecutive or discontinuous pairs of pages may occur for MLC NAND type flash memory. Or, for TLC NAND type flash memory, data errors of three consecutive or discontinuous pages may occur. Steps S304 to S308 of the embodiment of the present invention can effectively prevent error/loss of the data in the process of power-off and power-on, and the following description will be made with reference to FIG. 5A to FIG. 5D.

Referring to FIG. 5A, the memory controller 110 writes the material D0 to the page 122p indicated as P1-0 or P1-1 in the first physical block 122, where the data D0 is, for example, The reformed data that has been reorganized has been completed. After the data D0 is written to the first physical block 122, the memory controller 110 can continue to store the next round of reorganization data to the first physical block 122. It will be assumed here that a power down event occurs during the writing of the next round of reforming data to the first physical block 122 such that the next round of reforming data is not completely written to the first physical block 122. When power is supplied to the non-volatile memory device 100 again after the power-off event, as shown in FIG. 5B, the memory controller 110 may proceed to step S304 to select one physical block from the plurality of free-body blocks (for example, the second entity). Block 124), and the second physical block 124 is erased. Here, the memory controller 110 erases the data stored in the second physical block 124, for example. For example, the second physical block 124 illustrated in FIG. 5B indicates that the data stored in the second physical block 124 has been erased when power is again supplied to the non-volatile memory device 100 after the power-off event.

In step S306, after the erasing process is completed, the memory controller 110 searches for the valid data completely written to the first physical block 122 before the power-off event. For example, after re-powering, the memory controller 110 can determine, based on the corresponding information in the page 122p, that the reform data D0 has been completely written to the first physical block 122 before the power-off event. Therefore, the memory controller 110 copies the reformed material D0 completely written by the first physical block 122 before the power-off event to at least one page 124p of the second physical block 124 in step S306, wherein the at least one The page 124p corresponds to the at least one page 122p. For example, in FIG. 5C, the page 124p labeled P2-0~P2-1 in the second entity block 124 stores the reformation data D0 copied from the first physical block 122.

In step S308, the memory controller 110 continues to operate on non-volatile memory. The body device 100 performs reforming, and writes the second reforming material that is continuously reformed after the power is supplied to the non-volatile memory device 100 to the second physical block 124 without writing to the first physical block 122. For example, in FIG. 5D, after the completion of the reforming data D0 is copied to the second physical block 124, the memory controller 110 may continue to reform the non-volatile memory device 100 to obtain the second reforming data D2, and The second reformation data D2 is stored on the page 124p labeled P2-2~P2-y in the second physical block 124, where y is a positive integer. In an embodiment, after the second physical block 124 completes the data reconstruction operation, the memory controller 110 can also selectively erase the first physical block 122 to release the storage space of the first physical block 122. .

In addition, the memory controller 110 can also update the physical address information of the information table. The physical address information respectively indicates the physical address of the page 124p corresponding to the P2-0~P2-y in the second entity block 124. In this way, the memory controller 110 can access the reformed data in the non-volatile memory device 100 according to the information table (including the first reformed data D0 that is reformed before the power-off event, and the power-off After the event, power is again supplied to the second reforming data D2) reformed by the non-volatile memory device 100.

It is explained here that if the memory controller 110 stores the second reforming data D2 into the second physical block 124, another power-off event occurs to cause the memory controller 110 to be in progress. When the reforming operation is once again interrupted, the memory controller 110 executes the above steps S304 to S306 again. That is, when power is supplied to the memory device 100 again after the power-off event, the memory controller 110 initializes another physical block and completes the initialization process. After that, the memory controller 110 copies the first reformed material D0 written by the first physical block 122 before the power-off event to the page corresponding to the other physical block. Moreover, the memory controller 110 continues to reform the memory device 100 to obtain the second reforming data D2, and writes the obtained second reforming data D2 into the other physical block.

Based on the above, since the power is again supplied to the non-volatile memory device 100 after the power-off event, the memory controller 110 copies the first reformed data D0 that has been reformed from the original first physical block 122 to The second physical block 124 of the erased program has been erased. Moreover, the memory controller 110 can write the second reforming data D2 (ie, the reforming data after the first reforming data D0) that is reformed after the power supply is restored, to the second physical block 124 without writing. The first physical block 122. In this way, when the memory controller 110 performs the reforming of the non-volatile memory device 100, if the power-off event resumes the power supply again, the first reforming data D0 before the power-off event is safe. The remaining in the first physical block 122, the memory controller 110 can avoid the error caused by the power failure of the first physical block 122, thereby improving the correctness of the reformed data.

It is worth mentioning that the memory controller 110 can also execute the length when writing the reformed data that has been re-formed into at least one of the physical blocks (for example, the physical blocks 122, 124 or other physical blocks). A run-length mapping table that records re-formed data with consecutive logical addresses and bits in multiple consecutive pages of the same physical block to reduce logical address information and entities used to store the reconstructed data. The space of the address information. For convenience of explanation, the memory controller 110 is underneath. The step of writing the reformed data that has been reformed into at least one physical block of the non-volatile memory module 120 is taken as an example to explain the operation method of writing the reformed data into the physical block.

FIG. 6 is a flow chart showing an operation method of a non-volatile memory device according to an embodiment of the invention. Referring to FIG. 1 and FIG. 6 simultaneously, in step S602, the memory controller 110 writes the reformed data into at least one physical block of the non-volatile memory module 120, such as the first physical block 122 or the second physical block. 124. In step S604, the memory controller 110 determines whether the first condition is met, wherein the first condition includes that the plurality of logical addresses of the reformed material are consecutive and the reformed data bits are in the same physical block. In a continuous page. For example, if the memory controller 110 writes the reformed data having the plurality of consecutive logical addresses into the plurality of consecutive pages of the first physical block 122 of the non-volatile memory module 120, the first condition is established. . However, if the memory controller 110 writes the reformed data to the non-contiguous page of the first physical block 122 of the non-volatile memory module 120, the first condition does not hold.

When the first condition is met, the memory controller 110 records the start logical address of the reformed data, the starting physical address of the reformed data, and the data length of the reformed data, respectively, as shown in step S606. The logical address field, the physical address field, and the length field in the length mapping table are executed, wherein the memory controller 110 can learn the reorganization data according to the starting physical address and the ending physical address of the reorganization data. The length of the data.

FIG. 7A illustrates the relationship between logical address information and physical address information of the reformed data written to the non-volatile memory module 120 according to an embodiment of the invention. schematic diagram. FIG. 7B is a schematic diagram of an execution length mapping table according to an embodiment of the invention. In the embodiment shown in FIG. 7B, the logical address field of the execution length mapping table is a logical page address field, and the physical address field in the execution length mapping table includes a physical block address ( Physical block address) field and physical page address field. It can be seen from the logical address information of FIG. 7A that the logical page address of the reformed data is continuous, for example, the logical address is n1~n1+4. Moreover, according to the physical address information of FIG. 7A, the reorganization data is located in multiple consecutive pages of the same physical block, for example, the physical block address is m1, and the physical page address is k1~k1+4. The memory controller 110 can know that the data length of the reformed material is 5 according to the starting physical page address k1 and the ending physical page address k1+4 of the reformed data.

Therefore, the memory controller 110 determines in step S604 that the reforming data exemplified in FIG. 7A conforms to the first condition, so the memory controller 110 records the address mapping relationship of the reformed data in the execution length mapping in step S606. In the table. For example, as shown in FIG. 7B, the memory controller 110 will start the logical page address (in this case, n1), the physical block address (in this case, m1), and the starting physical page address of the data. (in this case, k1) and the data length (in this case, 5) record the logical page address field, the physical block address field, the physical page address field, and the length field in the execution length mapping table, respectively. .

On the other hand, when it is judged in step S604 of Fig. 6 that the first condition is not satisfied, the memory controller 110 proceeds to step S608. As shown in step S608, the memory controller 110 divides the plurality of logical addresses of the reformed material and the plurality of physical addresses. Do not record the logical address field and entity address field in the page mapping table. For example, FIG. 7C is a schematic diagram of a page mapping table according to an embodiment of the invention. In the page mapping table of FIG. 7C, the reorganization data bits are in non-contiguous pages of different physical blocks, wherein the logical page address field of the logical address field records the logical page address of the reorganization data as n1, n2 , n3, n4 and n5, the physical block address field of the physical address field records the physical block address of the reorganization data as m1, m2, m3, m4 and m5, and the physical page position of the physical address field The address field records the physical page addresses of the reorganization data as k1, k2, k3, k4, and k5.

It should be noted that the above operation method of FIG. 6 does not limit the write operation applied to the reformed data. For example, after the memory controller 110 receives a data write command from the host 10 and correspondingly writes a piece of data into the non-volatile memory module 120, the memory controller 110 can also be first according to FIG. 6 described above. The condition is used to determine whether to use the execution length mapping table or the page mapping table to record the mapping relationship between the logical address of the data and the physical address. That is, after the memory controller 110 writes a piece of data into at least one physical block of the non-volatile memory module 120, if the first condition is satisfied in step S604 of FIG. 6, the memory controller 110 selects to use The length mapping table is executed to record the mapping relationship between the logical address of the data and the physical address. However, if the step S604 of FIG. 6 determines that the first condition is not satisfied, the memory controller 110 selects to use the page mapping table to record the mapping relationship between the logical address of the material and the physical address.

Based on the above, the memory controller 110 of the embodiment can perform the length mapping when the data is written into at least one physical block of the non-volatile memory module 120. A table is used to record the reformed data having consecutive logical addresses and being located in a plurality of consecutive pages of the same physical block to effectively store logical address information and physical address information corresponding to the reformed data. Thereby, the amount of data in the mapping table can be greatly reduced.

It should be noted that the non-volatile memory module 120 of the embodiment may have multiple physical blocks operating in a single level cell (SLC) mode and operate on a three-layer memory cell (Trinary Level Cell). , TLC) mode of multiple physical blocks. During the operation of writing data into the TLC mode entity block, the data is temporarily stored in the entity block of the SLC mode, and is not directly written into the TLC mode entity block. When all the pages of the three physical blocks operating in the SLC physical block in the non-volatile memory module 120 are used, that is, when the temporary storage space of the three SLC physical blocks is used up, The three SLC physical blocks are subjected to reforming to reform/move the data of the three SLC physical blocks into a physical block operating in the TLC mode in the non-volatile memory module 120. Here, assuming that the first physical block 122 and the second physical block 124 are operating in the TLC mode, all pages of the three physical blocks operating in the SLC mode physical block in the non-volatile memory module 120 are all When used, the memory controller 110 may also perform reorganization on the three SLC physical blocks to reform the data of the three SLC physical blocks into the non-volatile memory module 120 to operate in the TLC mode. In the first physical block 122 or the second physical block 124. An embodiment will be described below for explanation.

FIG. 8 is a flow chart of an operation method according to an embodiment of the invention. The steps of the operation method of the present embodiment will be described below in conjunction with the above-described non-volatile memory device 100. Referring to FIG. 1 and FIG. 8, the memory controller 110 is in step S801. The intermediate data is written to one of the physical blocks operating in the SLC mode. In step S802, the memory controller 110 determines whether it is necessary to move the data of the SLC physical block to the TLC physical block. When all the pages of the three physical blocks operating in the SLC mode in the non-volatile memory module 120 are used, that is, the result of the determination in step S802 is "the data requirement of the SLC physical block. Moving to the TLC physical block", the memory controller 110 proceeds to step S806. In step S806, the memory controller 110 determines, according to a second condition, "internal reforming" or "external reforming" on the three SLC physical blocks to store the data of the three SLC physical blocks. Reconstructed to a selected physical block in a non-volatile memory module 120 operating in a TLC mode entity block. On the other hand, when the three SLC physical blocks still have pages that are not used, that is, the result of the determination in step S802 is "the data of the SLC physical block does not need to be moved to the TLC physical block", the memory controller 110 returns to Step S801, to wait for the next data.

In the embodiment shown in FIG. 8, step S806 includes sub-steps S804, S803, and S805. In step S804, the memory controller 110 determines whether the second condition is true. The second condition includes: the number of erasing of any one of the physical blocks operating in the TLC mode in the non-volatile memory module 120 has reached a first threshold, or is within the non-volatile memory module 120. The bit error rate of any of the entity blocks operating in the TLC mode has reached a second threshold. For example, the non-volatile memory module 120 can record the number of erases of a physical block operating in the TLC mode. And/or, the memory controller 110 can record the bit error rate of each of the TLC entity blocks. For example, when the memory controller 110 reads data from a physical block of the TLC mode, it is transparent. The error checking and correction circuit 210 performs error checking and correction on the data read from the TLC entity block (please refer to the related description of FIG. 2) to obtain the bit error rate of the physical block operating in the TLC mode.

When the step S804 determines that the second condition is met, the non-volatile memory device 100 performs the external reforming to reform the data of the three physical blocks operating in the SLC mode to operate in the TLC mode. The selected physical block. The external reforming is as shown in step S805. In step S805, the data of the three SLC physical blocks in the non-volatile memory module 120 are read to the memory controller 110 outside the non-volatile memory module 120, and the memory is read by the memory. The body controller 110 performs error correction (for example, error checking and correction) on the data of the three SLC physical blocks, and writes the error-corrected data from the memory controller 110 to the operation in the TLC mode. The physical block is selected (eg, written in the first physical block 122 or the second physical block 124). Specifically, the error checking and correction circuit 210 (shown in FIG. 2) in the memory controller 110 can correct the data of the three SLC physical blocks, and the error-corrected data write operation is performed on the TLC. The first physical block 122 or the second physical block 124 of the mode is to reduce the bit error rate of the data in the TLC physical block. After the external reforming is completed, the data in the three SLC physical blocks is erased to release the memory space.

On the other hand, when it is determined in step S804 that the second condition is not satisfied, the non-volatile memory device 100 performs the internal reforming to reform the data of the three physical blocks operating in the SLC mode to the operation. The selected physical block in the TLC mode. The difference from the external reforming is that the internal reforming is in the three The process of moving the data of the SLC entity block to the TLC entity block does not perform error correction operations. The internal reforming is as shown in step S803. In step S803, the data of the three SLC physical blocks is reformed by the control circuit inside the non-volatile memory module 120 to the selected physical block operating in the TLC mode (for example, writing the first In the entity block 122 or the second entity block 124). Specifically, the control circuit inside the non-volatile memory module 120 can execute a plurality of logic gates or control commands implemented in a hard type or a firmware type to control data in the three SLC entity blocks. The first entity block 122 or the second entity block 124 operating in the TLC mode is separately rewritten. That is to say, the control circuit can automatically reformate the data into the corresponding physical block operating in the TLC mode according to a preset instruction. Thereby, when data reforming is performed to write the data in the three SLC entity blocks into the physical block of the TLC mode, the internal reforming may have a higher data writing speed. After the internal reforming is completed, the data in the three SLC physical blocks is erased to release the memory space.

Based on the above, the non-volatile memory device 100 determines whether the non-volatile memory model is transmitted through the memory controller 110 outside the non-volatile memory module 120 according to whether the second condition is established or not. Group 120 performs a data reorganization operation, such as moving the data in the three SLC entity blocks to a physical block in the TLC mode. In the data reorganization operation, the memory controller 110 may perform error correction on the data written in the TLC physical block in step S805 to reduce the bit error rate of the data in the TLC physical block. Alternatively, the non-volatile memory device 100 moves the data directly from the original physical block to the TLC physical block through the control circuit inside the non-volatile memory module 120 in step S803 without error correction to obtain a higher data Reorganization speed. Thereby, the embodiment can simultaneously consider the correctness of data writing and the data writing speed.

In summary, in the non-volatile memory device of the embodiment and the method of operating the same, when the power is supplied to the non-volatile memory device again after the power-off event, the memory controller 110 will complete the reforming. The first reforming data is copied from the first physical block to the second physical block that has been erased, and the second reformed data reconstructed after the power supply is restored is connected to the first reformed data to be written into the second entity. Piece. In this way, if there is a power-off event and the power supply is restored again, the memory controller 110 can avoid the error caused by repeatedly writing the reformed data on the same physical page, thereby improving the correctness of the reformed data. In addition, in the operation method of the embodiment, the memory controller 110 can record the continuous logical address by executing the length mapping table when the data is written into at least one physical block of the non-volatile memory module 120. And data in multiple consecutive pages of the same physical block to reduce the amount of data in the mapping table. In another method of the present embodiment, it can be determined whether the data written in the TLC physical block in the non-volatile memory module 120 is corrected by the memory controller 110 outside the non-volatile memory module 120, or The data is directly transferred from the original physical block to the TLC physical block through the control circuit inside the non-volatile memory module 120 without error correction. Thereby, the embodiment can simultaneously consider the correctness of data writing and the data writing speed.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the present invention It is subject to the definition of the scope of the patent application attached.

S801~S806‧‧‧Methods of each step

Claims (4)

A method for operating a non-volatile memory device, wherein a non-volatile memory module of the non-volatile memory device includes a plurality of physical blocks operating in a single-layer memory cell mode and a plurality of operating modes in a three-layer memory cell mode The physical block includes: writing a data to one of the physical blocks operating in the single-layer memory cell mode; and operating the single-layer memory cell in the non-volatile memory module each time When all the pages of the three physical blocks in the physical block of the mode are used, it is decided to perform an internal reorganization or an external reorganization on the three physical blocks according to a condition to directly directly The data of the physical block is reformed to a selected one of the physical blocks operating in the three-layer memory cell mode in the non-volatile memory module. The method of claim 1, wherein the condition includes that the number of erasures of the one of the solid blocks operating in the three-layer memory cell mode in the non-volatile memory module has reached a first The threshold value, or the bit error rate of any of the non-volatile memory modules operating in the three-layer memory cell mode, has reached a second threshold. The method of operation of claim 1, wherein when the condition is met, the external reforming is performed to directly reform data of the three physical blocks operating in a single-layer memory cell mode to operate The selected physical block of the three-layer memory cell mode; and the external reforming includes: reading data of the three physical blocks operating in the single-layer memory cell mode to the non- a memory controller external to the volatile memory module; correcting data of the three physical blocks operating in the single-layer memory cell mode through the memory controller; and correcting the data The selected physical block operating in the three-layer memory cell mode is directly written from the memory controller. The operation method of claim 1, wherein when the condition is not satisfied, the internal reforming is performed to directly reform data of the three physical blocks operating in a single-layer memory cell mode to operate The selected physical block of the three-layer memory cell mode; and the internal reforming includes: operating, by a control circuit inside the non-volatile memory module, the three physical blocks operating in a single-layer memory cell mode The data is written directly into the selected physical block operating in the three-layer memory cell mode.