CN112527184A

CN112527184A - Data management method, memory control circuit unit and memory storage device

Info

Publication number: CN112527184A
Application number: CN201910875852.8A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2019-09-17
Filing date: 2019-09-17
Publication date: 2021-03-19

Abstract

A data management method, a memory control circuit unit, and a memory storage device. The method comprises the following steps: receiving a write-in command for writing first data into the rewritable nonvolatile memory module; when the first data is continuous data, respectively writing the first data into a plurality of first entity erasing units in a single page programming mode, and recording first management information corresponding to the first entity erasing units; and when the first data is not continuous data, respectively writing the first data into a plurality of second entity erasing units in a single page programming mode.

Description

Data management method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data management method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, cell phones and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years.

The NAND flash memory is classified into a Single Level Cell (SLC) NAND flash memory, a Multi-Level Cell (MLC) NAND flash memory, and a Triple Level Cell (TLC) NAND flash memory according to the number of bits that each memory Cell can store, wherein each memory Cell of the SLC NAND flash memory can store 1 bit of data (i.e., "1" and "0"), each memory Cell of the MLC NAND flash memory can store 2 bits of data, and each memory Cell of the TLC NAND flash memory can store 3 bits of data.

In the NAND flash memory, the physical programming unit is composed of a plurality of memory cells arranged on the same word line. Since each cell of the SLC NAND flash memory can store 1 bit of data, several cells arranged on the same word line correspond to one physical program cell in the SLC NAND flash memory.

The floating gate storage layer of each memory cell of the MLC NAND type flash memory can store 2 bits of data as compared to the SLC NAND type flash memory, wherein each memory state (i.e., "11", "10", "01", and "00") includes a Least Significant Bit (LSB) and a Most Significant Bit (MSB). For example, the value of the 1 st bit from the left side in the memory state is LSB, and the value of the 2 nd bit from the left side is MSB. Therefore, a plurality of memory cells arranged on the same word line may constitute 2 physical programming units, wherein a physical programming unit constituted by the LSBs of the memory cells is referred to as a lower physical programming unit (low physical programming unit), and a physical programming unit constituted by the MSBs of the memory cells is referred to as an upper physical programming unit (upper physical programming unit). In particular, the writing speed of the lower physical programming unit is faster than that of the upper physical programming unit, and when an error occurs in the upper physical programming unit, the data stored in the lower physical programming unit may be lost.

Similarly, in the TLC NAND type flash memory, each memory cell may store 3 bits of data, wherein each memory state (i.e., "111", "110", "101", "100", "011", "010", "001", and "000") includes the LSB of the 1 st Bit from the left side, the middle Significant Bit (CSB) of the 2 nd Bit from the left side, and the MSB of the 3 rd Bit from the left side. Therefore, the plurality of memory cells arranged on the same word line may constitute 3 physical program cells, wherein the physical program cell constituted by the LSB of the memory cells is referred to as a lower physical program cell, the physical program cell constituted by the CSB of the memory cells is referred to as a middle physical program cell, and the physical program cell constituted by the MSB of the memory cells is referred to as an upper physical program cell. In particular, when programming a plurality of memory cells arranged on the same word line, only the lower physical program cell or the lower physical program cell, the middle physical program cell and the upper physical program cell can be selected to be programmed, otherwise the stored data may be lost.

Generally, a memory module using TLC NAND type flash memory may group some of the physically erased cells therein to simulate the operation of SLC NAND type flash memory using a single page programming mode operating only in the next physically programmed cell, thereby improving the writing speed. Then, when the valid data merging operation is to be performed, the memory management circuit selects a plurality of source erase units from the erase units simulating the SLC NAND flash memory, collects a plurality of data written in the single page programming mode from the source erase units, and writes the data in the multiple page programming mode into one erase unit to store the data in a lower, a middle and an upper one of the erase units.

It should be noted, however, that when performing the valid data merge operation, the data in the source erase units are not necessarily consecutive based on the selection rule of the source erase units (e.g., based on the valid data count or erase count rule). Therefore, after performing the effective data merging operation, if a plurality of consecutive data are required to be stored in the same physical erase unit for data access efficiency, an additional data merging operation is usually performed to find the consecutive data from the plurality of physical erase units and then merge and store the consecutive data into the same physical erase unit. However, since a large amount of data merging operations are required in the foregoing situation, the operation performance of the rewritable nonvolatile memory is greatly reduced.

Based on the above, how to avoid performing a large amount of data merging and to store multiple data in succession in the same physical erase unit when performing the data merging is the objective of those skilled in the art.

Disclosure of Invention

The invention provides a data management method, a memory control circuit unit and a memory storage device, which can avoid executing massive data combination and store a plurality of continuous data in the same entity erasing unit when executing the data combination.

The invention provides a data management method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and the data management method comprises the following steps: receiving a write instruction for writing first data into the rewritable nonvolatile memory module; when the first data is continuous data, writing the first data into a plurality of first entity erasing units in the plurality of entity erasing units in a single page programming mode respectively, and recording first management information corresponding to the plurality of first entity erasing units; and when the first data is not continuous data, respectively writing the first data into a plurality of second entity erasing units in the plurality of entity erasing units in the single page programming mode.

In an embodiment of the present invention, the method further includes: identifying the first plurality of physically erased cells, which respectively store the first data, from the plurality of physically erased cells according to the first management information; and copying the first data from the first plurality of physically erased cells and writing the first data into a third physically erased cell of the plurality of physically erased cells in a multi-page programming mode.

In an embodiment of the present invention, the method further includes: judging whether the logic addresses of the first data are continuous or not; when the logic addresses of the first data are continuous, judging that the first data are continuous data; and when the logic address of the first data is discontinuous, judging that the first data is discontinuous data.

In an embodiment of the present invention, the step of recording the first management information corresponding to the plurality of first physically erased cells includes: recording the order of the first data.

In an embodiment of the present invention, the step of recording the first management information corresponding to the plurality of first physically erased cells includes: the first physical erase units are marked with a first flag.

In an embodiment of the present invention, the step of recording the first management information corresponding to the plurality of first physically erased cells includes: recording a binding relationship of the first entity erasing units into a lookup table.

The invention provides a memory control circuit unit, which is used for controlling a rewritable nonvolatile memory module and comprises: host interface, memory interface and memory management circuit. The host interface is used for coupling to a host system. The memory interface is used for being coupled to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units. Memory management circuitry is coupled to the host interface and the memory interface. The memory management circuit is used for executing the following operations: receiving a write instruction for writing first data into the rewritable nonvolatile memory module; when the first data is continuous data, writing the first data into a plurality of first entity erasing units in the plurality of entity erasing units in a single page programming mode respectively, and recording first management information corresponding to the plurality of first entity erasing units; and when the first data is not continuous data, respectively writing the first data into a plurality of second entity erasing units in the plurality of entity erasing units in the single page programming mode.

In an embodiment of the invention, the memory management circuit is further configured to perform the following operations: identifying the first plurality of physically erased cells, which respectively store the first data, from the plurality of physically erased cells according to the first management information; and copying the first data from the first plurality of physically erased cells and writing the first data into a third physically erased cell of the plurality of physically erased cells in a multi-page programming mode.

In an embodiment of the invention, the memory management circuit is further configured to perform the following operations: judging whether the logic addresses of the first data are continuous or not; when the logic addresses of the first data are continuous, judging that the first data are continuous data; and when the logic address of the first data is discontinuous, judging that the first data is discontinuous data.

In an embodiment of the invention, in the operation of recording the first management information corresponding to the plurality of first physically erased cells, the memory management circuit is further configured to record an order of the first data.

In an embodiment of the invention, in the operation of recording the first management information corresponding to the first plurality of physically erased cells, the memory management circuit is further configured to mark the first plurality of physically erased cells with a first flag.

In an embodiment of the invention, in the operation of recording the first management information corresponding to the first entity erasure units, the memory management circuit is further configured to record a binding relationship of the first entity erasure units into a lookup table.

The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for being coupled to a host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module and is used for executing the following operations: receiving a write instruction for writing first data into the rewritable nonvolatile memory module; when the first data is continuous data, writing the first data into a plurality of first entity erasing units in the plurality of entity erasing units in a single page programming mode respectively, and recording first management information corresponding to the plurality of first entity erasing units; and when the first data is not continuous data, respectively writing the first data into a plurality of second entity erasing units in the plurality of entity erasing units in the single page programming mode.

In an embodiment of the invention, the memory control circuit unit is further configured to perform the following operations: identifying the first plurality of physically erased cells, which respectively store the first data, from the plurality of physically erased cells according to the first management information; and copying the first data from the first plurality of physically erased cells and writing the first data into a third physically erased cell of the plurality of physically erased cells in a multi-page programming mode.

In an embodiment of the invention, the memory control circuit unit is further configured to perform the following operations: judging whether the logic addresses of the first data are continuous or not; when the logic addresses of the first data are continuous, judging that the first data are continuous data; and when the logic address of the first data is discontinuous, judging that the first data is discontinuous data.

In an embodiment of the invention, in the operation of recording the first management information corresponding to the plurality of first physical erase units, the memory control circuit unit is further configured to record an order of the first data.

In an embodiment of the invention, in the operation of recording the first management information corresponding to the first plurality of physically erased cells, the memory control circuit unit is further configured to mark the first plurality of physically erased cells with a first flag.

In an embodiment of the invention, in the operation of recording the first management information corresponding to the first entity erasure units, the memory control circuit unit is further configured to record a binding relationship of the first entity erasure units into a lookup table.

Based on the above, the data management method, the memory control circuit unit and the memory storage device of the present invention can ensure that a plurality of data stored in the same physical erase unit are mutually continuous after the rewritable nonvolatile memory module performs the effective data merge operation, thereby avoiding the problem of reduced operation performance of the rewritable nonvolatile memory module caused by performing a large amount of data merge operation in the prior art.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIGS. 5A and 5B are schematic diagrams of an example memory cell architecture and physically erased cells according to the example embodiment;

FIG. 6A is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6B is a diagram illustrating multi-frame coding in accordance with an exemplary embodiment of the present invention;

FIGS. 7 and 8 illustrate exemplary diagrams of managing physical erase units according to one exemplary embodiment;

FIG. 9 is a diagram illustrating writing data to a rewritable nonvolatile memory module using a single page programming mode according to an example;

FIG. 10 is a diagram illustrating an effective data merge operation for data written in a single page program mode using a multi-page program mode, according to an example;

FIG. 11 is a flow diagram illustrating a method of data management, according to an example.

The reference numbers illustrate:

10: memory storage device

11: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main machine board

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

702: memory management circuit

704: host interface

706: memory interface

708: error checking and correcting circuit

710: buffer memory

712: power management circuit

801(1) -801 (r): position of

820: encoding data

810(0) -810 (E): physical programming unit

502: data area

504: idle zone

506: temporary storage area

508: substitution zone

510(0) to 510 (N): physical erase unit

LBA (0) to LBA (h): logic unit

LZ (0) to LZ (M): logical area

Step S1101: receiving a write command for writing first data into a rewritable nonvolatile memory module

Step S1103: judging whether the first data is continuous data

Step S1105: when the first data is continuous data, respectively writing the first data into a plurality of first entity erasing units in a single page programming mode, and recording first management information corresponding to the first entity erasing units

Step S1107: respectively writing the first data into a plurality of second physically erased cells in a single page programming mode when the first data is not continuous data

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all coupled to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is coupled to the I/O devices 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless manner through the data transmission interface 114. The memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be coupled to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory devices (eMCP) 342, which directly couple the memory module to the embedded memory device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia Memory Card (Multimedia, Embedded Multimedia Card (MMC), eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading, erasing and merging of data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has entity erasing units 510(0) -510 (N). For example, the physical erase units 510(0) -510 (N) may belong to the same memory die or to different memory dies. Each of the plurality of physically erased cells has a plurality of physically programmed cells, for example, in the exemplary embodiment of the present invention, each of the plurality of physically erased cells includes 258 physically programmed cells, and the physically programmed cells belonging to the same physically erased cell can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 4 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention.

In an exemplary embodiment of the invention, the rewritable nonvolatile memory module 406 is a multi-Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

FIGS. 5A and 5B are schematic diagrams of memory cell architectures and physically erased cells according to the present example embodiment.

Referring to fig. 5A, the memory state of each memory cell of the rewritable nonvolatile memory module 406 can be identified as "111", "110", "101", "100", "011", "010", "001", or "000" (as shown in fig. 5A), wherein the 1 st bit from the left side is LSB, the 2 nd bit from the left side is CSB, and the 3 rd bit from the left side is MSB. In addition, the plurality of memory cells arranged on the same word line may constitute 3 physical program cells, wherein the physical program cell constituted by the LSB of the memory cells is referred to as a lower physical program cell, the physical program cell constituted by the CSB of the memory cells is referred to as a middle physical program cell, and the physical program cell constituted by the MSB of the memory cells is referred to as an upper physical program cell.

Referring to fig. 5B, a physical erase unit is composed of a plurality of physical program unit groups, wherein each of the physical program unit groups includes a lower physical program unit, a middle physical program unit and an upper physical program unit composed of a plurality of memory cells arranged on the same word line. For example, in the solid erase cell, the 0 th solid program cell belonging to the lower solid program cell, the 1 st solid program cell belonging to the middle solid program cell, and the 2 nd solid program cell belonging to the upper solid program cell are regarded as one solid program cell group. Similarly, the 3 rd, 4 th, and 5 th physical programming cells are considered as a physical programming cell group, and the other physical programming cells are classified into a plurality of physical programming cell groups according to the same manner.

FIG. 6A is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention.

Referring to FIG. 6A, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706, and an error checking and correcting circuit 708.

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to write, read, and erase data during operation of the memory storage device 10. When the operation of the memory management circuit 702 or any circuit element included in the memory control circuit unit 404 is described below, the operation of the memory control circuit unit 404 is equivalently described.

In the exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 702 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware format. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 702 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 704 is coupled to the memory management circuit 702 and is used for receiving and identifying commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the exemplary embodiment, host interface 704 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 706 is coupled to the memory management circuit 702 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 wants to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions are generated by, for example, the memory management circuit 702 and transferred to the rewritable non-volatile memory module 406 via the memory interface 706. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The error checking and correcting circuit 708 is coupled to the memory management circuit 702 and is used for performing an error checking and correcting procedure to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 708 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.

The buffer memory 710 is coupled to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is coupled to the memory management circuit 702 and is used to control the power of the memory storage device 10.

In the exemplary embodiment, the error checking and correcting circuit 708 can perform single-frame (single-frame) coding on data stored in the same physical program unit, or perform multi-frame (multi-frame) coding on data stored in a plurality of physical program units. The single-frame coding and the multi-frame coding may respectively use at least one of coding algorithms such as a low density parity check code (LDPC), a BCH code, a convolutional code (convolutional code), and a turbo code. Alternatively, in an example embodiment, the multi-frame coding may also employ Reed-solomon (RS) codes or exclusive or (XOR) algorithms. In addition, in another exemplary embodiment, more unlisted coding algorithms may be used, and are not described herein. Depending on the encoding algorithm employed, the error checking and correction circuit 708 may encode the data to be protected to produce a corresponding error correction code and/or error check code. For convenience of explanation, the error correction code and/or the error check code generated through encoding will be collectively referred to as encoded data hereinafter.

Fig. 6B is a diagram illustrating multi-frame coding according to an exemplary embodiment of the invention.

Referring to fig. 6B, taking the data stored in the encoded entity programming units 810(0) to 810(E) as an example to generate the corresponding encoded data 820, at least a portion of the data stored in each of the entity programming units 810(0) to 810(E) can be regarded as a frame. In multi-frame coding, data in the physical programming units 810(0) to 810(E) is coded according to the position of each bit (or byte). For example, bit b at position 801(1)₁₁、b₂₁、…、b_p1Will be encoded as bit b in the encoded data 820_o1Bit b at position 801(2)₁₂、b₂₂、…、b_p2Will be encoded as bit b in the encoded data 820_o2(ii) a By analogy, bit b at position 801(r)_1r、b_2r、…、b_prWill be encoded as bit b in the encoded data 820_or. The slave can then be paired according to the encoded data 820The data read in the bulk programming units 810(0) -810 (E) are decoded to attempt to correct errors that may exist in the read data.

In addition, in another exemplary embodiment of fig. 6B, the data for generating the encoded data 820 may also include redundant bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the entity programming units 810(0) -810 (E). Take the data stored in the entity programming unit 810(0) as an example, wherein the redundant bits are generated by performing single frame encoding on the data bits stored in the entity programming unit 810(0), for example. In the present exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810(0), the data read from the physical programming unit 810(0) can be decoded by using the redundancy bits (e.g., the single frame coded data) in the physical programming unit 810(0) for error detection and correction. However, when the decoding using the redundancy bits in the physical programming unit 810(0) fails (e.g., the number of bits error of the data stored in the decoded physical programming unit 810(0) is greater than a threshold), a Retry-Read mechanism may be used to attempt to Read the correct data from the physical programming unit 810 (0). Details regarding the re-read mechanism are detailed later. When the correct data cannot be Read from the physical programming units 810(0) by the Retry-Read mechanism, the encoded data 820 and the data of the physical programming units 810(1) to 810(E) can be Read, and the decoding is performed according to the encoded data 820 and the data of the physical programming units 810(1) to 810(E) to try to correct the errors in the data stored in the physical programming units 810 (0). That is, in the exemplary embodiment, when decoding using the encoded data generated by the single-frame encoding fails and reading using the re-Read (Retry-Read) mechanism fails, the encoded data generated by the multi-frame encoding is decoded instead.

FIGS. 7 and 8 illustrate exemplary diagrams of managing physically erased cells, according to an exemplary embodiment.

Referring to FIG. 7, the rewritable nonvolatile memory module 406 has physical erase units 510(0) -510 (N), and the memory management circuit 702 is logically divided (partitioned) into a data area 502, an idle area 504, a temporary area 506 and a replacement area 508.

The physically erased cells logically belonging to the data area 502 and the idle area 504 are used for storing data from the host system 11. Specifically, the physical erase units in the data area 502 are regarded as physical erase units with stored data, and the physical erase units in the idle area 504 are used to replace the physical erase units in the data area 502. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 702 extracts the physical erase unit from the idle region 504 and writes the data into the extracted physical erase unit to replace the physical erase unit of the data region 502.

The physical erase unit logically belonging to the register 506 is used for recording system data. For example, the system data includes a logical to physical address mapping table, a manufacturer and a model of the rewritable nonvolatile memory module, a number of physical erase units of the rewritable nonvolatile memory module, a number of physical program units of each physical erase unit, and the like.

The physically erased cells logically belonging to the replacement area 508 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are still normal physically erased cells in the replacement area 508 and the physically erased cells in the data area 502 are damaged, the memory management circuit 302 extracts the normal physically erased cells from the replacement area 508 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 502, the idle area 504, the temporary area 506 and the replacement area 508 may vary according to different memory specifications. Moreover, it should be appreciated that during operation of the memory storage device 10, the grouping relationship of the physically erased cells associated with the data area 502, the idle area 504, the temporary area 506 and the replacement area 508 will dynamically change. For example, when the physically erased cells in the idle area 504 are damaged and replaced by the physically erased cells in the replacement area 508, the physically erased cells in the replacement area 508 are associated with the idle area 504.

Referring to fig. 8, the memory management circuit 702 allocates logical units LBA (0) -LBA (h) to map the physical erase units of the data area 502, wherein each logical unit has a plurality of logical sub-units to map the physical program unit of the corresponding physical erase unit. Moreover, when the host system 11 wants to write data to the logical units or update the data stored in the logical units, the memory management circuit 702 extracts a physical erase unit from the idle area 504 to write data, so as to replace the physical erase unit in the data area 502. In the present exemplary embodiment, the logical subunit may be a logical page or a logical sector.

In order to identify the physical erase unit in which the data of each logical unit is stored, in the present exemplary embodiment, the memory management circuit 702 records the mapping between the logical units and the physical erase units. Moreover, when the host system 11 intends to access data in the logical sub-unit, the memory management circuit 702 identifies the logical unit to which the logical sub-unit belongs, and accesses data in the physical erase unit mapped by the logical unit. For example, in the exemplary embodiment, the memory management circuit 702 stores a logical-to-physical address mapping table in the rewritable non-volatile memory module 406 to record the physical erase unit mapped by each logical unit, and the memory management circuit 702 loads the logical-to-physical address mapping table into the buffer memory 710 for maintenance when data is to be accessed.

It should be noted that, since the capacity of the buffer memory 710 is limited and cannot store the mapping table for recording the mapping relationships of all the logic units, in the exemplary embodiment, the memory management circuit 702 groups the logic units LBA (0) to LBA (h) into a plurality of logic zones LZ (0) to LZ (m), and configures a logical-to-physical address mapping table for each logic zone. In particular, when the memory management circuit 702 wants to update the mapping of a logical unit, the logical-to-physical address mapping table corresponding to the logical area to which the logical unit belongs is loaded into the buffer memory 710 for updating.

It should be noted that the memory management circuit 702 can write to the rewritable nonvolatile memory module 406 in a single-page programming mode or a multi-page programming mode.

In particular, in the embodiment, when the memory management circuit 702 receives a plurality of write commands for writing a plurality of data (also referred to as first data) to the rewritable nonvolatile memory module 406 from the host system 11, the memory management circuit 702 determines whether the plurality of first data are consecutive data. For example, when the logical addresses of the first data are consecutive, the memory management circuit 702 determines that the first data are consecutive. When the logical addresses of the first data are not consecutive, the memory management circuit 702 determines that the first data are not consecutive.

When the first data are continuous data, the memory management circuit 702 writes the first data into a plurality of physical erase units (also referred to as first physical erase units) in a single page programming mode, and records management information (also referred to as first management information) corresponding to the first physical erase units. In an embodiment, the first management information may be used to record an order of the first data with respect to each other. In another embodiment, in the operation of recording the first management information, the memory management circuit 702 further marks the first physically erased cells with a first flag (e.g. bit value "1") to indicate that consecutive first data are stored in the first physically erased cells. However, the invention is not limited thereto, and in other embodiments, the memory management circuit 702 may record the binding relationship of the first entity erasure units into a lookup table.

When the first data are not consecutive data, the memory management circuit 702 writes the first data into a plurality of physically erased cells (also referred to as second physically erased cells) in a single page programming mode. In one embodiment, the memory management circuit 702 may not record the management information corresponding to the second physically erased cell. Alternatively, in other embodiments, the memory management circuit 702 may mark the second physically erased cells with a second flag (e.g., bit value "0") to indicate that the second physically erased cells store discontinuous data.

The following describes a detailed process of writing a plurality of continuous data into the rewritable nonvolatile memory module 406 by way of example.

FIG. 9 is a diagram illustrating writing data to a rewritable nonvolatile memory module using a single page programming mode according to an example.

Referring to fig. 9, when the memory storage device 10 receives a plurality of write commands (also referred to as first write commands) from the host system 11 indicating to store the update data to the 0 th to 257 th logical sub-units of the logical unit LBA (0), the memory management circuit 702 determines that the logical addresses of the update data of the first write commands are consecutive. In the present exemplary embodiment, the memory management circuit 702 extracts 3 physical erase units 510(F +1), 510(F +2), 510(F +3) (i.e., the first physical erase unit) from the idle area 504 as a plurality of active physical erase units corresponding to the first write command. Assuming that the memory management circuit 702 is programmed in the single page programming mode, the memory management circuit 702 writes the data of the first write command from the buffer memory 710 to the physical program cells of the physical erase cells 510(F +1), 510(F +2), and 510(F +3) according to the first command sequence. Here, since the physical program cells of the physical erase cells 510(F +1), 510(F +2), and 510(F +3) are programmed in the single page program mode, the memory cells of the physical program cells constituting the physical erase cells 510(F +1), 510(F +2), and 510(F +3) are programmed to store 1 bit of data, as described above. That is, in the single page programming mode, the lower physical program cells of the physically erased cells 510(F +1), 510(F +2), and 510(F +3) are used to write data, and the middle and upper physical program cells of the physically erased cells 510(F +1), 510(F +2), and 510(F +3) are not used to write data.

In detail, as shown in FIG. 9, the memory management circuit 702 sequentially writes the data of 0 th to 257 th logical sub-units to be stored in the logical unit LBA (0) to the next physical program unit of the physical erase units 510(F +1), 510(F +2), and 510(F + 3). That is, the memory management circuit 702 uses the single-page programming mode to write the data corresponding to the first write command from the buffer memory 710 into the lower entity programming cells of the entity erased cells 510(F +1), 510(F +2), and 510(F +3) in the rewritable nonvolatile memory module 406, and the middle entity programming cells and the upper entity programming cells of the entity erased cells 510(F +1), 510(F +2), and 510(F +3) are not used to write the data.

After writing the data corresponding to the first write command from the buffer memory 710 to the next physical program unit of the physical erase units 510(F +1), 510(F +2), and 510(F +3) in the rewritable non-volatile memory module 406 using the single-page programming mode, the memory management circuit 702 associates the physical erase units 510(F +1), 510(F +2), and 510(F +3) with the data area 502, and returns the write completion information to the host system 11 in response to the first write command issued by the host system 11.

In particular, in the present embodiment, since the data written into the physically erased cells 510(F +1), 510(F +2), and 510(F +3) is continuous data, the memory management circuit 702 further records a management information (i.e., the aforementioned first management information) corresponding to the physically erased cells 510(F +1), 510(F +2), and 510(F + 3). In one embodiment, the first management information may be used to record the sequence of the data stored in the physical erase units 510(F +1), 510(F +2), and 510(F + 3). In another embodiment, the memory management circuit 702 also marks the physically erased cells 510(F +1), 510(F +2), and 510(F +3) with a first flag to indicate that consecutive data are stored in the physically erased cells. However, the invention is not limited thereto, and in other embodiments, the memory management circuit 702 may record the binding relationship of the physical erase units 510(F +1), 510(F +2), and 510(F +3) into a lookup table.

FIG. 10 is a diagram illustrating an effective data merge operation for data written in a single page program mode using a multi-page program mode according to an example.

Assuming that the physical erase units 510(F +1), 510(F +2), and 510(F +3) corresponding to the logical unit LBA (0) have stored valid data of all logical sub-units of the logical unit LBA (0) (as shown in FIG. 9), the memory management circuit 702 performs a valid data merge operation when the memory storage device 10 is in a background execution mode, such as the memory storage device 10 is in an idle state for a period of time (e.g., 30 seconds has not received commands from the host system 11 (e.g., write commands, read commands, flush commands, trim commands (trim command), etc.)) or when the number of empty physical erase units in the idle area 504 is less than a predetermined threshold value.

In detail, the memory management circuit 702 performs the valid data merge operation when the memory storage device 10 is idle and does not receive a command from the host system 11 for 30 seconds, or when the number of empty physical erase units in the idle area 504 is smaller than a predetermined threshold. Referring to FIG. 10, when the memory management circuit 702 performs the valid data merge operation, the memory management circuit 702 extracts a physical erase unit from the idle region 604 as a physical erase unit 510(F +4) for rotation (hereinafter, referred to as a third physical erase unit). Specifically, the memory management circuit 702 selects an empty physical erase cell or a physical erase cell with invalid data stored therein from the idle region 604. In particular, if the extracted physical erase cell is a physical erase cell storing invalid data, the memory management circuit 702 performs an erase operation on the physical erase cell. That is, the invalid data on the physically erased cells must be erased first.

Thereafter, the memory management circuit 702 identifies the physical erase units (e.g., the physical erase units 510(F +1), 510(F +2), 510(F +3)) for storing the sequential data according to the "first management information" recorded previously when the write operation is performed. Taking the solid erase units 510(F +1), 510(F +2), 510(F +3) storing continuous data as an example, the memory management circuit 702 uses the multi-page programming mode to copy the valid data in the solid erase units 510(F +1), 510(F +2), 510(F +3) to the solid program units in the solid erase units 510(F +4) in the rewritable non-volatile memory module 406. Here, since the physically erased cell 510(F +4) is programmed in the multi-page program mode, the memory cell of the physically programmed cell constituting the physically erased cell 510(F +4) is programmed to store a plurality of bits of data, as described above. That is, in the multi-page program mode, the lower, middle and upper physical program cells of the physical erase cell 510(F +4) are used to write data.

In detail, the memory management circuit 702 writes (or copies) the valid data of the 0 th to 85 th logical sub-units belonging to the logical unit LBA (0) from the lower physical program unit of the physical erase unit 510(F +1) to the corresponding page (e.g., 0 th to 85 th physical program units) of the physical erase unit 510(F + 4). Then, the memory management circuit 702 copies the valid data of the 86 th to 171 th logical sub-units belonging to the logical unit LBA (0) from the lower physical program unit of the temporary physical erase unit 510(F +2) to the corresponding page (e.g., the 86 th to 171 th physical program units) of the physical erase unit 510(F + 4). Finally, the memory management circuit 702 copies the valid data of the 172 nd to 257 th logical sub-cells belonging to the logical cell LBA (0) from the lower physical program cell of the temporary physical erase cell 510(F +3) to the corresponding page (e.g., the 172 th to 257 th physical program cells) of the physical erase cell 510(F + 4). That is, in the multi-page programming mode, the 0 th to 257 th physical program cells of the physical erase cell 510(F +4) are all used to write data.

That is, in performing the effective data merge operation, the physical erase cells to be associated with the data region 502 are operated in the multi-page programming mode, and thus, the writing to the physical erase cells 510(F +4) is simultaneously or stepwise programmed in units of the physical program cell group. Specifically, in an exemplary embodiment, the 0 th, 1 th, and 2 nd physical program cells of the physical erase cell 510(F +4) are simultaneously programmed to write data belonging to the 0 th, 1 th, and 2 nd logical sub-cells of the logical cell LBA (0); the 3 rd, 4 th, and 5 th physical programming units of the physical erase unit 510(F +4) are simultaneously programmed to write data belonging to the 3 rd, 4 th, and 5 th logical sub-units of the logical unit LBA (0); and so on, the data of other logical sub-cells are written into the physically erased cell 510(F +4) in units of the physically programmed cell group.

Finally, the memory management circuit 702 maps the logical unit LBA (0) to the physical unit 510(F +4) in the logical-to-physical mapping table, and performs an erase operation on the physical units 510(F +1) -510 (F +3) and re-associates the physical units 510(F +1) -510 (F +3) with the idle area 504. That is, in the following write command, the erased entity-erased units 510(F +1) -510 (F +3) can be selected as the active entity-erased units of the logic units to be written.

Referring to fig. 11, in step S1101, the memory management circuit 702 receives a write command for writing first data into the rewritable nonvolatile memory module 406. In step S1103, the memory management circuit 702 determines whether the first data is continuous data. When the first data is continuous data, in step S1105, the memory management circuit 702 writes the first data into the first plurality of erase units in the single page programming mode, and records the first management information corresponding to the first erase units. When the first data is not continuous data, in step S1107, the memory management circuit 702 writes the first data into a plurality of second physically erased cells respectively in a single page programming mode.

In summary, the data management method, the memory control circuit unit and the memory storage device of the present invention can ensure that a plurality of data stored in the same physical erase unit are mutually continuous after the rewritable nonvolatile memory module performs the valid data merge operation, thereby avoiding the problem of reduced operation performance of the rewritable nonvolatile memory module caused by performing a large number of data merge operations in the prior art.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data management method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and the data management method comprises the following steps:

receiving a write instruction for writing first data into the rewritable nonvolatile memory module;

when the first data is continuous data, respectively writing the first data into a plurality of first entity erasing units in the plurality of entity erasing units in a single-page programming mode, and recording first management information corresponding to the plurality of first entity erasing units; and

and when the first data is not continuous data, respectively writing the first data into a plurality of second entity erasing units in the plurality of entity erasing units in the single-page programming mode.

2. The data management method of claim 1, further comprising:

identifying the first plurality of physically erased cells, which respectively store the first data, from the plurality of physically erased cells according to the first management information; and

copying the first data from the first plurality of physically erased cells and writing the first data into a third physically erased cell of the plurality of physically erased cells in a multi-page programming mode.

3. The data management method of claim 1, further comprising:

judging whether the logic addresses of the first data are continuous or not;

when the logic addresses of the first data are continuous, judging that the first data are continuous data; and

and when the logic address of the first data is discontinuous, judging that the first data is discontinuous.

4. The data management method of claim 1, wherein the step of recording the first management information corresponding to the plurality of first physically erased cells comprises:

recording the order of the first data.

5. The data management method of claim 1, wherein the step of recording the first management information corresponding to the plurality of first physically erased cells comprises:

the plurality of first physically erased cells are marked with first flags.

6. The data management method of claim 1, wherein the step of recording the first management information corresponding to the plurality of first physically erased cells comprises:

and recording the binding relations of the first entity erasing units into a lookup table.

7. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for coupling to a host system;

a memory interface coupled to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of entity erasing units;

memory management circuitry coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to receive a write command for writing first data into the rewritable non-volatile memory module,

when the first data is continuous data, the memory management circuit is further configured to write the first data into a plurality of first physically erased cells of the plurality of physically erased cells in a single-page programming mode, respectively, and record first management information corresponding to the plurality of first physically erased cells,

when the first data is not continuous data, the memory management circuit is further configured to write the first data into a plurality of second physically erased cells of the plurality of physically erased cells in the single page programming mode, respectively.

8. The memory control circuit cell of claim 7, wherein

The memory management circuit is further configured to identify the first plurality of physically erased cells respectively storing the first data from the plurality of physically erased cells according to the first management information,

the memory management circuit is further configured to copy the first data from the plurality of first physically erased cells and write the first data into a third physically erased cell of the plurality of physically erased cells in a multi-page programming mode.

9. The memory control circuit cell of claim 7, wherein

The memory management circuit is further configured to determine whether logical addresses of the first data are consecutive,

when the logical addresses of the first data are consecutive, the memory management circuit is further configured to determine that the first data are consecutive data,

when the logical address of the first data is discontinuous, the memory management circuit is further configured to determine that the first data is discontinuous.

10. The memory control circuit unit according to claim 7, wherein in the operation of recording the first management information corresponding to the plurality of first physically erased cells,

the memory management circuit is also used for recording the sequence of the first data.

11. The memory control circuit unit according to claim 7, wherein in the operation of recording the first management information corresponding to the plurality of first physically erased cells,

the memory management circuit is also configured to mark the plurality of first physically erased cells with a first flag.

12. The memory control circuit unit according to claim 7, wherein in the operation of recording the first management information corresponding to the plurality of first physically erased cells,

the memory management circuit is further configured to record the binding relationship of the first entity erasure units into a lookup table.

13. A memory storage device, comprising:

a connection interface unit for coupling to a host system;

the memory module comprises a rewritable nonvolatile memory module, a first memory module and a second memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units; and

a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for receiving a write command for writing first data into the rewritable non-volatile memory module,

when the first data is continuous data, the memory control circuit unit is further configured to write the first data into a plurality of first physically erased cells of the plurality of physically erased cells in a single-page programming mode, and record first management information corresponding to the plurality of first physically erased cells, and

when the first data is not continuous data, the memory control circuit unit is further configured to write the first data into a plurality of second physically erased cells of the plurality of physically erased cells in the single page programming mode, respectively.

14. The memory storage device of claim 13, wherein

The memory control circuit unit is further configured to identify the first plurality of physically erased cells respectively storing the first data from the plurality of physically erased cells according to the first management information,

the memory control circuit unit is further configured to copy the first data from the plurality of first physically erased cells and write the first data into a third physically erased cell of the plurality of physically erased cells in a multi-page programming mode.

15. The memory storage device of claim 13, wherein

The memory control circuit unit is further configured to determine whether the logical addresses of the first data are consecutive,

when the logical addresses of the first data are consecutive, the memory control circuit unit is further configured to determine that the first data are consecutive data,

when the logical address of the first data is discontinuous, the memory control circuit unit is further configured to determine that the first data is discontinuous.

16. The memory storage device of claim 13, wherein in the operation of recording the first management information corresponding to the plurality of first physically erased cells,

the memory control circuit unit is further used for recording the sequence of the first data.

17. The memory storage device of claim 13, wherein in the operation of recording the first management information corresponding to the plurality of first physically erased cells,

the memory control circuit unit is also used for marking the plurality of first physically erased units by using a first flag.

18. The memory storage device of claim 13, wherein in the operation of recording the first management information corresponding to the plurality of first physically erased cells,

the memory control circuit unit is further configured to record the binding relationship of the first entity erasing units into a lookup table.