TWI582902B - Substrate structure and manufacturing method thereof - Google Patents

Substrate structure and manufacturing method thereof Download PDF

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TWI582902B
TWI582902B TW104122878A TW104122878A TWI582902B TW I582902 B TWI582902 B TW I582902B TW 104122878 A TW104122878 A TW 104122878A TW 104122878 A TW104122878 A TW 104122878A TW I582902 B TWI582902 B TW I582902B
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layer
dielectric material
metal
conductive pillar
material layer
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TW104122878A
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TW201703196A (en
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許詩濱
許哲瑋
劉晉銘
楊智貴
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恆勁科技股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Description

基板結構及其製作方法 Substrate structure and manufacturing method thereof

本發明係關於一種基板結構及其製作方法。更詳細地說,本發明係關於一種半導體基板結構及其製作方法。 The present invention relates to a substrate structure and a method of fabricating the same. More specifically, the present invention relates to a semiconductor substrate structure and a method of fabricating the same.

在新一代的電子產品中,使用者不但追求更輕薄短小,更要求其具有多功能以及高性能。因此,電子產品製造商必須在積體電路(integrated circuit;IC)之有限的區域中,容納更多電子元件以達成高密度與微型化之要求。據此,電子產品製造商開發了新型封裝技術,將電子元件埋入基板中,進而大幅縮小積體電路的封裝體積,亦縮短電子元件與基板的連接路徑。此外,電子產品製造商使用增層技術(build-up)增加佈線面積,以符合電子產品之輕薄短小與多功能的趨勢。 In a new generation of electronic products, users are not only pursuing thinner and lighter, but also demanding versatility and high performance. Therefore, electronics manufacturers must accommodate more electronic components in a limited area of an integrated circuit (IC) to achieve high density and miniaturization requirements. Accordingly, electronics manufacturers have developed new packaging technologies that embed electronic components in the substrate, thereby significantly reducing the package size of the integrated circuit and shortening the connection path between the electronic components and the substrate. In addition, electronics manufacturers use build-up to increase cabling area to meet the trend of thin, light, and versatile electronics.

在高階技術的需求下,大部分高階晶片係採用覆晶封裝(flip chip;FC)製作而成。進一步來說,一種稱為晶片尺寸封裝(chip scale package;CSP)的方式更是目前主要應用於需要高頻/高速運作與輕薄短小之主流產品(例如,智慧型行動電話、平板電腦、筆記型電腦或微型數位相機等產品)的封裝技術。而對於封裝用的基板來說,則朝向細密線路間距、高密度、薄型化、低成本化以及高電氣特性發展。 Under the demand of high-end technology, most high-order chips are fabricated by flip chip (FC). Further, a method called chip scale package (CSP) is currently mainly used in mainstream products that require high-frequency/high-speed operation and light and short (eg, smart mobile phones, tablets, notebooks). Packaging technology for products such as computers or micro-digital cameras. On the other hand, the substrate for packaging is developed toward fine wiring pitch, high density, thinness, low cost, and high electrical characteristics.

一般使用玻璃纖維作為需大幅薄型化之基板結構中,玻璃纖維之成本過高,其剛性與散熱性不若金屬材料而使得含有玻璃纖維之基板容易產生翹曲變形,且含有玻璃纖維之基板的雷射鑽孔難度亦隨之增加,進而造成雷射鑽孔之孔型不佳而無法滿足細密線路的佈線要求。同時,反覆使用雷射鑽孔技術來形成雷射盲孔之疊層結構的加工時間長且製程複雜,因而使得含有 玻璃纖維之基板結構不具產業優勢。 Generally, glass fiber is used as a substrate structure which is required to be greatly thinned, and the cost of the glass fiber is too high, and the rigidity and heat dissipation are not as good as the metal material, so that the substrate containing the glass fiber is easily warped and the substrate containing the glass fiber is used. The difficulty of laser drilling has also increased, which in turn has resulted in poor hole diameters for laser drilling and cannot meet the wiring requirements of fine wiring. At the same time, the use of laser drilling technology to form a laminated structure of laser blind holes has a long processing time and a complicated process, thus making it contain The substrate structure of glass fiber does not have industrial advantages.

因此,電子產品製造商在基板結構中使用金屬材料來作為基板,以改善前述使用玻璃纖維作為基板的基板結構的缺陷。然而,由於金屬材料的導電性因素,因此在使用金屬材料之基板的疊層結構中,需要考量各層間之通孔的絕緣設計,而增加製程的複雜程度。此外,使用金屬材料之基板需在同一層結構中同時使用雷射鑽孔技術來形成雷射盲孔並使用機械鑽孔技術來形成通孔,如此一來將因對位誤差所產生的偏移而無法滿足細密線路的佈線要求。 Therefore, the electronic product manufacturer uses a metal material as a substrate in the substrate structure to improve the aforementioned defect of the substrate structure using the glass fiber as the substrate. However, due to the conductivity of the metal material, in the laminated structure of the substrate using the metal material, it is necessary to consider the insulation design of the via holes between the layers, which increases the complexity of the process. In addition, the substrate using the metal material needs to use the laser drilling technique in the same layer structure to form the laser blind hole and use the mechanical drilling technique to form the through hole, so that the offset due to the alignment error is generated. It cannot meet the wiring requirements of fine lines.

有鑑於此,如何提供一種具有剛性與散熱性且滿足細密線路間距、高密度、薄型化、低成本化以及高電氣特性的基板結構,乃是業界亟待解決的問題。 In view of this, how to provide a substrate structure having rigidity and heat dissipation and satisfying fine line pitch, high density, thinness, low cost, and high electrical characteristics is an urgent problem to be solved in the industry.

本發明之一目的在於提供一種基板結構。該基板結構包含一介電材料層、一第一導線層、一第二導線層、一金屬核心層、一第一導電柱層以及一第二導電柱層。該第一導線層以及該第二導線層分別設置於該介電材料層之一第一表面以及一第二表面。該金屬核心層嵌設於該介電材料層內,其具有至少一金屬塊。該第一導電柱層嵌設於該介電材料層內並設置於該金屬核心層以及該第一導線層之間,其具有至少一導電柱。該第二導電柱層嵌設於該介電材料層內並設置於該金屬核心層以及該第二導線層之間,其具有至少一導電柱。該至少一金屬塊具有一第一端以及相對於該第一端之一第二端。該第一端以及該第二端分別電性連接該第一導電柱層之至少一導電柱以及該第二導電柱層之至少一導電柱,且該第一端之一寬度與該第二端之一寬度不同。 It is an object of the present invention to provide a substrate structure. The substrate structure comprises a dielectric material layer, a first wire layer, a second wire layer, a metal core layer, a first conductive pillar layer and a second conductive pillar layer. The first wire layer and the second wire layer are respectively disposed on one of the first surface and the second surface of the dielectric material layer. The metal core layer is embedded in the dielectric material layer and has at least one metal block. The first conductive pillar layer is embedded in the dielectric material layer and disposed between the metal core layer and the first wire layer, and has at least one conductive pillar. The second conductive pillar layer is embedded in the dielectric material layer and disposed between the metal core layer and the second wire layer, and has at least one conductive pillar. The at least one metal block has a first end and a second end opposite the first end. The first end and the second end are respectively electrically connected to at least one conductive pillar of the first conductive pillar layer and at least one conductive pillar of the second conductive pillar layer, and one of the first end has a width and the second end One of the widths is different.

本發明之另一目的在於提供一種基板結構之製作方法。該製作方法包括下列步驟:提供一金屬板;蝕刻該金屬板以形成一金屬核心層,其中,該金屬核心層具有複數個金屬塊以及至少一耦接塊,該等金屬塊分別具有一第一端以及相對於該第一端之一第二端,且該等金屬塊藉由該至少一耦接塊部份地耦接; 形成一介電材料層於該至少一耦接塊以及該等金屬塊上;蝕刻該金屬核心層以移除該至少一耦接塊,並使該第一端之一寬度與該第二端之一寬度不同;形成該介電材料層於該等金屬塊上,使該介電材料層包覆該金屬核心層;露出該等金屬塊其中之一之第一端以及第二端;形成一第一導電柱層於該等金屬塊其中之一之第一端上;形成一第二導電柱層於該等金屬塊其中之一之第二端上;形成一第一導線層於該介電材料層之一第一表面上;以及形成一第二導線層於該介電材料層之一第二表面上。 Another object of the present invention is to provide a method of fabricating a substrate structure. The manufacturing method includes the following steps: providing a metal plate; etching the metal plate to form a metal core layer, wherein the metal core layer has a plurality of metal blocks and at least one coupling block, the metal blocks respectively having a first And the second end of the first end, and the metal blocks are partially coupled by the at least one coupling block; Forming a dielectric material layer on the at least one coupling block and the metal blocks; etching the metal core layer to remove the at least one coupling block, and widthing one of the first ends and the second end Forming the dielectric material layer on the metal blocks to cover the metal core layer; exposing the first end and the second end of one of the metal blocks; forming a first a conductive pillar layer on the first end of one of the metal blocks; forming a second conductive pillar layer on the second end of one of the metal blocks; forming a first wire layer on the dielectric material And constituting a second wire layer on one of the second surfaces of the dielectric material layer.

本發明之又一目的在於提供一種基板結構。該基板結構包含一介電材料層、至少一導線層、一金屬核心層以及至少一導電柱層。該至少一導線層設置於該介電材料層之一表面。該金屬核心層嵌設於該介電材料層內,其具有至少一金屬塊。該導電柱層嵌設於該介電材料層內並設置於該金屬核心層以及該至少一導線層之間。該至少一金屬塊具有一第一端以及相對於該第一端之一第二端。該第一端以及該第二端其中之一電性連接該至少一導電柱層,且該第一端之一寬度與該第二端之一寬度不同。 It is still another object of the present invention to provide a substrate structure. The substrate structure comprises a dielectric material layer, at least one wire layer, a metal core layer and at least one conductive pillar layer. The at least one wire layer is disposed on a surface of the dielectric material layer. The metal core layer is embedded in the dielectric material layer and has at least one metal block. The conductive pillar layer is embedded in the dielectric material layer and disposed between the metal core layer and the at least one wire layer. The at least one metal block has a first end and a second end opposite the first end. One of the first end and the second end is electrically connected to the at least one conductive pillar layer, and one of the first ends has a width different from a width of one of the second ends.

綜上所述,本發明之基板結構及其製作方法係利用金屬材料之基板來取代含有玻璃纖維之基板,同時,以較簡易的製作流程形成金屬核心層、導電柱層與導線層,並取代傳統之使用雷射鑽孔技術來形成雷射盲孔並使用機械鑽孔技術來形成通孔之流程。據此,本發明之基板結構及其製作方法可達成細密線路的佈線要求,以縮小基板尺寸,同時增加電性與訊號穩定性,以滿足高電氣特性,並兼具剛性與散熱性。如此一來,將可縮短基板結構之加工時間並大幅降低製作成本。 In summary, the substrate structure and the manufacturing method thereof of the present invention replace the substrate containing the glass fiber by using the substrate of the metal material, and at the same time, form the metal core layer, the conductive pillar layer and the wire layer in a relatively simple manufacturing process, and replace Traditionally, laser drilling techniques have been used to form laser blind holes and mechanical drilling techniques have been used to form the vias. Accordingly, the substrate structure and the manufacturing method thereof of the present invention can achieve the wiring requirements of the fine lines, thereby reducing the substrate size, increasing the electrical and signal stability, and satisfying the high electrical characteristics, and having both rigidity and heat dissipation. As a result, the processing time of the substrate structure can be shortened and the manufacturing cost can be greatly reduced.

在參閱圖式及隨後描述之實施方式後,所屬技術領域具有通常知識者便可瞭解本發明之其它目的、優點以及本發明之技術手段及實施態樣。 Other objects, advantages, and technical means and embodiments of the present invention will become apparent to those skilled in the <RTIgt;

10、20‧‧‧基板結構 10, 20‧‧‧ substrate structure

101‧‧‧介電材料層 101‧‧‧ dielectric material layer

1011‧‧‧第一表面 1011‧‧‧ first surface

1013‧‧‧第二表面 1013‧‧‧ second surface

103‧‧‧第一導線層 103‧‧‧First wire layer

105‧‧‧第二導線層 105‧‧‧Second wire layer

107A、107B、107C、107D‧‧‧金屬塊 107A, 107B, 107C, 107D‧‧‧ metal blocks

109‧‧‧內接元件 109‧‧‧Internal components

1091‧‧‧導電極層 1091‧‧‧conductive electrode layer

111‧‧‧第一導電柱層 111‧‧‧First conductive column

113‧‧‧第二導電柱層 113‧‧‧Second conductive column

201‧‧‧第三導電柱層 201‧‧‧ Third conductive column

203‧‧‧第四導電柱層 203‧‧‧fourth conductive pillar

205A、205B‧‧‧環氧鑄模化合物層 205A, 205B‧‧‧epoxy mold compound layer

401‧‧‧金屬板 401‧‧‧Metal plate

403A、403B‧‧‧耦接塊 403A, 403B‧‧‧ coupling block

第1圖係為本發明之第一實施例之基板結構之示意圖。 Fig. 1 is a schematic view showing the structure of a substrate according to a first embodiment of the present invention.

第2圖係為本發明之第二實施例之基板結構之示意圖。 Fig. 2 is a schematic view showing the structure of a substrate of a second embodiment of the present invention.

第3圖係為本發明之第三實施例之基板結構之製作方法之流程圖。 Fig. 3 is a flow chart showing a method of fabricating a substrate structure according to a third embodiment of the present invention.

第4A圖至第4I圖係為本發明之第三實施例之基板結構之製作示意圖。 4A to 4I are schematic views showing the fabrication of the substrate structure of the third embodiment of the present invention.

第5圖係為形成介電材料層之流程圖。 Figure 5 is a flow chart for forming a layer of dielectric material.

第6圖係為本發明之第四實施例之基板結構之製作方法之流程圖。 Fig. 6 is a flow chart showing a method of fabricating a substrate structure according to a fourth embodiment of the present invention.

第7A圖至第7D圖係為本發明之第四實施例之基板結構之製作示意圖。 7A to 7D are views showing the fabrication of the substrate structure of the fourth embodiment of the present invention.

以下將透過實施例來解釋本發明內容,本發明的實施例並非用以限制本發明須在如實施例所述之任何特定的環境、應用或特殊方式方能實施。因此,關於實施例之說明僅為闡釋本發明之目的,而非用以限制本發明。須說明者,以下實施例及圖式中,與本發明非直接相關之元件已省略而未繪示;且圖式中各元件間之尺寸關係僅為求容易瞭解,非用以限制實際比例。 The present invention is not limited by the embodiment, and the embodiment of the present invention is not intended to limit the invention to any specific environment, application or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that, in the following embodiments and drawings, components that are not directly related to the present invention have been omitted and are not shown; and the dimensional relationships between the components in the drawings are merely for ease of understanding and are not intended to limit the actual ratio.

本發明之第一實施例如第1圖所示,係為一基板結構10之示意圖。基板結構10包含一介電材料層101、一第一導線層103、一第二導線層105、一金屬核心層、一第一導電柱層111、一第二導電柱層113以及一內接元件109。介電材料層101具有一第一表面1011以及一第二表面1013。金屬核心層具有複數個金屬塊107A、107B、107C、107D。第一導電柱層111以及第二導電柱層113分別具有複數個導電柱。內接元件109更包含一導電極層1091。 A first embodiment of the present invention, as shown in FIG. 1, is a schematic view of a substrate structure 10. The substrate structure 10 includes a dielectric material layer 101, a first wire layer 103, a second wire layer 105, a metal core layer, a first conductive pillar layer 111, a second conductive pillar layer 113, and an inscribed component. 109. The dielectric material layer 101 has a first surface 1011 and a second surface 1013. The metal core layer has a plurality of metal blocks 107A, 107B, 107C, 107D. The first conductive pillar layer 111 and the second conductive pillar layer 113 respectively have a plurality of conductive pillars. The internal component 109 further includes a conductive electrode layer 1091.

介電材料層101係為一鑄模化合物(Molding Compound)層,其具有酚醛基樹脂(Novolac-based Resin)、環氧基樹脂(Epoxy-based Resin)、矽基樹脂(Silicone-based Resin)或其它適當之鑄模化合物,但不以此為限。此外,在本實施例中,金屬核心層具有四個金屬塊107A、107B、107C、107D。然而,在其它實施例中,依據基板結構10之不同用途與類型,金屬核心層 可具有任意數目之金屬塊,並不以本實施例所述之四個金屬塊107A、107B、107C、107D為限。類似地,在本實施例中,第一導電柱層111具有六個導電柱;第二導電柱層113具有二個導電柱。然而,在其它實施例中,依據基板結構10之不同用途與類型,第一導電柱層111以及第二導電柱層113可分別具有任意數目之導電柱,並不以本實施例所述之導電柱的數量為限。 The dielectric material layer 101 is a Molding Compound layer having a Novolac-based Resin, an Epoxy-based Resin, a Silicone-based Resin or the like. Suitable mold compounds, but not limited to this. Further, in the present embodiment, the metal core layer has four metal blocks 107A, 107B, 107C, 107D. However, in other embodiments, depending on the use and type of substrate structure 10, the metal core layer There may be any number of metal blocks, and is not limited to the four metal blocks 107A, 107B, 107C, 107D described in this embodiment. Similarly, in the present embodiment, the first conductive pillar layer 111 has six conductive pillars; the second conductive pillar layer 113 has two conductive pillars. However, in other embodiments, the first conductive pillar layer 111 and the second conductive pillar layer 113 may have any number of conductive pillars respectively according to different uses and types of the substrate structure 10, and are not electrically conductive as described in this embodiment. The number of columns is limited.

金屬塊107A具有寬度為X1之一第一端以及相對於第一端之寬度為Y1之一第二端。類似地,金屬塊107B有寬度為X2之一第一端以及相對於第一端之寬度為Y2之一第二端。金屬塊107C具有寬度為X3之一第一端以及相對於第一端之寬度為Y3之一第二端。金屬塊107D具有寬度為X4之一第一端以及相對於第一端之寬度為Y4之一第二端。金屬塊107B、107D之第一端X2、X4電性連接第一導電柱層111之導電柱;金屬塊107B、107D之第二端Y2、Y4電性連接第二導電柱層113之導電柱。 The metal block 107A has a first end having a width X1 and a second end having a width Y1 with respect to the first end. Similarly, metal block 107B has a first end having a width X2 and a second end having a width Y2 relative to the first end. The metal block 107C has a first end having a width X3 and a second end having a width Y3 with respect to the first end. The metal block 107D has a first end having a width X4 and a second end having a width Y4 with respect to the first end. The first ends X2 and X4 of the metal blocks 107B and 107D are electrically connected to the conductive pillars of the first conductive pillar layer 111; the second ends Y2 and Y4 of the metal blocks 107B and 107D are electrically connected to the conductive pillars of the second conductive pillar layer 113.

在本實施例中,金屬塊107A之第二端之寬度Y1大於第一端之寬度X1;金屬塊107B之第二端之寬度Y2大於第一端之寬度X2;金屬塊107C之第二端之寬度Y3大於第一端之寬度X3;金屬塊107D之第二端之寬度Y4與第一端之寬度X4約略相同。換句話說,金屬塊107A、107B、107C之第一端之寬度X1、X2、X3分別與第二端之寬度Y1、Y2、Y3不同。 In this embodiment, the width Y1 of the second end of the metal block 107A is greater than the width X1 of the first end; the width Y2 of the second end of the metal block 107B is greater than the width X2 of the first end; the second end of the metal block 107C The width Y3 is greater than the width X3 of the first end; the width Y4 of the second end of the metal block 107D is approximately the same as the width X4 of the first end. In other words, the widths X1, X2, and X3 of the first ends of the metal blocks 107A, 107B, and 107C are different from the widths Y1, Y2, and Y3 of the second end, respectively.

第一導電柱層111嵌設於介電材料層101內,並設置於金屬核心層以及第一導線層103之間;同時,第一導電柱層111電性連接金屬核心層以及第一導線層103。類似地,第二導電柱層113嵌設於介電材料層101內,並設置於金屬核心層以及第二導線層105之間;同時,第二導電柱層113電性連接金屬核心層以及第二導線層105。 The first conductive pillar layer 111 is embedded in the dielectric material layer 101 and disposed between the metal core layer and the first conductive layer 103. Meanwhile, the first conductive pillar layer 111 is electrically connected to the metal core layer and the first conductive layer 103. Similarly, the second conductive pillar layer 113 is embedded in the dielectric material layer 101 and disposed between the metal core layer and the second conductive layer 105. Meanwhile, the second conductive pillar layer 113 is electrically connected to the metal core layer and Two wire layers 105.

金屬塊107A、107B、107C、107D以及內接元件109嵌設於介電材料層101內。第一導線層103設置於介電材料層101之第一表面1011。第二導線層105則設置於介電材料層101之第二表面1013。此外,金屬塊107A、107B、107C、107D設置於第一導電 柱層111以及第二導電柱層113之間。在本實施例中,內接元件109之導電極層1091電性連接第一導電柱層111。然而,在其它實施例中,內接元件109之導電極層1091可因應擺放位置的不同而電性連接第二導電柱層113,並不以本實施例所述之電性連接第一導電柱層111為限。 The metal blocks 107A, 107B, 107C, 107D and the inscribed element 109 are embedded in the dielectric material layer 101. The first wire layer 103 is disposed on the first surface 1011 of the dielectric material layer 101. The second wire layer 105 is disposed on the second surface 1013 of the dielectric material layer 101. In addition, the metal blocks 107A, 107B, 107C, 107D are disposed on the first conductive Between the pillar layer 111 and the second conductive pillar layer 113. In this embodiment, the conductive electrode layer 1091 of the interconnecting component 109 is electrically connected to the first conductive pillar layer 111. However, in other embodiments, the conductive layer 1091 of the inscribed component 109 can be electrically connected to the second conductive pillar layer 113 according to the position of the placement, and is not electrically connected to the first conductive layer as described in this embodiment. The column layer 111 is limited.

本發明之第二實施例如第2圖所示,係為一基板結構20之示意圖。基板結構20之一結構類似於本發明之第一實施例所述之基板結構10之結構,其差異在於基板結構20更包含一第三導電柱層201、一第四導電柱層203以及二環氧鑄模化合物層205A、205B。第三導電柱層201部份地電性連接第一導線層103,並設置於環氧鑄模化合物層205A內。第四導電柱層203部份地電性連接第二導線層105,並設置於環氧鑄模化合物層205B內。環氧鑄模化合物層205A包覆第一導線層103;環氧鑄模化合物層205B包覆第二導線層105。 A second embodiment of the present invention, as shown in FIG. 2, is a schematic view of a substrate structure 20. The structure of the substrate structure 20 is similar to the structure of the substrate structure 10 of the first embodiment of the present invention. The difference is that the substrate structure 20 further includes a third conductive pillar layer 201, a fourth conductive pillar layer 203, and a second ring. Oxygen mold compound layers 205A, 205B. The third conductive pillar layer 201 is partially electrically connected to the first wiring layer 103 and disposed in the epoxy mold compound layer 205A. The fourth conductive pillar layer 203 is partially electrically connected to the second wiring layer 105 and disposed in the epoxy mold compound layer 205B. The epoxy mold compound layer 205A coats the first wire layer 103; the epoxy mold compound layer 205B covers the second wire layer 105.

需說明的是,前段所述之基板結構10、20皆包含二個導線層,且其導線層分別電性連接導電柱層之導電柱。然而,在其它實施例中,基板結構10、20可僅包含一個導線層,且其導線層電性連接導電柱層之導電柱。所屬技術領域具有通常知識者可透過前述之說明了解基板結構10、20之導線層的數量以及導線層電性連接導電柱層之導電柱的方式,故在此不再贅述。 It should be noted that the substrate structures 10 and 20 described in the preceding paragraph each include two wire layers, and the wire layers are electrically connected to the conductive pillars of the conductive pillar layer. However, in other embodiments, the substrate structures 10, 20 may comprise only one wire layer, and the wire layers thereof are electrically connected to the conductive pillars of the conductive pillar layer. Those skilled in the art can understand the number of the wire layers of the substrate structures 10 and 20 and the manner in which the wire layers are electrically connected to the conductive pillars of the conductive pillar layer through the foregoing description, and thus will not be described herein.

本發明之第三實施例如第3圖所示,其係為一種基板結構之製作方法之流程圖。本實施例所述之製作方法可用於製作一基板結構,例如:第一實施例所述基板結構10。以下將透過第3圖以及第4A圖至第4I圖進一步說明本實施例之基板結構之製作方法的步驟。 A third embodiment of the present invention is shown in FIG. 3, which is a flow chart of a method of fabricating a substrate structure. The fabrication method described in this embodiment can be used to fabricate a substrate structure, such as the substrate structure 10 of the first embodiment. The steps of the method of fabricating the substrate structure of the present embodiment will be further described below through FIG. 3 and FIGS. 4A to 4I.

首先,於步驟301中,提供如第4A圖繪示之一金屬板401。其中,金屬板401係由鋁、銅、不銹鋼或其組合製成之一金屬板。 First, in step 301, a metal plate 401 is provided as shown in FIG. 4A. Among them, the metal plate 401 is a metal plate made of aluminum, copper, stainless steel or a combination thereof.

接著,於步驟303中,蝕刻金屬板401以形成如第4B圖繪示之一金屬核心層。其中,金屬核心層具有複數個金屬塊 107A、107B、107C、107D以及二耦接塊403A、403B。金屬塊107A、107B、107C、107D分別具有一第一端以及相對於第一端之一第二端。同時,金屬塊107A與金屬塊107B藉由耦接塊403A部份地耦接;金屬塊107B與金屬塊107C藉由耦接塊403B部份地耦接。 Next, in step 303, the metal plate 401 is etched to form a metal core layer as shown in FIG. 4B. Wherein the metal core layer has a plurality of metal blocks 107A, 107B, 107C, 107D and two coupling blocks 403A, 403B. The metal blocks 107A, 107B, 107C, 107D each have a first end and a second end opposite the first end. At the same time, the metal block 107A and the metal block 107B are partially coupled by the coupling block 403A; the metal block 107B and the metal block 107C are partially coupled by the coupling block 403B.

於步驟305中,如第4C圖所示,將內接元件109放置於金屬塊107C與金屬塊107D之間。其中,內接元件109包含一導電極層1091。接著,於步驟307中,如第4D圖所示,形成一介電材料層101於耦接塊403A、403B以及金屬塊107A、107B、107C、107D上。 In step 305, as shown in FIG. 4C, the inscribed element 109 is placed between the metal block 107C and the metal block 107D. The internal component 109 includes a conductive electrode layer 1091. Next, in step 307, as shown in FIG. 4D, a dielectric material layer 101 is formed on the coupling blocks 403A, 403B and the metal blocks 107A, 107B, 107C, 107D.

於步驟309中,如第4E圖所示,蝕刻金屬核心層以移除耦接塊403A、403B,並分別使金屬塊107A、107B、107C之第一端之一寬度與第二端之一寬度不同。詳細來說,金屬塊107A之第二端之寬度Y1大於第一端之寬度X1;金屬塊107B之第二端之寬度Y2大於第一端之寬度X2;金屬塊107C之第二端之寬度Y3大於第一端之寬度X3。 In step 309, as shown in FIG. 4E, the metal core layer is etched to remove the coupling blocks 403A, 403B, and the width of one of the first ends of the metal blocks 107A, 107B, 107C and the width of one of the second ends, respectively. different. In detail, the width Y1 of the second end of the metal block 107A is greater than the width X1 of the first end; the width Y2 of the second end of the metal block 107B is greater than the width X2 of the first end; and the width Y3 of the second end of the metal block 107C Greater than the width X3 of the first end.

於步驟311中,如第4F圖所示,形成介電材料層101於金屬塊107A、107B、107C、107D上,使介電材料層101包覆金屬核心層之金屬塊107A、107B、107C、107D。於步驟313中,如第4G圖所示,露出導電極層1091並選擇性地露出金屬塊107A、107B、107C、107D之第一端以及第二端。其中,步驟313係露出金屬塊107B、107D第一端以及第二端。 In step 311, as shown in FIG. 4F, a dielectric material layer 101 is formed on the metal blocks 107A, 107B, 107C, and 107D, and the dielectric material layer 101 is coated with the metal core layers 107A, 107B, and 107C of the metal core layer. 107D. In step 313, as shown in FIG. 4G, the conductive electrode layer 1091 is exposed and the first end and the second end of the metal blocks 107A, 107B, 107C, and 107D are selectively exposed. Wherein, step 313 exposes the first end and the second end of the metal blocks 107B, 107D.

於步驟315中,如第4H圖所示,形成一第一導電柱層111於導電極層1091與已露出第一端之金屬塊107B、107D上;並形成一第一導線層103於介電材料層101之一第一表面1011上。詳細來說,第一導電柱層111係形成於金屬塊107A、107B、107C、107D其中之一之第一端上。最後,於步驟317中,如第4I圖所示,形成一第二導電柱層113於已露出第二端之金屬塊107B、107D上;並形成一第二導線層105於介電材料層101之一第二表面1013上。詳細來說,第二導電柱層113係形成於金屬塊107A、107B、107C、107D其中之一之第二端上。 In step 315, as shown in FIG. 4H, a first conductive pillar layer 111 is formed on the conductive electrode layer 1091 and the metal blocks 107B and 107D having the first end exposed; and a first wiring layer 103 is formed on the dielectric layer. One of the material layers 101 is on the first surface 1011. In detail, the first conductive pillar layer 111 is formed on the first end of one of the metal blocks 107A, 107B, 107C, 107D. Finally, in step 317, as shown in FIG. 4I, a second conductive pillar layer 113 is formed on the metal blocks 107B and 107D having the second end exposed; and a second wiring layer 105 is formed on the dielectric material layer 101. One of the second surfaces 1013. In detail, the second conductive pillar layer 113 is formed on the second end of one of the metal blocks 107A, 107B, 107C, 107D.

此外,於形成介電材料層101於金屬塊107A、107B、107C、107D上之步驟307與步驟311中,更包含如第5圖繪示之步驟。首先,於步驟501中,提供一鑄模化合物。其中,鑄模化合物可為酚醛基樹脂、環氧基樹脂、矽基樹脂或其它適當之鑄模化合物。於步驟503中,加熱鑄模化合物至一液體狀態。接著,於步驟505中,將呈現液體狀態之鑄模化合物注入金屬塊107A、107B、107C、107D上,使呈現液體狀態之鑄模化合物包覆金屬核心層之金屬塊107A、107B、107C、107D。最後,於步驟507中,固化呈現液體狀態之鑄模化合物以形成一鑄模化合物層。換句話說,前述之鑄模化合物層即為介電材料層101。 In addition, in steps 307 and 311 of forming the dielectric material layer 101 on the metal blocks 107A, 107B, 107C, and 107D, the steps as shown in FIG. 5 are further included. First, in step 501, a mold compound is provided. Among them, the mold compound may be a phenolic resin, an epoxy resin, a ruthenium-based resin or other suitable mold compound. In step 503, the mold compound is heated to a liquid state. Next, in step 505, a mold compound exhibiting a liquid state is injected into the metal blocks 107A, 107B, 107C, and 107D, and the mold compound exhibiting a liquid state is coated with the metal blocks 107A, 107B, 107C, and 107D of the metal core layer. Finally, in step 507, the mold compound in a liquid state is solidified to form a mold compound layer. In other words, the aforementioned mold compound layer is the dielectric material layer 101.

本發明之第四實施例如第6圖所示,其係為一種基板結構之製作方法之流程圖。本實施例所述之製作方法可用於製作一基板結構,例如:第二實施例所述基板結構20。其中,第6圖所示之第四實施例之步驟601至步驟617與本發明之第三實施例之步驟301至步驟317相同,故在此不再贅述。以下將透過第6圖以及第7A圖至第7D圖進一步說明本實施例之基板結構之製作方法的後續步驟。 A fourth embodiment of the present invention is shown in Fig. 6, which is a flow chart of a method of fabricating a substrate structure. The fabrication method described in this embodiment can be used to fabricate a substrate structure, such as the substrate structure 20 described in the second embodiment. The steps 601 to 617 of the fourth embodiment shown in FIG. 6 are the same as the steps 301 to 317 of the third embodiment of the present invention, and thus are not described herein again. The subsequent steps of the method of fabricating the substrate structure of the present embodiment will be further described below through FIG. 6 and FIGS. 7A through 7D.

於步驟619中,於第一導線層103上形成如第7A圖繪示之一第三導電柱層201。其中,第三導電柱層201部份地電性連接第一導線層103。於步驟621中,於第二導線層105上形成如第7B圖繪示之一第四導電柱層203。其中,第四導電柱層203部份地電性連接第二導線層105。 In step 619, a third conductive pillar layer 201 as shown in FIG. 7A is formed on the first wire layer 103. The third conductive pillar layer 201 is partially electrically connected to the first conductive layer 103. In step 621, a fourth conductive pillar layer 203 as shown in FIG. 7B is formed on the second wire layer 105. The fourth conductive pillar layer 203 is partially electrically connected to the second conductive layer 105.

接著,於步驟623中,形成如第7C圖繪示之一環氧鑄模化合物層205A。其中,環氧鑄模化合物層205A包覆第一導線層103。最後,於步驟625中,形成如第7D圖繪示之一環氧鑄模化合物層205B。其中,環氧鑄模化合物層205B包覆第二導線層105。 Next, in step 623, an epoxy mold compound layer 205A is formed as shown in FIG. 7C. The epoxy mold compound layer 205A covers the first wire layer 103. Finally, in step 625, an epoxy mold compound layer 205B is formed as shown in FIG. 7D. The epoxy mold compound layer 205B covers the second wire layer 105.

綜上所述,本發明之基板結構及其製作方法係利用金屬材料之基板來取代含有玻璃纖維之基板,同時,以較簡易的製作流程形成金屬核心層、導電柱層與導線層,並取代傳統之使用雷射鑽孔技術來形成雷射盲孔並使用機械鑽孔技術來形成通孔 之流程。據此,本發明之基板結構及其製作方法可達成細密線路的佈線要求,以縮小基板尺寸,同時增加電性與訊號穩定性,以滿足高電氣特性,並兼具剛性與散熱性。如此一來,將可縮短基板結構之加工時間並大幅降低製作成本。 In summary, the substrate structure and the manufacturing method thereof of the present invention replace the substrate containing the glass fiber by using the substrate of the metal material, and at the same time, form the metal core layer, the conductive pillar layer and the wire layer in a relatively simple manufacturing process, and replace Conventional use of laser drilling techniques to form laser blind holes and use mechanical drilling techniques to form vias The process. Accordingly, the substrate structure and the manufacturing method thereof of the present invention can achieve the wiring requirements of the fine lines, thereby reducing the substrate size, increasing the electrical and signal stability, and satisfying the high electrical characteristics, and having both rigidity and heat dissipation. As a result, the processing time of the substrate structure can be shortened and the manufacturing cost can be greatly reduced.

上述之實施例僅用來例舉本發明之實施態樣,以及闡釋本發明之技術特徵,並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍,本發明之權利保護範圍應以申請專利範圍為準。 The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the claims.

10‧‧‧基板結構 10‧‧‧Substrate structure

101‧‧‧介電材料層 101‧‧‧ dielectric material layer

1011‧‧‧第一表面 1011‧‧‧ first surface

1013‧‧‧第二表面 1013‧‧‧ second surface

103‧‧‧第一導線層 103‧‧‧First wire layer

105‧‧‧第二導線層 105‧‧‧Second wire layer

107A、107B、107C、107D‧‧‧金屬塊 107A, 107B, 107C, 107D‧‧‧ metal blocks

109‧‧‧內接元件 109‧‧‧Internal components

1091‧‧‧導電極層 1091‧‧‧conductive electrode layer

111‧‧‧第一導電柱層 111‧‧‧First conductive column

113‧‧‧第二導電柱層 113‧‧‧Second conductive column

Claims (10)

一種基板結構,包含:一介電材料層;一第一導線層,設置於該介電材料層之一第一表面;一第二導線層,設置於該介電材料層之一第二表面;一金屬核心層,其嵌設於該介電材料層內,具有至少一金屬塊;一第一導電柱層,其嵌設於該介電材料層內並設置於該金屬核心層以及該第一導線層之間,具有至少一導電柱;以及一第二導電柱層,其嵌設於該介電材料層內並設置於該金屬核心層以及該第二導線層之間,具有至少一導電柱;其中,該至少一金屬塊具有一第一端以及相對於該第一端之一第二端,該第一端以及該第二端分別電性連接該第一導電柱層之至少一導電柱以及該第二導電柱層之至少一導電柱,且該第一端之一寬度與該第二端之一寬度不同。 A substrate structure comprising: a dielectric material layer; a first wire layer disposed on a first surface of the dielectric material layer; a second wire layer disposed on a second surface of the dielectric material layer; a metal core layer embedded in the dielectric material layer and having at least one metal block; a first conductive pillar layer embedded in the dielectric material layer and disposed on the metal core layer and the first Between the wire layers, having at least one conductive pillar; and a second conductive pillar layer embedded in the dielectric material layer and disposed between the metal core layer and the second wire layer, having at least one conductive pillar Wherein the at least one metal block has a first end and a second end opposite to the first end, the first end and the second end are electrically connected to the at least one conductive post of the first conductive pillar layer respectively And at least one conductive pillar of the second conductive pillar layer, and one of the first ends has a width different from a width of one of the second ends. 如請求項1所述之基板結構,更包含一內接元件,嵌設於該介電材料層內,具有一導電極層,其中,該導電極層電性連接該第一導電柱層以及該第二導電柱層其中之一。 The substrate structure of claim 1, further comprising an inscribed component embedded in the dielectric material layer and having a conductive electrode layer, wherein the conductive electrode layer is electrically connected to the first conductive pillar layer and One of the second conductive pillar layers. 如請求項1所述之基板結構,其中,該第二端之寬度大於該第一端之寬度。 The substrate structure of claim 1, wherein the width of the second end is greater than the width of the first end. 如請求項1所述之基板結構,其中,該介電材料層係為一鑄模化合物(Molding Compound)層,該鑄模化合物層具有酚醛基樹脂(Novolac-based Resin)、環氧基樹脂(Epoxy-based Resin)以及矽基樹脂(Silicone-based Resin)其中之一。 The substrate structure according to claim 1, wherein the dielectric material layer is a Molding Compound layer having a phenolic resin (Novolac-based Resin) and an epoxy resin (Epoxy- Based on Resin) and one of Silicone-based Resin. 一種基板結構之製作方法,包含下列步驟:提供一金屬板;蝕刻該金屬板以形成一金屬核心層,其中,該金屬核心層具有複數個金屬塊以及至少一耦接塊,該等金屬塊分別具有一第一端以及相對於該第一端之一第二端,且該等金屬塊藉由該至少一耦接塊部份地耦接;形成一介電材料層於該至少一耦接塊以及該等金屬塊上; 蝕刻該金屬核心層以移除該至少一耦接塊,並使該第一端之一寬度與該第二端之一寬度不同;形成該介電材料層於該等金屬塊上,使該介電材料層包覆該金屬核心層;露出該等金屬塊其中之一之第一端以及第二端;形成一第一導電柱層於該等金屬塊其中之一之第一端上;形成一第二導電柱層於該等金屬塊其中之一之第二端上;形成一第一導線層於該介電材料層之一第一表面上;以及形成一第二導線層於該介電材料層之一第二表面上。 A method for fabricating a substrate structure, comprising the steps of: providing a metal plate; etching the metal plate to form a metal core layer, wherein the metal core layer has a plurality of metal blocks and at least one coupling block, the metal blocks respectively Having a first end and a second end opposite to the first end, and the metal blocks are partially coupled by the at least one coupling block; forming a dielectric material layer on the at least one coupling block And the metal blocks; Etching the metal core layer to remove the at least one coupling block, and making one of the first ends different in width from one of the second ends; forming the dielectric material layer on the metal blocks to enable the dielectric layer a layer of electrical material covering the metal core layer; exposing the first end and the second end of one of the metal blocks; forming a first conductive pillar layer on the first end of one of the metal blocks; forming a a second conductive pillar layer on the second end of one of the metal blocks; a first wiring layer formed on one of the first surfaces of the dielectric material layer; and a second wiring layer formed on the dielectric material One of the layers is on the second surface. 如請求項5所述之製作方法,其中,形成一介電材料層之步驟更包含下列步驟:提供一鑄模化合物;加熱該鑄模化合物至一液體狀態;將呈現該液體狀態之鑄模化合物注入該等金屬塊之第一端以及第二端,使呈現該液體狀態之鑄模化合物包覆該金屬核心層;以及固化呈現該液體狀態之鑄模化合物以形成一鑄模化合物層。 The method of claim 5, wherein the step of forming a layer of dielectric material further comprises the steps of: providing a mold compound; heating the mold compound to a liquid state; and injecting a mold compound exhibiting the liquid state into the liquid The first end and the second end of the metal block, the mold compound exhibiting the liquid state is coated with the metal core layer; and the mold compound exhibiting the liquid state is cured to form a mold compound layer. 如請求項5所述之製作方法,其中,該金屬板係由鋁、銅、不銹鋼及其組合其中之一製成。 The manufacturing method according to claim 5, wherein the metal plate is made of one of aluminum, copper, stainless steel, and a combination thereof. 如請求項5所述之製作方法,其中,該第二端之寬度大於該第一端之寬度。 The method of claim 5, wherein the width of the second end is greater than the width of the first end. 一種基板結構,包含:一介電材料層;至少一導線層,設置於該介電材料層之一表面;一金屬核心層,其嵌設於該介電材料層內,具有至少一金屬塊;以及至少一導電柱層,其嵌設於該介電材料層內並設置於該金屬核心層以及該至少一導線層之間;其中,該至少一金屬塊具有一第一端以及相對於該第一端之一第二端,該第一端以及該第二端其中之一電性連接該至少一 導電柱層,且該第一端之一寬度與該第二端之一寬度不同。 A substrate structure comprising: a dielectric material layer; at least one wire layer disposed on a surface of the dielectric material layer; a metal core layer embedded in the dielectric material layer, having at least one metal block; And at least one conductive pillar layer embedded in the dielectric material layer and disposed between the metal core layer and the at least one wire layer; wherein the at least one metal block has a first end and opposite to the first a second end of one end, one of the first end and the second end electrically connected to the at least one a conductive pillar layer, and one of the first ends has a width different from a width of one of the second ends. 如請求項9所述之基板結構,更包含一內接元件,嵌設於該介電材料層內,具有一導電極層,其中,該導電極層電性連接該至少一導電柱層。 The substrate structure of claim 9, further comprising an inscribed component embedded in the dielectric material layer and having a conductive electrode layer, wherein the conductive electrode layer is electrically connected to the at least one conductive pillar layer.
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