TWI591739B - Method of manufacture a package stack-up structure - Google Patents

Description

Method of manufacturing package stack structure

The present invention relates to a semiconductor package process, and more particularly to a method of fabricating a package stack structure.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to improve electrical functions and save packaging space, the industry has developed a stacked complex package structure to form a package stack structure (Package on Package, POP) package type, this package type can use the system package (SiP) heterogeneous integration characteristics, can be used for different electronic components, such as: memory, central processing unit, graphics processor, image application processor Etc., through the stack design to achieve system integration, and is suitable for a variety of thin and light short electronic products.

1 is a schematic cross-sectional view of a conventional package stack structure 1. As shown in FIG. 1 , the package stack structure 1 includes a first semiconductor device 10 , a first package substrate 11 , a second package substrate 12 , a plurality of solder balls 13 , a second semiconductor device 14 , and an encapsulant 15 . The first package substrate 11 has a core layer 110 and a plurality of circuit layers 111 , and the second package substrate 12 has a core layer 120 and a plurality of circuit layers 121 . The first semiconductor component 10 is covered The crystal system is disposed on the first package substrate 11 , and the second semiconductor device 14 is also flip-chip mounted on the second package substrate 12 . The solder balls 13 are used to connect and electrically couple the first package substrate 11 and the second package substrate 12 . The encapsulant 15 covers the solder balls 13 and the first semiconductor component 10. Optionally, a primer 16 is formed between the first semiconductor component 10 and the first package substrate 11.

However, in the conventional package stack structure 1, the first package substrate 11 and the second package substrate 12 both have the core layers 110, 120, which results in high fabrication cost, and the package stack structure 1 has a thickness H of about 620 micrometers, which is inconsistent with the current products. Short-term needs.

Therefore, how to overcome the problems in the prior art has become a problem that is currently being solved.

The present invention provides a method for fabricating a package stack structure, comprising: providing a first coreless package substrate and a second coreless package substrate, wherein the second coreless package One side of the package substrate is provided with at least one electronic component; the first coreless package substrate is bonded to the second coreless package substrate on one side of the electronic component; And forming an encapsulation layer between the first coreless package substrate and the second coreless package substrate, so that the encapsulation layer encapsulates the first conductive elements and the electronic components.

In the above method for manufacturing a package stack structure, the first coreless package substrate further comprises a first dielectric layer, and the first embedded in the first dielectric layer and electrically connected to the first conductive elements Line layer. In addition, the first no The core layer package substrate comprises a plurality of first conductive pillars embedded in the first dielectric layer and formed on the first circuit layer, so that the first conductive components are electrically connected by the first conductive pillars The first circuit layer.

In the manufacturing method of the package stack structure, the other side of the first coreless package substrate is combined with a carrier board. For example, the first coreless package substrate is bonded to the carrier board by a first insulating layer. After the formation of the encapsulation layer, the carrier board is removed. After the carrier is removed, a plurality of first openings are formed on the first insulating layer.

In the above method for fabricating a package stack structure, a primer is formed between the second coreless package substrate and the electronic component.

In the above method for manufacturing a package stack structure, the second coreless package substrate comprises a line build-up structure, and the first conductive element and the electronic component are electrically connected to the line build-up structure. For example, the second coreless package substrate comprises a plurality of second conductive elements formed on the line build-up structure and electrically connected to the line build-up structure, such that the second conductive elements are combined with the first conductive elements. And the electronic component, and the encapsulation layer overlies the second conductive components. Or the second coreless package substrate further comprises a second insulating layer formed on the circuit build-up structure, the second coreless layer is combined before the first and second coreless package substrates are combined. The layered package substrate is combined with the other carrier plate by the second insulating layer, and after the package layer is formed, the other carrier plate is removed, so after the other carrier plate is removed, a plurality of second openings can be formed. On the second insulating layer.

In the foregoing method for fabricating a package stack structure, after forming the package layer, another electronic component is disposed on the first coreless package substrate. on. For example, a package material is formed on the first coreless package substrate so that the package covers the other electronic component.

In addition, in the method for manufacturing the package stack structure, the first conductive elements are first disposed on one side of the first coreless package substrate, and the first coreless package substrate is bonded to the second On a coreless package substrate. Alternatively, the first conductive elements are first disposed on one side of the second coreless package substrate, and the first coreless package substrate is bonded to the second coreless package substrate.

As can be seen from the above, the method for manufacturing the package stack structure of the present invention is to stack two coreless package substrates without core layers, so that the material and process of the core layer can be omitted to reduce the manufacturing cost compared with the prior art. And the thickness of the package stack structure can be greatly reduced.

1,4,4’‧‧‧ package stack structure

10‧‧‧First semiconductor component

11‧‧‧First package substrate

110, 120‧‧‧ core layer

111, 121‧‧‧ circuit layer

12‧‧‧Second package substrate

13,42‧‧‧ solder balls

14‧‧‧Second semiconductor component

15‧‧‧Package colloid

16‧‧‧Bottom glue

2,2'‧‧‧First coreless package substrate

20, 30‧‧‧ carrier board

21, 21' ‧ ‧ first insulation

210‧‧‧First opening

22,22’‧‧‧First dielectric layer

23‧‧‧First line layer

24‧‧‧First Conductive Column

25‧‧‧First conductive element

3,3',3"‧‧‧Second coreless package substrate

3a, 5a, 6a‧‧‧ line build-up structure

31‧‧‧Second insulation

310‧‧‧Second opening

32,52,62‧‧‧second dielectric layer

32', 52'‧‧‧ solder mask

33,53,63‧‧‧second circuit layer

34,54,64‧‧‧second conductive column

35‧‧‧Second conductive element

40,44‧‧‧Electronic components

40a‧‧‧Action surface

40b‧‧‧Non-active surface

400‧‧‧electrode pads

41‧‧‧Encapsulation layer

41’‧‧‧Bottom

43‧‧‧ solder materials

50, 60‧‧‧ carrier

500‧‧‧Fractal layer

501,601‧‧‧metal layer

H, T‧‧‧ thickness

45‧‧‧Package

1A is a cross-sectional view showing a conventional package stack structure; FIGS. 2A to 2B are cross-sectional views showing a method of fabricating the first coreless package substrate of the present invention; and FIG. 2B' is a second FIG. 3A to 3C are schematic cross-sectional views showing a method of fabricating a second coreless package substrate of the present invention; and FIGS. 4A to 4C are cross-sectional views showing a method of fabricating the package stack structure of the present invention; 4A′ to 4B′ are schematic views of another embodiment of FIGS. 4A-4B; FIG. 4C′ is a schematic view of another embodiment of FIG. 4C; 5A to 5C are schematic cross-sectional views showing another embodiment of the method for fabricating the second coreless package substrate of the present invention; and FIGS. 6A to 6C are diagrams showing the second coreless package substrate of the present invention. A schematic cross-sectional view of yet another embodiment of the process.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2B are schematic cross-sectional views showing the manufacturing method of the first coreless package substrate 2 of the present invention.

As shown in FIG. 2A, a first insulating layer 21 is formed on a carrier 20 .

In the embodiment, the carrier 20 is a metal plate, a semiconductor wafer or a glass plate.

Furthermore, the material forming the first insulating layer 21 is selected from a solder resist layer such as green lacquer, polyimide (PI), polyamide-imide (PAI) or poly benzene. Isoimidazole (PBI).

As shown in FIG. 2B, a first dielectric layer 22 is formed on the first insulating layer 21, and the first wiring layer 23 is embedded in the first dielectric layer 22 and formed on the first wiring layer 23. The first conductive pillar 24 is plural, and the first conductive pillar 24 is exposed to the first dielectric layer 22. Then, a plurality of first conductive elements 25 are formed on the first dielectric layer 22 (ie, the first conductive pillars 24) and electrically connected to the first circuit layer 23 by the first conductive pillars 24.

In this embodiment, the order in which the first dielectric layer 22, the first wiring layer 23, and the first conductive pillar 24 are disposed is not particularly limited. For example, a first wiring layer 23 is formed on the first insulating layer 21, and a first conductive pillar 24 is formed on a portion of the first wiring layer 23, and a dielectric material is formed on the first insulating layer 21. The first circuit layer 23 and the first conductive pillars 24 are embedded in the first dielectric layer 22 .

Furthermore, there is no particular limitation on the material for forming the first dielectric layer 22, such as a prepreg, a molding compound, or a photosensitive dielectric layer. In addition, the material of the first dielectric layer 22 may be the same material as the first insulating layer 21.

Moreover, the first conductive element 25 is a copper pillar, a solder ball or a solder ball having a core copper ball, and the shape thereof is not particularly limited, and may be a cylinder or an elliptical cylinder. Or a polygonal cylinder.

In addition, the first coreless package substrate as shown in FIG. 2B' 2 ′, the first conductive pillar 24 can be omitted, and the first conductive component 25 is disposed on the first circuit layer 23 and directly electrically connected to the first circuit layer 23 , and the first dielectric layer 22 ′ It can be a solder mask such as green paint. Specifically, a first insulating layer 21 ′ such as a dielectric material can be selectively formed on a carrier 20 . For example, when the carrier 20 is made of copper, when the carrier 20 is subsequently removed, The first insulating layer 21' can prevent over etching to avoid damaging the first circuit layer 23. If the carrier board 20 and the first circuit layer 23 are made of different materials, the first insulating layer can be omitted. twenty one'.

3A to 3C are schematic cross-sectional views showing the manufacturing method of the second coreless package substrate 3 of the present invention.

As shown in FIGS. 3A to 3C, a carrier board 30 having a second insulating layer 31 is provided, and a line build-up structure 3a is formed on the second insulating layer 31. Next, a plurality of second conductive elements 35 are formed on the line build-up structure 3a and electrically connected to the line build-up structure 3a.

In the embodiment, the carrier 30 is a metal plate, a semiconductor wafer or a glass plate.

Furthermore, the material forming the second insulating layer 31 is selected from a solder resist layer such as green lacquer, polyimide (PI), polyamide-imide (PAI) or polyphenylene. Isoimidazole (PBI).

Moreover, the line build-up structure 3a includes a plurality of second dielectric layers 32, a second circuit layer 33 disposed on the second dielectric layer 32, and embedded in the second dielectric layer 32 for electrical A plurality of second conductive pillars 34 connected to the second wiring layer 33. Specifically, the material of the second dielectric layer 32 is formed as a prepreg. (prepreg), a molding compound or a photosensitive dielectric layer, but is not limited thereto, and the order of setting the second dielectric layer 32, the second wiring layer 33 and the second conductive pillar 34 is not particularly limited. . For example, a second conductive pillar 34 is formed on the second circuit layer 33, and a second dielectric layer 32 is formed on the second insulating layer 31 to cover the second circuit layer 33 and the second conductive pillar 34. And forming a green paint solder resist layer 32 ′ on the outermost second dielectric layer 32 and the second circuit layer 33 , so that a part of the surface of the outermost second circuit layer 33 is exposed to the solder resist layer 32'.

In addition, the second conductive element 35 is a copper pillar, a solder ball or a solder ball having a core copper ball, and is not particularly limited, and is disposed on the second circuit layer 33. And electrically connecting the second circuit layer 33 directly.

4A to 4C are schematic cross-sectional views showing the manufacturing method of the package stack structure 4 of the present invention.

As shown in FIG. 4A, a structure shown in FIG. 3C is provided, and an electronic component 40 is disposed on a portion of the second conductive member 35 of the second coreless package substrate 3.

In this embodiment, the electronic component 40 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 40 is a semiconductor wafer having an opposite active surface 40a and a non-active surface 40b. The active surface 40a has a plurality of electrode pads 400, and the electrode pads 400 are flip-chip-coated. The second conductive elements 35 are electrically connected to the second circuit layer 33. In another embodiment, prior to the electrode pad 400 The second conductive element 35 is formed, and the electronic component 40 is bonded to the second wiring layer 33 with the second conductive element 35.

As shown in FIG. 4B, the structure shown in FIG. 2B is provided, and the first conductive element 25 of the first coreless package substrate 2 is combined with a portion of the second conductive element 35 of the second coreless package substrate 3. The first coreless package substrate 2 is stacked on the second coreless package substrate 3. Then, an encapsulation layer 41 is formed between the first coreless package substrate 2 and the second coreless package substrate 3, so that the encapsulation layer 41 covers the electronic component 40 and the first conductive layers. Element 25 and the second conductive elements 35.

In this embodiment, the encapsulation layer 41 is an insulating material such as an encapsulant of epoxy resin.

Furthermore, before the first coreless package substrate 2 and the second coreless package substrate 3 are combined, a primer (not shown) may be formed on the electronic component 40 and the second coreless layer. Between the package substrates 3.

It should be understood that the structure shown in Fig. 2B may be replaced by the structure shown in Fig. 2B' for stacking.

In other embodiments, as shown in FIGS. 4A' and 4B', the first conductive elements 25 may be disposed on one side of the second coreless package substrate 3, and a portion of the second conductive portion. The component 35 is disposed on the first coreless package substrate 2, and the first coreless package substrate 2 is bonded to the second coreless package substrate 3.

As shown in FIG. 4C, the carrier boards 20, 30 are removed, and a plurality of first openings 210 and a plurality of second openings 310 are formed on the first insulating layer 21, respectively. And the second insulating layer 31, the first circuit layer 23 is exposed to the first openings 210, and the second circuit layers 33 are exposed to the second openings 310 to form a package. Stack structure 4.

In the present embodiment, the package stack 4 has a thickness T of about 440 microns.

Furthermore, if stacked in the structure shown in FIG. 2B', when the first insulating layer 21' is formed, a plurality of first openings 210 may be formed on the first insulating layer 21'; In the insulating layer 21', the first circuit layers 23 are exposed to the first dielectric layer 22'.

In another embodiment, as shown in FIG. 4C', the second circuit layer 33 of the second opening 310 may be coupled to the solder ball 42 for connection to an electronic device such as a circuit board (not shown). And the first circuit layer 23 of the first opening 210 can be combined with the solder material 43 to bond another electronic component 44 such as a chip, and then a package 45 is formed to cover the electronic component 44 to stack the package. Structure 4' becomes a package on package (POP).

It should be understood that the first circuit layer 23 of the first opening 210 may also be combined with a package or an electronic device such as a circuit board.

It should be understood that, as shown in FIG. 4C', a primer 41' may be formed between the second coreless package substrate 3 and the electronic component 40 to cover a portion of the second conductive component 35, and The encapsulation layer 41 covers the primer 41'.

The method of the present invention is to reduce the thickness of the upper and lower package substrates by stacking the first coreless package substrates 2, 2' and the second coreless package substrate 3, so that the conventional method is known Technology, not only can omit the core layer The materials and processes are used to reduce the manufacturing cost, and the overall thickness of the package stack 4, 4' can be greatly reduced to meet the trend of thinness and shortness of electronic products.

5A to 5C are schematic cross-sectional views showing another embodiment of the manufacturing method of the second coreless package substrate 3' of the present invention. The difference between this embodiment and the embodiment of Figs. 3A to 3C lies in the process of the line build-up structure 5a.

As shown in FIG. 5A, a carrier 50 is provided having a release layer 500 and a metal layer 501 formed thereon. Next, a second wiring layer 53 is formed on the metal layer 501.

As shown in FIG. 5B, a plurality of second dielectric layers 52 are formed on the metal layer 501, and a second circuit layer 53 disposed on the second dielectric layer 52 is electrically connected to the second dielectric layer 52. The plurality of second conductive pillars 54 (ie, conductive blind vias) of the second circuit layer 53 are connected.

In this embodiment, a second dielectric layer 52 is formed, and a second wiring layer 53 is formed on the second dielectric layer 52, and a second conductive pillar 54 is formed in the second dielectric layer 52.

As shown in FIG. 5C, the carrier 50 is removed by the release layer 500, and the metal layer 501 is removed by etching. Next, the solder resist layers 32', 52' are respectively formed on the opposite second dielectric layers 52, and the second circuit layer 53 is exposed to the solder resist layers 32', 52' to complete the line increase. Layer structure 5a. Thereafter, a plurality of second conductive elements 35 are formed on at least one of the second circuit layers 53 and electrically connected to the second circuit layer 53.

Therefore, the second coreless package substrate 3' can replace the second coreless package substrate 3 shown in Fig. 4C. For example, the second conductive elements 35 combine the electronic component 40 with the first conductive component 25.

6A to 6C are schematic cross-sectional views showing another embodiment of the manufacturing method of the second coreless package substrate 3" of the present invention. The difference between the embodiment and the embodiments of Figs. 3A to 3C is that the circuit is layered. Process of structure 6a.

As shown in FIG. 6A, a carrier member 60 is provided, and the upper and lower sides thereof have a metal layer 601, and the second dielectric layer 62 and the second line are formed on the metal layer 601 according to the processes of FIGS. 3A to 3B. Layer 63 and second conductive pillar 64. Next, the carrier plate 30 and the second insulating layer 31 are formed (eg, pressed) on the outermost second dielectric layer 62 and the second wiring layer 63.

As shown in FIG. 6B, the carrier 60 and the metal layer 601 are removed to expose the second dielectric layer 62 and the second wiring layer 63.

As shown in Fig. 6C, a solder resist layer 32' is formed on the outermost second dielectric layer 62 and the second wiring layer 63, and a portion of the second wiring layer 63 is exposed to the solder resist layer 32'. Next, a plurality of second conductive elements 35 are formed on the exposed second wiring layer 63.

Therefore, the structure shown in FIG. 6C is such that the electronic component 40 is disposed on a portion of the second conductive member 35 of the second coreless package substrate 3" when the process shown in FIG. 4A is performed.

In summary, the package stack structure 4, 4' of the present invention is mainly formed by stacking the first coreless package substrate 2, 2' and the second coreless package substrate 3, 3', 3", To omit the material and process of the core layer and reduce the thickness of the package stack 4, 4'.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. change. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧First coreless package substrate

21‧‧‧First insulation

210‧‧‧First opening

22‧‧‧First dielectric layer

23‧‧‧First line layer

24‧‧‧First Conductive Column

25‧‧‧First conductive element

3‧‧‧Second no core layer package substrate

3a‧‧‧Line layering structure

31‧‧‧Second insulation

310‧‧‧Second opening

33‧‧‧Second circuit layer

35‧‧‧Second conductive element

4‧‧‧Package stack structure

40‧‧‧Electronic components

41‧‧‧Encapsulation layer

T‧‧‧ thickness

Claims (19)

A method for manufacturing a package stack structure includes: providing a first coreless package substrate and a second coreless package substrate, wherein the first coreless package substrate is bonded to the second coreless The other side of the layered package substrate is coupled with a carrier board, and one side of the second coreless package substrate is provided with at least one electronic component; and the first coreless package substrate is combined with the plurality of first conductive components. And the second coreless package substrate is disposed on one side of the electronic component; and an encapsulation layer is formed between the first coreless package substrate and the second coreless package substrate The encapsulation layer encapsulates the first conductive elements and the electronic components. The method for manufacturing a package stack structure according to claim 1, wherein the first coreless package substrate comprises a first dielectric layer, and is embedded in the first dielectric layer and electrically connected. a first circuit layer of the first conductive elements. The method for manufacturing a package stack structure according to claim 2, wherein the first coreless package substrate comprises a plurality of layers embedded in the first dielectric layer and formed on the first circuit layer. The first conductive pillars are configured to electrically connect the first conductive elements to the first circuit layer by the first conductive pillars. The method for manufacturing a package stack structure according to claim 1, wherein the method further comprises: after forming the package layer, removing the carrier board. The method for manufacturing a package stack structure according to claim 1, wherein the first coreless package substrate is bonded to the carrier by a first insulating layer. The method for manufacturing a package stack structure according to claim 5, further comprising removing the carrier plate after forming the package layer. The method for manufacturing a package stack structure according to claim 6 is characterized in that after the carrier plate is removed, a plurality of first openings are formed in the first insulating layer. The method of manufacturing a package stack structure according to claim 1, wherein the second coreless package substrate and the electronic component are formed with a primer. The method for manufacturing a package stack structure according to claim 1, wherein the second coreless package substrate comprises a line build-up structure, and the first conductive element is electrically connected to the electronic component. Line build-up structure. The method for manufacturing a package stack structure according to claim 9, wherein the second coreless package substrate comprises a plurality of second layers formed on the line build-up structure and electrically connected to the line build-up structure. Conducting elements such that the second conductive elements combine the first conductive elements with the electronic components. The method of fabricating a package stack structure according to claim 10, wherein the package layer overlies the second conductive elements. The method for manufacturing a package stack structure according to claim 9, wherein the second coreless package substrate comprises a plurality of formed on the line a second insulating layer on the buildup structure. The method for manufacturing a package stack structure according to claim 12, wherein the second coreless package substrate is combined with the second insulation layer before the first and second coreless package substrates are combined Another carrier board. The method for manufacturing a package stack structure according to claim 13 is characterized in that after the encapsulation layer is formed, the other carrier plate is removed. The method for manufacturing a package stack structure according to claim 14 is characterized in that after removing the other carrier plate, a plurality of second openings are formed in the second insulating layer. The method for manufacturing a package stack structure according to claim 1, wherein after the forming the package layer, another electronic component is disposed on the first coreless package substrate. The method for manufacturing a package stack structure according to claim 16, further comprising forming a package material on the first coreless package substrate to cover the package with the other electronic component. The method for manufacturing a package stack structure according to claim 1, wherein the first conductive elements are first disposed on one side of the first coreless package substrate, and the first coreless layer is The package substrate is bonded to the second coreless package substrate. The method for manufacturing a package stack structure according to claim 1, wherein the first conductive elements are first disposed on one side of the second coreless package substrate, and the first coreless layer is The package substrate is bonded to the second coreless package substrate.