TWI551058B - Decoder and decoding method thereof for min-sum algorithm of low density parity-check code - Google Patents

Description

Low-density parity check code decoder with minimum-sum algorithm and decoding method thereof

The present invention is a low density parity check code decoder, and more particularly to a decoder for a low density parity check code of a minimum-sum algorithm and a decoding method thereof.

The data may be destroyed during the transmission process due to the poor reliability of the transmission medium or the interference of external factors, and the effect of the error control coding is to restore the damaged data. Commonly used error correction codes include Hamming Code, Reed Solomon Code, BCH Code (Bose Chaudhuri Hocquengham Code), and Low Density Parity-Check Code. Errors with low-density parity check codes have better error detection and correction capabilities, and can also be decoded at very high rates. In the design of a part of the parallel architecture of the decoder of the conventional low-density parity check code, in order to improve the parallelism of the operation, and in order to avoid the memory access problem of the column block and the column block, the memory is usually The body is divided into memory blocks in units of a cyclic matrix for operation, and these memory blocks are read or written.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a decoder of a conventional low density parity check code. The decoder 1 includes a memory 11 and a computing module 12. The computing module 12 includes a plurality of computing units 12-1, 12-2, ..., 12-n. The arithmetic unit 12-1, 12-2, ..., 12-n is commonly coupled to the memory 11. Traditionally, decoder 1 has to store the data generated by the calculation process when performing iterative calculations. Therefore, the arithmetic units 12-1, 12-2, ..., 12-n are connected to an external memory 11. However, by sharing the storage area of the memory 11, the data collision of the storage space due to writing or reading is encountered during the access of each of the arithmetic units 12-1, 12-2, ..., 12-n.

Therefore, although the low-density parity check code has various advantages, there are still many problems, such as the above-mentioned data collision, circuit area, and computational complexity. In the design of the decoder of low-density parity check code, how to effectively improve is still the goal of future efforts.

The embodiment of the invention provides a low-density parity check code decoder of a minimum-sum algorithm for decoding encoded data having a bit node and a check node. The decoder includes a computing module and a memory. The computing module includes a plurality of computing units, and the memory includes a plurality of memory units. The operation unit includes a check node unit, a first message reconstruction unit, and a second message reconstruction unit. The memory is coupled to the computing module. The memory unit is coupled to the computing unit in a one-to-one manner, the first information reconstruction unit is coupled to the checking node unit, and the second information reconstruction unit is coupled to the checking node unit. The computing module is configured to divide the encoded data into a plurality of data groups, and the computing unit respectively calculates corresponding data groups. The checking node unit is configured to calculate the storage format by generating a corresponding data group, and the first message reconstruction unit is configured to reconstruct the calculation result into a calculation format and add up the calculation with the subsequently input data group. The second message reconstruction unit is configured to reconstruct the calculation result of the storage format into an output format. The memory unit is configured to store the calculation result generated by the corresponding operation unit.

The embodiment of the invention provides a low-density parity check code decoding method of a minimum-sum algorithm, which comprises the steps of: dividing the coded data into a plurality of data groups; and calculating corresponding data groups by using a plurality of operation units respectively group. In the steps of respectively calculating corresponding data groups by a plurality of arithmetic units, the following includes the following Step: each computing unit calculates the storage format by calculating the corresponding data group through the checking node unit; storing the calculation result generated by the corresponding computing unit one by one through the plurality of memory units; reconstructing through the first message The calculation result of the unit storage is reconstructed into a calculation format and the first summation calculation is performed with the subsequently input data group; and the calculation result of the storage format is reconstructed into an output format by the second message reconstruction unit.

In summary, the decoder of the low-density parity check code proposed by the embodiment of the present invention and the decoding method thereof can avoid the conventional decoding of the decoder using the low-density parity check code. Collision of data caused during the reading process. More specifically, since the data required for the minimum-sum algorithm is relatively simple, through the present invention, each arithmetic unit has a one-to-one correspondence to access the exclusive memory space, and does not generate a collision of the decoder of the conventional shared memory space. situation. On the other hand, as the length of the encoded data and the length of the string increase, the conventional decoder also causes a burden on the shared memory space to increase the cost. Therefore, through the present invention, the plurality of memory cells can be further used to store the calculated data, thereby reducing the storage space required for the overall required memory storage.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

1, 2‧‧‧ decoder

11, 21‧‧‧ memory

12, 22‧‧‧ Calculation Module

12-1, 12-2, 12-3, ..., 12-n, 22-1, 22-2, 22-3, ..., 22-n‧‧‧ arithmetic unit

21-1, 21-2, 21-3, ..., 21-n‧‧‧ memory unit

22-1a‧‧‧Check node unit

22-1b‧‧‧First Message Reconstruction Unit

22-1c‧‧‧Second Message Reconstruction Unit

22-1d‧‧‧Adder

INPUT_1, INPUT_2, INPUT_3, ..., INPUT_k-1, INPUT_k‧‧‧ inputs

OUTPUT_1, OUTPUT_2, OUTPUT_3, ..., OUTPUT_k-1, OUTPUT_k‧‧‧ output

SIGN_BIT‧‧‧ data positive and negative sign bit output

MIN_1‧‧‧first minimum bit string output

MIN_2‧‧‧Second minimum bit string output

S101~S113‧‧‧ is the method step flow

1 is a schematic diagram of a decoder of a conventional low-density parity check code; FIG. 2 is a schematic diagram of a decoder of a low-density parity check code of a minimum-sum algorithm in accordance with an embodiment of the present invention; Detailed diagram of the arithmetic unit of the decoder; FIG. 4 is a flowchart of a decoding method of the low-density parity check code of the minimum-sum algorithm in the embodiment of the present invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "or" may include all combinations of any one or more of the associated listed items.

First, please refer to FIG. 2. FIG. 2 is a schematic diagram of a decoder of a low-density parity check code of a minimum-sum algorithm in accordance with an embodiment of the present invention. The decoder 2 includes a memory 21 and a computing module 22. The memory 21 includes memory units 21-1, 21-2, ..., 21-n and the calculation module 22 includes arithmetic units 22-1, 22-2, ..., 22-n. The arithmetic units 22-1, 22-2, ..., 22-n are coupled to the memory units 21-1, 21-2, ..., 21-n, respectively, one-to-one. The decoder 2 with low-density parity check code in the embodiment of the present invention is configured to decode encoded data having a bit node and a check node to generate decoded data and ensure decoding of data. Correctness. The related bit nodes and the check nodes are those commonly used in the technical field, and the techniques commonly used in error correction codes are not described herein.

The computing module 22 is configured to perform operations on the received encoded data. The computing module 22 divides the encoded data of the low density parity check code having the bit node and the check node into a plurality of data groups to provide subsequent decoding. The data group includes a plurality of data bit strings. In the embodiment of the present invention, the calculation module 22 uses a minimum-sum algorithm (Min-Sum Algorithm, MSA) to calculate the coded data of the low density parity check code. More specifically, the computing module 22 performs the above calculations for each of the data groups through the plurality of internal computing units 22-1, 22-2, ..., 22-n. For example, the computing module 22 cuts the encoded data into 15 data groups. The arithmetic unit 22-1 receives and calculates the first data group. Similarly, the arithmetic unit 22-2 receives the second data group, and so on. In the embodiment of the present invention, the operation units 22-1, 22-2, ..., 22-n may be a Central Process Unit (CPU), a Micro Control Unit (MCU) or the like. The components having the computing function are not limited by the invention. It is also worth noting that the present invention does not limit the type of minimum-summation algorithm, and can correct the Self-corrected Min-sum Algorithm and the Modified Min-sum Algorithm. Or an optimization of the minimum-sum algorithm (Optimized Min-sum Algorithm) and so on the minimum-sum algorithm to extend the algorithm.

In the embodiment of the present invention, the memory 21 is used to store the calculation results generated by the arithmetic units 22-1, 22-2, ..., 22-n. More specifically, the embodiment of the present invention is a one-to-one correspondence operation unit 22-1, 22 through a memory 21 composed of a plurality of memory units 21-1, 21-2, ..., 21-n. 2,..., 22-n for storage.

Next, please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is a schematic diagram of the arithmetic unit of the decoder according to the embodiment of the present invention. It is worth mentioning that each of the computing units 22-1, 22-2, ..., 22-n has a checking node unit 22-1a, a first message reconstructing unit 22-1b, and a second message reconstructing unit 22- 1c, a plurality of adders 22-1d, a plurality of input terminals INPUT_1, INPUT_2, INPUT_3, ..., INPUT_k and a plurality of output terminals OUTPUT_1, OUTPUT_2, OUTPUT_3, ..., OUTPUT_k. However, FIG. 3 is only described by the arithmetic unit 22-1 and the memory unit 21-1.

The check node unit 22-1a is configured to calculate the received data group and generate a calculation result of the storage format. More specifically, the arithmetic unit 22-1 receives the k data bit strings in the data group corresponding to the arithmetic unit 22-1 through the input terminals INPUT_1, INPUT_2, INPUT_3, ..., INPUT_k, respectively. Each of the data bit strings has a length r, r ≧ 1, and is an integer. The check node unit 22-1a performs calculation based on the minimum-sum algorithm to generate the calculation result of the above storage format. Those of ordinary skill in the art should understand that the calculation process of the min-sum algorithm focuses on the first minimum value, the second minimum value, the position of the first minimum value, and the data bit string in the calculated data bit string. Each meta-information is positive and negative. Therefore, after the calculation by the check node unit 22-1a, the first minimum bit string output/output terminal MIN_1 of the check node unit 22-1a outputs the first minimum bit string and the first minimum position bit string. The second minimum bit string output/output terminal MIN_2 of the check node unit 22-1a outputs the second minimum bit string, and the positive and negative sign bit of the check node unit 22-1a is outputted to the front end SIGN_BIT output data positive and negative sign bit The storage format of the metastring is stored in the corresponding memory unit 21-1. The length of the positive and negative sign bit string is equal to the length of the data bit string. In addition, since the minimum-sum algorithm is calculated by two bits, since the length of the data bit string is r, when storing the bit string at the minimum position, the length is only ceil (Log ₂ r) is sufficient (in It is defined here as ceil(Log ₂ r)=L). The calculus of the minimum-sum algorithm is a commonly used calculus method in the error correction code, and therefore will not be described here.

The memory unit 21-1 is configured to store the calculation result of the storage format generated by the operation unit 22-1. In the embodiment of the present invention, when the decoder calculates the low density parity check code by the minimum-sum algorithm, the decoder repeats the calculation in an iterative manner. Therefore, the calculation result of each time is stored through the corresponding memory unit 21-1. The calculation result is the first minimum bit string, the first minimum position bit string, the second minimum bit string, and the data positive sign bit string of the data group calculated by the operation unit 22-1. The memory unit 21-1 includes a plurality of storage columns, and the number of the storage columns is the number of the check nodes of each data group. It is worth mentioning that the storage space length of the storage column is greater than or equal to the length of the first minimum bit string, the length of the second minimum bit string, the length of the first minimum position bit string, and the positive and negative sign bits of the data. The length of the metastring is added up. The memory unit 21-1 may be a volatile or non-volatile memory such as a flash memory chip, a read only memory chip or a random access memory chip. The chip is implemented, but the embodiment is not limited thereto.

In the iterative calculation process of the check node unit 22-1a, the first message reconstruction unit 22-1b is configured to reconstruct the calculation result of the storage format stored in the memory unit 21-1 into a calculation format and the data group that is subsequently input. The group performs a first calculated value generated by the first total calculation by the adder 22-1d. More specifically, the first minimum bit string input/output terminal MIN_1 of the first message reconstruction unit 22-1b receives the first minimum bit string and the first minimum position bit string of the storage format, first The second minimum bit string output terminal MIN_2 of the message reconstruction unit 22-1b receives the second minimum bit string of the storage format, and the data positive and negative sign bit of the first message reconstruction unit 22-1b is outputted to the SIGN_BIT. After receiving the data positive and negative symbol bit string of the storage format, the first calculated value is used for the next operation with the data group that is subsequently input.

The calculation result is output when the iteration calculation of the check node unit 22-1a reaches the stop condition, that is, when the check node unit 22-1a reaches the preset number of calculations or when the Syndrome Text is zero. More specifically, the second message reconstruction unit 22-1c is configured to receive the first minimum bit string and the first minimum value calculated by the last check node unit 22-1a when the check node unit 22-1a ends the calculation. a position bit string, a second minimum bit string, and a data sign bit string, reconstructing the message into a calculation result of the output format of the decoded data group, and further adding the first sum by the plurality of adders 22-1d The first calculated value of the calculation performs a second total calculation. After the second total calculation, the output is outputted to the plurality of output terminals OUTPUT_1, OUTPUT_2, OUTPUT_3, . . . , OUTPUT_k, respectively, to provide an operation in which the arithmetic unit 22-1 subsequently integrates the decoded data group to generate decoded data to complete decoding.

Next, please refer to FIG. 4. FIG. 4 is a flowchart of a method for decoding a low-density parity check code of a minimum-sum algorithm in accordance with an embodiment of the present invention. The decoding method of the embodiment of the present invention includes the following steps: Step S101, the encoded data is divided into a plurality of data groups; and in step S103, the computing unit calculates the data group by using the checking node unit to generate a storage format calculation result; S105. Store the calculation result generated by the corresponding operation unit one by one through the plurality of memory units; and step S107 The first message reconstruction unit reconstructs the stored calculation result into a calculation format and performs a first total calculation with the subsequently input data group; and in step S109, determines whether to stop checking the node unit according to the preset calculation number or symptom test. Step S111, the calculation result of the storage format is reconstructed into an output format by the second message reconstruction unit; in step S113, the calculation result of the reconstruction to the output format is further performed with the first calculation value of the first total calculation, and the second total calculation is performed. And outputting the second calculated value of the second total calculation.

Please refer to Figure 2 and Figure 4 at the same time. In step S101, the calculation module 22 divides the encoded data of the low density parity check code having the bit node and the check node into a plurality of data groups to provide subsequent decoding. The data group includes a plurality of data bit strings.

Next, in step S103, the checking node unit 22-1a is configured to calculate the received data group and generate a calculation result of the storage format. Those of ordinary skill in the art should understand that the calculation process of the min-sum algorithm focuses on the first minimum value, the second minimum value, the position of the first minimum value, and the data bit string in the calculated data bit string. Each meta-information is positive and negative.

Please refer to Figure 3 and Figure 4 at the same time. In step S105, after the calculation by the checking node unit 22-1a, the first minimum bit string output terminal MIN_1 of the checking node unit 22-1a outputs the first minimum bit string and the first minimum position bit. The string, the second minimum bit string output/output terminal MIN_2 of the check node unit 22-1a outputs the second minimum bit string, and the data of the positive and negative sign bit of the check node unit 22-1a is outputted to the SIGN_BIT output data. The storage format of the positive and negative sign bit strings is stored to the corresponding memory unit 21-1. The length of the positive and negative sign bit string is equal to the length of the data bit string. In addition, since the minimum-sum algorithm is calculated by two bits, since the length of the data bit string is r, when the bit string of the minimum value is stored, the length is only ceil (Log ₂ r). The memory unit 21-1 includes a plurality of storage columns, and the number of the storage columns is the number of the check nodes of each data group. It is worth mentioning that the length of the storage column is greater than or equal to the length of the first minimum bit string, the length of the second minimum bit string, the length of the first minimum position bit string, and the positive and negative sign bit of the data. The length of the string is added up.

In step S107, the calculation result of the storage format stored in the memory unit 21-1 is reconstructed into a calculation format by the first message reconstruction unit 22-1b, and the data group that is subsequently input is first transmitted through the adder 22-1d. The total calculation produces a first calculated value. In step S109, the checking node unit 22-1a determines whether to stop the calculation of the check node unit according to the preset number of calculations or the symptom test. If yes, go to step S111; if no, go to step S103 to repeat the calculation of iteration.

In step S111, when the iteration calculation of the check node unit 22-1a reaches the stop condition, that is, when the check node unit 22-1a reaches the preset calculation number or the symptom test is stopped, the output is the output format calculation result. . In step S113, the second summation calculation is performed by the plurality of adders 22-1d to further calculate the first calculated value of the first total calculation and the calculation result of the output format. Finally, after the second total calculation, and outputted to the plurality of output terminals OUTPUT_1, OUTPUT_2, OUTPUT_3, ..., OUTPUT_k, respectively, the operation unit 22-1 is subsequently integrated to decode the data group to generate decoded data to complete decoding. action.

[effects of invention]

In summary, the decoder of the low-density parity check code proposed by the embodiment of the present invention and the decoding method thereof can avoid the conventional decoding of the decoder using the low-density parity check code. Collision of data caused during the reading process. More specifically, since the data required for the minimum-sum algorithm is relatively simple, through the present invention, each arithmetic unit has a one-to-one correspondence to access the exclusive memory space, and does not generate a collision of the decoder of the conventional shared memory space. situation. On the other hand, as the length of the encoded data and the length of the string increase, the conventional decoder also causes a burden on the shared memory space to increase the cost. Therefore, through the present invention, the plurality of memory cells can be further used to store the calculated data, thereby reducing the storage space required for the overall required memory storage.

The above description is only the preferred embodiment of the present invention, but the features of the present invention. It is not limited thereto, and any variation or modification that can be easily conceived by those skilled in the art in the field of the present invention can be covered in the following patent scope of the present invention.

22-1‧‧‧ arithmetic unit

21-1‧‧‧Memory unit

22-1a‧‧‧Check node unit

22-1b‧‧‧First Message Reconstruction Unit

22-1c‧‧‧Second Message Reconstruction Unit

22-1d‧‧‧Adder

INPUT_1, INPUT_2, INPUT_3, ..., INPUT_k-1, INPUT_k‧‧‧ inputs

OUTPUT_1, OUTPUT_2, OUTPUT_3, ..., OUTPUT_k-1, OUTPUT_k‧‧‧ output

SIGN_BIT‧‧‧ data positive and negative sign bit output

MIN_1‧‧‧first minimum bit string output

MIN_2‧‧‧Second minimum bit string output

Claims (11)

A low-density parity check code (LDPC) decoder of a Min-sum Algorithm (MSA) for encoding a coded data having a one-bit node and a check node Decoding, the decoder includes: a computing module, the encoded data is divided into a plurality of data groups, the computing module includes: a plurality of computing units, each of the computing units respectively calculating a corresponding data group Each of the computing units includes: a check node unit, the corresponding data group is calculated to generate a storage format calculation result; a first message reconstruction unit coupled to the check node unit to The calculation result is reconstructed into a calculation format and summed with the data group of the subsequent input; and a second message reconstruction unit is coupled to the verification node unit for reconstructing the calculation result of the storage format into an output And a memory coupled to the computing module, comprising: a plurality of memory units, each of the memory units being coupled to the computing units one-to-one for storing Corresponding to the calculation result produced by the arithmetic unit. A decoder for a low-density parity check code of the minimum-sum algorithm described in claim 1, wherein the memory unit comprises a plurality of storage columns. The decoder of the low-density parity check code of the minimum-sum algorithm described in claim 2, wherein the number of the storage columns of the operation unit is the number of the check nodes of each data group. A decoder for a low-density parity check code of the minimum-sum algorithm described in claim 1, wherein the data group comprises a plurality of data bit strings. A decoder for a low-density parity check code of the minimum-sum algorithm described in claim 1, wherein each of the arithmetic units comprises: a plurality of input ends, each of the input ends respectively receiving a plurality of data bit strings in the corresponding data group; wherein the data bit string length is r, r ≧ 1, and is an integer. The decoder of the low-density parity check code of the minimum-sum algorithm described in claim 2, wherein the calculation result includes a first minimum bit string, a second minimum bit string, and a first minimum The value position bit string and a data positive sign bit string. A decoder for a low-density parity check code of the minimum-sum algorithm described in claim 6, wherein the data positive and negative sign bit string length is equal to the data bit string length. The decoder of the low-density parity check code of the minimum-sum algorithm described in claim 6, wherein the length of the first minimum position bit string is L, where L=ceil(Log ₂ r). The decoder of the low-density parity check code of the minimum-sum algorithm described in claim 6, wherein a space length of the storage column is greater than or equal to a length of the first minimum bit string, the second minimum The length of the bit string, the length of the first minimum position bit string, and the length of the data positive and negative sign bit string are summed. The decoder of the low-density parity check code of the minimum-sum algorithm described in claim 1, wherein the minimum-sum algorithm is a modified Min-sum Algorithm. A decoding method for a low-density parity check code of a minimum-sum algorithm for decoding an encoded data having a one-bit node and a check node, the decoding method comprising: dividing the encoded data into a plurality of data a group; each of the computing units calculates a data storage format by calculating a corresponding data group by using a checking node unit; and storing the corresponding one of the operating units by a plurality of memory units Calculation results; Reconstructing the stored calculation result into a calculation format by a first message reconstruction unit and performing a first total calculation with the subsequently input data group; and calculating the storage format by a second message reconstruction unit The result is reconstructed into an output format.