TWI524177B - Debug test circuit and method thereof - Google Patents

Description

Debug test circuit and method thereof

The present invention is a debug test circuit and method thereof, and more particularly to a debug test circuit and a method thereof disposed on a motherboard.

With the advancement of technology, electronic devices such as computers, computers, tablets, notebook computers, mobile communication devices, personal digital assistants (PDAs), handheld game consoles, medical information platforms, medical information nursing platforms or servo hosts are also gradually becoming more and more popular. As a result, the above electronic devices have been widely used by institutions, organizations, businesses, families, or individuals. For example, the average person can conveniently operate a tablet or a smart phone to easily access the Internet, watch movies, listen to music, read e-books, check maps or play games while on the go.

However, when the program, the download program, the software or the firmware of the above-mentioned electronic device is defective due to a design defect or a virus, or an electronic component such as a hardware, a circuit board or a firmware in the electronic device, etc. In the event of loss or defective defects, the above electronic equipment will malfunction. Generally, people will send the faulty electronic equipment to the factory for repair. Therefore, the staff must first disassemble the casing or casing of the above electronic equipment or loosen multiple locks. Fixing screws to further detect the motherboard installed in the casing, thereby performing debugging operations, thereby increasing the inspection time or maintenance time of the staff, and even some of the electronic equipment casings need to be disassembled using special tools. Among them, special tools such as hexagonal wrenches or plum wrenches are not necessarily arranged in the maintenance site, thus causing inconvenience for the worker to detect the motherboard.

The present invention provides a debug test circuit in which the present invention is transparent The motherboard is reserved for the general-purpose serial bus outside the electronic device to perform debugging operations, thereby saving time, reducing costs, and improving the convenience of detecting the motherboard.

The invention provides a debugging test circuit, which is disposed on a motherboard, and includes a central processing unit, a multiplexing processing unit, a determining unit and a universal serial bus unit. The multiplex processing unit is coupled to the central processing unit through a debug channel and a universal serial bus channel. The determining unit is coupled to the multiplex processing unit. The universal sequence bus unit is coupled to the multiplex processing unit and the determining unit. Wherein, when the universal sequence bus bar unit receives an identification signal, the identification signal is determined by the determining unit, and when it is determined that the identification signal belongs to a setting signal, the determining unit outputs a first signal to the multiplex processing unit, so as to The processing unit switches to turn on a debug channel.

The invention provides a debugging test method, which is suitable for detecting a motherboard, which comprises determining whether the identification signal is a set signal when the universal sequence bus unit receives an identification signal, and if so, the determining unit outputs a first signal to the multiplexer. The processing unit; and the multiplex processing unit turn on a debug channel according to the first signal.

The debug test circuit of the present invention is disposed on the motherboard. Therefore, the user can insert the debug test circuit of the present invention through the universal serial bus, wherein the judging unit outputs the identification signal according to the universal serial bus. To determine whether it is the first signal, when the result of the determination is the first signal, the multiplex processing unit will turn on the universal asynchronous transceiver channel, thereby saving time, reducing cost, and improving the convenience of detecting the motherboard.

The above summary and the following examples are intended to be illustrative of the invention and the embodiments of the invention.

1‧‧‧Debug test circuit

9‧‧‧Computer equipment

10‧‧‧Central Processing Unit

12‧‧‧Multiworking unit

14‧‧‧judging unit

140‧‧‧Comparative lines

OP1‧‧‧First Comparator

C11‧‧‧ first input

C12‧‧‧ second input

CO1‧‧‧ first output

OP2‧‧‧Second comparator

C21‧‧‧ first input

C22‧‧‧ second input

CO2‧‧‧ second output

16‧‧‧Common sequence bus unit

18‧‧‧ Conversion device

181‧‧‧First connecting element

182‧‧‧Second connection element

U1‧‧‧Wiring channel

U2‧‧‧Universal Sequence Bus Channel

OUTC‧‧‧ output channel

R1~R4‧‧‧ resistor

IDV‧‧‧ identification signal

VDD‧‧‧ working voltage

V1‧‧‧ first voltage

V2‧‧‧second voltage

C1~C6‧‧‧ capacitor

D1‧‧‧First Diode

D2‧‧‧ second diode

DGND‧‧‧ grounding terminal

S401~S413‧‧‧ Process steps

1 is a functional block diagram of a debug test circuit according to an embodiment of the present invention.

2 is a circuit diagram of a debug test circuit in accordance with another embodiment of the present invention.

3 is an identification operation table of a debug test circuit according to another embodiment of the present invention.

4 is a flow chart of a debugging test method according to another embodiment of the present invention.

1 is a functional block diagram of a debug test circuit according to an embodiment of the present invention. Please refer to Figure 1. A debug test circuit 1 includes a central processing unit 10, a multiplex processing unit 12, a determination unit 14, a universal sequence bus unit 16 and a conversion device 18.

In practice, the multiplex processing unit 12 is coupled to the sequence bus bar unit 16, the judging unit 14 and the central processing unit 10, and the central processing unit 10, the multiplex processing unit 12, the judging unit 14, and the universal sequence bus unit 16 are The device is disposed on the motherboard, and the conversion device 18 is electrically connected to the universal serial bus unit 16 and the computer device 9. The embedded program of the motherboard can output the program through the universal serial bus unit 16. The message is output to the computer device 9 via the conversion device 18. Therefore, the user can use the information displayed by the computer device 9 to detect a defect of the motherboard.

Further, the motherboard is, for example, a computer board, a circuit board or a printed circuit board with a reduced instruction set (RISC) or an advanced reduced instruction set (ARM), and is installed in a computer, a computer, a tablet, a notebook computer, Electronic devices such as mobile communication devices, personal digital assistants (PDAs), handheld game consoles, medical information platforms, medical information nursing platforms, or servo hosts. The built-in programs of the motherboards are, for example, built-in debug detectors, initialization programs, or It is a compiler that supports C++ language and/or combination language. This embodiment does not limit the aspect and use of the motherboard.

The central processing unit 10 is, for example, an x86 processor, a RISC Processor, an ARM Processor, or other type of processor, wherein the central processing unit 10 is, for example, Advanced Micro Devices. Processors manufactured by companies such as TI, Samsung, Cortex or Intel, and central The processing unit 10 can output a Universal Signal Receiver Transmitter Signal (UART Signal) and a Universal Asynchronous Receiver Transmitter Signal (UART Signal) to the multiplex processing unit 12. This embodiment does not limit the aspect of the central processing unit 10. .

The multiplex processing unit 12 is coupled to the central processing unit 10 and the universal sequence bus unit 16. In practice, the multiplex processing unit 12 is, for example, 2-1MUX, 3-1MUX, M-NMUX (M, N is a positive integer greater than 2), an output selection multiplexer (DMUX), or a PI3USB10 multiplexer. The aspect of the multiplex processing unit 12 is not limited. The multiplex processing unit 12 and the central processing unit 10 have two channels, one of which is used for outputting or receiving a universal serial bus signal. For example, the D+ and D- signals of the universal serial bus can be transmitted on the channel; The other channel is used to output a general asynchronous transceiver signal. For example, the TX and RX signals of the universal asynchronous transceiver can be transmitted on the channel.

In detail, the multiplex processing unit 12 is electrically connected to the central processing unit 10 through the debug channel U1 and the universal serial bus channel U2, and the multiplex processing unit 12 is, for example, a 2-1 MUX, and the multiplex processing unit 12 is The two input signals are selected: one of the input signals is a universal serial bus signal, and the other input signal is a universal asynchronous transceiver signal. Therefore, the multiplex processing unit 12 can select one of the two input signals. And output through the universal sequence bus unit 16.

For example, the input end of the multiplex processing unit 12 is coupled to the central processing unit 10, so that the input of the multiplex processing unit 12 will receive the D+/D- universal sequence bus signal or the TX/RX universal non-synchronization. The transceiver signal, wherein the output of the multiplex processing unit 12 is coupled to the serial bus unit 16, so that the multiplex processing unit 12 can select the universal sequence bus channel U2 to output D+ according to the first or second signal. /D- general-purpose serial bus signal, or select the debug channel U1 to output the TX/RX universal non-synchronous transceiver signal, and D+/D- general-purpose serial bus signal or TX/RX universal asynchronous transmission and reception The device signal will be transmitted to the computer device 9 via the universal serial bus unit 16.

In other embodiments, the multiplex processing unit 12 is, for example, an output selection multiplexer (DMUX), wherein the input of the multiplex processing unit 12 is coupled to the serial bus unit 16 so that the input of the multiplex processing unit 12 The output of the multiplexed processing unit 12 is coupled to the central processing unit 10, and the multiplex processing unit 12 can select the output D+/D- according to the first signal or the second signal. The serial bus signal or the TX/RX universal non-synchronous transceiver signal is sent to the central processing unit 10. This embodiment does not limit the operation of the multiplex processing unit 12 and the central processing unit 10.

The determining unit 14 is coupled to the multiplex processing unit 12 and the universal sequence bus unit 16. In practice, when the first connection component 181 of the conversion device 18 is inserted into the sequence bus bar unit 16, an identification pin of the universal sequence bus bar unit 16 outputs an identification signal to the determination unit 14, and the determination unit 14 uses For determining the identification signal, wherein the identification signal is, for example, a voltage signal conforming to the universal serial bus communication protocol, when the voltage signal conforms to the preset signal of the universal serial bus communication protocol, the central processing unit 10 will distinguish the main according to the preset signal. From relationship.

For example, when the portable device is plugged into the universal serial bus unit 16 on the motherboard, the determining unit 14 determines that the identification signal is a preset signal, and the central processing unit 10 will distinguish the master-slave relationship according to the preset signal. For example, the universal serial bus unit 16 on the motherboard side is a Host Port, and the external flash drive device is, for example, a Device Port. Therefore, when the USB flash drive device is plugged into the universal serial bus of the present invention, In the case of the unit 16, the determining unit 14 can determine the flash drive device according to the identification signal conforming to the preset signal, and distinguish the master-slave relationship between the flash drive device and the motherboard.

It should be noted that the determining unit 14 further includes a comparison line 140 having a first voltage and a second voltage, and the first voltage is greater than the second voltage. In practice, the comparison line 140 is, for example, a circuit or a chip composed of one or more comparators, a logic integrated circuit, a wafer or a logic determination circuit or a wafer. This embodiment does not limit the aspect of the comparison line 140, wherein the first The voltage is, for example, an upper limit voltage, The second voltage is, for example, a lower limit voltage, wherein the upper limit voltage is, for example, 3, 2.5 or 2.2 volts, and the lower limit voltage is, for example, 0.5, 0.8 or 1.1 volts, and the present embodiment does not limit the values of the first and second voltages.

The universal sequence bus unit 16 is coupled to the multiplex processing unit 12 and the determining unit 14. In practice, the universal sequence bus unit 16 can be a universal serial bus (USB), a mini universal serial bus (Mini USB), a micro universal serial bus (Micro USB) or other transmission signal transmission interface, this embodiment The aspect of the universal sequence bus unit 16 is not limited.

Next, when the identification signal is received by the universal sequence bus unit 16, the identification signal is determined by the determining unit 14, and when it is determined that the identification signal belongs to a setting signal, the determining unit 14 outputs a first signal to the multiplex processing unit. 12, so that the multiplex processing unit 12 switches to turn on a debug channel U1.

In practice, the setting signal conforms to the communication protocol of the universal serial bus, and the setting signal is a voltage signal between the first voltage and the second voltage. In other words, the setting signal is between the upper limit voltage and the lower limit. Voltage signal between voltages. Therefore, when the determining unit 14 determines that the identification signal is a set signal, the determining unit 14 outputs the first signal to the multiplex processing unit 12, wherein the first signal is for instructing the multiplex processing unit 12 to select the universal asynchronous transceiver channel. Signals, therefore, users can use the universal serial bus to perform debugging operations.

In addition, when the identification signal is received by the universal sequence bus unit 16, the identification signal is determined by the determining unit 14, and when it is determined that the identification signal belongs to a predetermined signal, the determining unit 14 outputs a second signal to the multiplex processing unit 12. So that the multiplex processing unit 12 switches to turn on a universal sequence bus channel U2. In practice, when the identification signal is determined to be greater than the first voltage, or the identification signal is determined to be smaller than the second voltage, the determining unit 14 determines that the identification signal is a preset signal, and therefore, the determining unit 14 outputs the second signal. The multiplex processing unit 12, wherein the second signal is a signal indicating that the multiplex processing unit 12 selects the universal sequence bus channel U2, so that the user can use the universal sequence bus to perform the insertion of the general universal sequence bus. Ready to use Data access operation.

It is worth mentioning that the debug test circuit 1 further includes a conversion device 18 having a first connection element 181 and a second connection element 182, wherein the first connection element 181 is used to plug in the serial bus unit 16 for connection. The second connecting component 182 is for plugging in a computer device 9. In practice, the conversion device 18 is configured to convert the universal asynchronous transceiver signal into an RS-232 interface signal, wherein the first connection component 181 is, for example, a universal serial bus (USB), a mini universal serial bus (Mini USB). a micro-universal serial bus (Micro USB) or other transmission interface for transmitting signals, and the first connection component 181 is designed to match the aspect of the universal serial bus unit 16, and the second connection component 182 is, for example, RS-232. The two connecting members 182 are designed in accordance with the state of the terminal port of the computer device 9, and the embodiment does not limit the aspect of the switching device 18.

Next, the detailed operation and circuit of the debug test circuit 1 will be further explained.

2 is a circuit diagram of a debug test circuit in accordance with another embodiment of the present invention. Please refer to Figure 2. 2 illustrates a multiplex processing unit 12 and a determination unit 14, wherein the determination unit 14 includes a comparison line 140, and the comparison line 140 is composed of a plurality of comparators OP1, OP2, a plurality of resistors R1 ^to R4, and a plurality of Capacitors C1 ^~ C4 and a plurality of diodes D1, D2.

Further, the comparison circuit 140 includes a first comparator OP1 and a second comparator OP2. The first input terminal C11 of the first comparator OP1 is coupled to a first voltage, and the second input terminal of the first comparator OP1. C12 is configured to receive the identification signal IDV, the output of the first comparator OP1 is coupled to a first diode D1, and the first input C21 of the second comparator OP2 is configured to receive the identification signal IDV, and the second comparator OP2 The second input terminal C22 is coupled to the second voltage, and the output terminal of the second comparator OP2 is coupled to the second diode D2.

The first or second comparators OP1 and OP2 are, for example, operational amplifiers, wherein the first input terminals C11 and C21 are, for example, non-inverting inputs, and the second input terminals C12 and C22 are, for example, inverting inputs. End, therefore, first Or the second comparators OP1 and OP2 are used to compare the voltages of the non-inverting input terminal and the inverting input terminal, and generate a signal opposite to the result, and the embodiment does not limit the aspect of the first or second comparators OP1 and OP2. .

Briefly, the first comparator OP1 is used to compare the voltages of the first and second input terminals C11, C12, for example, the upper limit voltage and the voltage of the identification signal IDV to generate a signal opposite to the result. When the voltage of the non-inverting input terminal is greater than the voltage of the inverting input terminal, the comparators OP1 and OP2 output a high voltage level or a high logic level. Conversely, when the voltage of the non-inverting input terminal is lower than the voltage of the inverting input terminal. The comparators OP1 and OP2 output a low voltage level or a low logic level.

Similarly, the second comparator OP2 is used to compare the voltages of the first and second input terminals C21 and C22, for example, to compare the voltage of the identification signal IDV with the lower limit voltage, and generate a signal opposite to the result. The first and second comparators OP1 and OP2 have the same functions and will not be described herein.

In addition, the first or second diodes D1 and D2 are, for example, a sinus diode, and the embodiment does not limit the aspect of the first or second diodes D1 and D2. The cathode end of the first diode OP1 is coupled to the first output terminal CO1 of the first comparator OP1, and the cathode end of the second diode D2 is coupled to the first output terminal CO1 of the second comparator OP2. The anode ends of the second diodes D1 and D2 are coupled to the SEL pins of the multiplex processing unit 12.

It is worth mentioning that the SEL pin of the multiplex processing unit 12 is coupled to the determining unit 14, the Y0 and Y1 pins of the multiplex processing unit 12 are coupled to the sequence bus bar unit 16, and the P1 and P2 of the multiplex processing unit 12. The pin is used to output or receive the universal serial bus signal, and the P3 and P4 pins are used to receive the universal asynchronous transceiver signal. The first signal or the second signal is sent from the determining unit 14 to the multiplex via the SEL pin. The processing unit 12, therefore, the multiplex processing unit 12 can output a universal sequence bus signal or a universal non-synchronous transceiver signal according to the first signal or the second signal and through the Y0 and Y1 pins.

In addition, the input node of the identification signal IDV in FIG. 2 is coupled to an adjustable resistor (not shown), and one end of the adjustable resistor is grounded, and the other end of the adjustable resistor is coupled. A conventional resistor (not shown), wherein the impedance value of the conventional resistor is a fixed value, and the other end of the conventional resistor is coupled to an operating voltage VDD. Therefore, the adjustable resistor and the conventional resistor form a The voltage dividing circuit, wherein the magnitude of the impedance of the adjustable resistor affects the voltage value of the identification signal IDV. For example, when the impedance value of the adjustable resistor is 10K ohms, the voltage value of the identification signal IDV is 2.06 volts, when the adjustable resistor is When the impedance value is 1K ohm, the voltage value of the identification signal IDV is 2.3 volts, whereby the user can adjust the impedance value of the adjustable resistor so that the voltage value of the identification signal IDV is between the first voltage and the second voltage. Therefore, the user can adjust the adjustable resistor to detect the motherboard and perform debugging operations anytime and anywhere.

3 is an identification operation table of a debug test circuit according to another embodiment of the present invention. Please refer to Figure 3 and Figure 2. For convenience of explanation, the first voltage of the present invention is, for example, 2.2 volts, and the second voltage is, for example, 1.1 volts. Therefore, the voltage of the non-inverting input terminal of the first comparator OP1 is 2.2 volts, and the phase of the second comparator OP2 is inverted. The voltage at the input is 1.1 volts, wherein the user inserts the universal serial bus unit 16 of the present invention through a universal serial bus, and this embodiment is illustrated by the identified voltage signals of 3 volts, 0 volts, and 1.5 volts. Those skilled in the art can freely design voltage values of the first and second voltages and the identification signal IDV.

In the operating state of the state 1, the determining unit 14 receives a voltage of the identification signal IDV of, for example, 3V, wherein the first comparator OP1 compares the voltage of the non-inverting input terminal with the voltage of the inverting input terminal, and therefore, the first comparator OP1 generates a low logic level signal; the second comparator OP2 compares the voltage of the non-inverting input terminal to be greater than the voltage of the inverting input terminal. Therefore, the second comparator OP2 generates a signal with a high logic level.

The SEL pin of the multiplex processing unit 12 receives a low logic level and a high logic level signal, wherein the low logic level and the high logic level signal are, for example, unequal signals, and the above are different. The signal is, for example, a second signal. Therefore, the multiplex processing unit 12 selects a universal sequence bus channel according to the second signal, and the above This function is a universal serial bus-user terminal (USB-Client), which distinguishes the motherboard side as the main port, and the pen drive device side as the slave port.

Next, in the operation state of the second state, the determining unit 14 receives the voltage of the identification signal IDV, for example, 0V, wherein the first comparator OP1 compares the voltage of the non-inverting input terminal with the voltage of the inverting input terminal, therefore, A comparator OP1 generates a high logic level signal; and a second comparator OP2 compares the voltage of the non-inverting input terminal to a voltage lower than the inverting input terminal. Therefore, the second comparator OP2 generates a low logic level signal.

The SEL pin of the multiplex processing unit 12 receives a high logic level and a low logic level signal, wherein the high logic level and the low logic level signal are, for example, unequal signals, and the above are different. The signal is, for example, a second signal. Therefore, the multiplex processing unit 12 selects a universal sequence bus channel according to the second signal, and the above function is a universal serial bus-host (USB-Host), thereby distinguishing the motherboard. The end is slave, and the pen drive device is the main one.

Thereafter, in the operating state of state three, the determining unit 14 receives a voltage of, for example, an identification signal IDV of 1.5 V, wherein the first comparator OP1 compares the voltage of the non-inverting input terminal with the voltage of the inverting input terminal, and therefore, A comparator OP1 generates a high logic level signal; and a second comparator OP2 compares the voltage of the non-inverting input terminal to a voltage greater than the inverting input terminal. Therefore, the second comparator OP2 generates a high logic level signal.

The SEL pin of the multiplex processing unit 12 receives two high logic level signals, wherein the two high logic level signals are, for example, the same signal, and the same signals are the first signals. The multiplex processing unit 12 selects a universal non-synchronous transceiver channel according to the first signal, and the above function is a debug-universal asynchronous transceiver (Debug-UART), so that the user can perform debugging operations through the computer device 9. .

4 is a flow chart of a debugging test method according to another embodiment of the present invention. See Figure 4 and Figure 1. A debugging test method, applicable to detecting a motherboard, includes: determining, in step S401, whether the universal sequence bus unit 16 receives an identification signal. In practice, when the user inserts the universal serial bus unit 16 of the present invention through the flash drive device or the device having the universal serial bus, the flash drive device or the device having the universal serial bus will generate an identification signal, and The determination unit 14 can determine whether to receive the identification signal, and if so, proceed to step S403; if not, the universal sequence bus unit 16 of the present invention maintains the original state or the standby state.

In step S403, it is determined whether the identification signal is a set signal. In practice, the determining unit 14 determines whether the identification signal is a set signal according to the identification signal, wherein the condition for determining the set signal is that the voltage of the identification signal is between the first voltage and the second voltage, when judging If the determination result of the unit 14 is YES, the process proceeds to step S405, and if the determination result of the determination unit 14 is NO, the process proceeds to step S409.

In step S405, the determining unit 14 outputs a first signal to the multiplex processing unit 12. In practice, the determination result in step S403 is YES, indicating that the universal sequence bus bar unit 16 of the present invention is plugged into a computer device 9 for performing a debugging operation, and therefore, the determining unit 14 outputs the first signal to the multiplex processing. The unit 12, wherein the first signal is a signal indicating that the multiplex processing unit 12 selects a universal non-synchronous transceiver channel.

Next, in step S407, the multiplex processing unit 12 turns on a debug channel U1 according to the first signal. In practice, the universal asynchronous transceiver channel is used for the channel of the debugging operation. Therefore, when the debugging channel U1 is turned on, the computer device 9 performing the debugging operation can receive the debugging of the central processing unit 10. The message is, for example, a debug message of the TX/RX. Therefore, the user does not need to disassemble the chassis, and the general-purpose serial bus unit 16 outside the electronic device is reserved through the motherboard for debugging, thereby improving the deletion. The convenience of wrong work.

In addition, in step S409, it is determined whether the identification signal is a preset signal. In practice, the determining unit 14 determines whether the identification signal is a preset signal according to the identification signal, wherein the condition for determining the preset signal is that the voltage of the identification signal is greater than The first voltage, or the voltage of the identification signal is less than the second voltage. When the determination result of the determining unit 14 is YES, the process proceeds to step S411, and if the determination result of the determining unit 14 is negative, the universal sequence convergence of the present invention. Row unit 16 remains in its original state or standby state.

In step S411, the determining unit 14 outputs a second signal to the multiplex processing unit 12. In practice, the determination result in step S409 is YES, indicating that the universal sequence bus bar unit 16 of the present invention is plugged into a flash drive device, and therefore, the determining unit 14 outputs the second signal to the multiplex processing unit 12, wherein The second signal is a signal for instructing the multiplex processing unit 12 to select the universal serial bus channel U2.

In step S413, the multiplex processing unit 12 turns on a general sequence bus channel U2 according to the second signal. In practice, the universal sequence bus channel U2 is used to perform a general universal sequence bus signal or power transmission channel. Therefore, when the universal sequence bus channel U2 is turned on, the above-mentioned flash drive device can receive the central processing unit. The universal sequence bus message of 10, for example, the general sequence bus message of D+/D-, allows the user to perform operations such as plug-and-play data access.

It is worth mentioning that the steps S403 ^~ S407 and steps S409 ^~ S413 can adjust the order of, for example, can be the first step S409, "determine whether the identification signal to a predetermined signal" judgment, then step S403 "determine whether the identifying signal The judgment of a setting signal", of course, according to the judgment result of step S409 or step S403, the corresponding subsequent steps will be performed. In addition, in other embodiments, steps S409 ^to S413 are steps that can be omitted. For example, steps S409 ^to S413 are defined by the specification of the original universal sequence bus, and the debug test circuit 1 performs the determination of steps S403 ^to S407. Certainly, when the determination in step S403, "determine whether the identification signal is a setting signal" is negative, it may be judged by the circuit of the original universal sequence bus specification. This embodiment does not limit the aspect of the flow of the debugging test method.

In summary, the debug test circuit of the present invention is externally coupled to a computer device for performing debug operations through a universal serial bus unit, wherein the user can insert the debug of the present invention through the universal serial bus. Test circuit According to the identification signal outputted by the universal sequence bus, to determine whether it is the first signal, when the result of the determination is the first signal, the multiplex processing unit will turn on a universal asynchronous transceiver channel, thereby saving time and reducing Cost and ease of inspection of the motherboard. In addition, when the result of the discrimination is the second signal, the multiplex processing unit will turn on a universal sequence bus channel, thereby achieving the convenience of plug-and-play data access.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

1‧‧‧Debug test circuit

9‧‧‧Computer equipment

10‧‧‧Central Processing Unit

12‧‧‧Multiworking unit

14‧‧‧judging unit

140‧‧‧Comparative lines

16‧‧‧Common sequence bus unit

18‧‧‧ Conversion device

181‧‧‧First connecting element

182‧‧‧Second connection element

U1‧‧‧Wiring channel

U2‧‧‧Universal Sequence Bus Channel

Claims (11)

A debugging test circuit is provided on a motherboard, comprising: a central processing unit; a multiplex processing unit, coupled to the central processing unit through a debug channel and a universal serial bus channel; a determining unit, The multiplex processing unit is coupled to the multiplex processing unit and coupled to the multiplex processing unit and the determining unit; wherein when the universal sequence bus unit receives an identification signal, the determining unit determines The determining signal, when determining that the identification signal belongs to a setting signal, the determining unit outputs a first signal to the multiplexing processing unit, so that the multiplexing processing unit switches to turn on the debugging channel. The debug test circuit of claim 1, wherein when the identification signal is received by the universal sequence bus unit, the identification signal is determined by the determining unit, and the identification signal is determined to be a preset. During the signal, the determining unit outputs a second signal to the multiplex processing unit, so that the multiplex processing unit switches to turn on the universal sequence bus channel. The debugging test circuit of claim 1 or 2, wherein the determining unit further comprises a comparison circuit having a first voltage and a second voltage, the first voltage being greater than the second voltage When the identification signal is determined to be between the first voltage and the second voltage, the determining unit determines that the identification signal belongs to the setting signal. The debug circuit of claim 3, wherein the comparison circuit includes a first comparator and a second comparator, a first input of the first comparator is coupled to the first voltage, A first input end of the first comparator is configured to receive the identification signal, a first output end of the first comparator is coupled to a first diode, and a first input end of the second comparator is used Receiving the identification signal, a second input end of the second comparator is coupled to the second voltage, and one of the second comparators The second output is coupled to a second diode. The debugging test circuit of claim 3, wherein the determining unit discriminates when the identification signal is determined to be greater than the first voltage, or the identification signal is determined to be smaller than the second voltage The identification signal is the preset signal. The debug test circuit of claim 2, wherein the first signal is a signal indicating that the multiplex processing unit selects a debug channel, and the second signal is to indicate that the multiplex processing unit selects a universal sequence bus Signal. The debug test circuit of claim 2, wherein the debug channel is a general-purpose asynchronous transceiver channel, and the central processing unit outputs when the multiplex processing unit turns on the universal asynchronous transceiver channel. Or receiving a universal asynchronous transceiver signal, and the universal asynchronous transceiver signal is transmitted to the multiplex processing unit via the universal asynchronous transceiver channel, and outputted through the universal serial bus unit, or the universal The asynchronous transceiver signal is input via the universal sequence bus unit for transmission to the multiplex processing unit and the central processing unit is transmitted via the universal asynchronous transceiver channel. The debug test circuit of claim 7, further comprising a conversion device having a first connection component and a second connection component, the first connection component being used to connect the universal serial bus unit, The second connecting component is connected to a computer device, and the first connecting component is a universal serial bus, the second connecting component is RS-232, and the universal asynchronous transceiver signal is transmitted to the computer device via the converting device Or the computer device transmits the universal asynchronous transceiver signal and transmits to the universal serial bus unit via the conversion device. A debugging method for detecting a motherboard having a central processing unit, a multiplexing processing unit, a determining unit, and a universal serial bus unit coupled to the central processing unit The multiplex processing unit is coupled to the central processing unit through a debug channel and a universal serial bus channel, and the debug test method includes: When the universal sequence bus unit receives an identification signal, determining whether the identification signal is a set signal, and if the determination result is yes, the determining unit outputs a first signal to the multiplex processing unit; and the multiplexing The processing unit turns on the debug channel according to the first signal. The method of determining the debug signal according to the ninth aspect of the invention, wherein the determining whether the identification signal is a set signal further comprises: determining whether the identification signal is not the set signal, determining whether the identification signal is If the identification signal is a preset signal, the determining unit outputs a second signal to the multiplex processing unit; and the multiplex processing unit turns on the universal sequence according to the second signal Bus channel. The debugging test method of claim 10, wherein the determining unit comprises a comparison line having a first voltage and a second voltage, and the first voltage is greater than the second voltage, when the identification signal When the first voltage of the comparison line is between the first voltage and the second voltage, the determining unit determines that the identification signal belongs to the setting signal; when the identification signal is greater than the first voltage of the comparison line, or When the identification signal is less than the second voltage of the comparison line, the determining unit determines that the identification signal belongs to the preset signal.