TWI517261B - Semiconductor process - Google Patents

Description

Semiconductor process

The present invention relates to a semiconductor process, and more particularly to a semiconductor process for forming a cap layer having a material different from that of a hard mask layer, and covering the two gates with a material layer and etching back, so that the two gates are equal in height.

As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster. Generally, when an epitaxial layer is formed in the substrate on the side of the gate to strain the germanium lattice, a first spacer is formed to define the position of the epitaxial layer, and then the substrate is etched to form a recess, and then An epitaxial layer is formed in the recess. After the epitaxial layer is formed, the first spacer must be completely removed to re-form a second spacer to define the location of the source/drain regions in the substrate on the side of the gate.

For a complementary metal-oxide semiconductor (CMOS) component or a static random access memory (SRAM), an NMOS transistor and a PMOS transistor system are located relative to each other. On both sides, the material of the epitaxial layer and the process of forming the PMOS transistor and the NMOS transistor are different. For example, a PMOS transistor must form a germanium epitaxial layer in the substrate on the side of the gate, while an NMOS transistor is not suitable for forming a germanium epitaxial layer, and even an NMOS transistor may have an additional germanium carbon epitaxial layer. Wait. When a germanium epitaxial layer is formed only in the substrate on the gate side of the PMOS transistor, a lithography process is performed only on the PMOS transistor to form the first spacer and form a recess, and After the epitaxial layer is formed, the first spacer is also etched away. In these steps of forming the germanium epitaxial layer, the cap layer of the PMOS transistor is etched, resulting in different thicknesses of the gates of the NMOS transistor and the PMOS transistor. Moreover, when the cap layer of the PMOS transistor is excessively etched, the gate layer under the cap layer may be exposed or the first spacer may not be completely removed.

Furthermore, in the case of a static random access memory, a method of solving the difference in the thickness of the gate of the NMOS transistor and the PMOS transistor is, for example, performing a photolithography etching process to thin the NMOS transistor. The capping layer, but the thinning process is complicated, and the photoresist of the secondary lithography process also causes a problem of inaccuracy at the junction of the NMOS transistor and the PMOS transistor, resulting in over-etching of the cap layer at the junction or Remains without covering, degrading the quality of the components formed.

Therefore, in today's industry, there is a need for a semiconductor process that can solve the problem of the gate thickness of the two transistors caused by the strain 矽 process, and the problem that the spacers in the process cannot be completely removed or the gate layer is exposed.

The invention provides a semiconductor process, which uses a material different from the hard mask layer as a cap layer, so that the hard mask layer can be completely removed in the process, and the material layer covers the two gates and is etched back again. , so that the two gates are equal.

The present invention provides a semiconductor process comprising the steps described below. First, a first gate and a second gate are formed on a substrate, wherein the first gate includes a first gate layer on the substrate and a first cap layer on the first gate layer, and The second gate includes a second gate layer on the substrate and a second cap layer on the second gate layer. Next, a hard mask layer is formed to cover the first gate and the second gate, wherein the hard mask layer is different from the material of the first cover layer and the second cover layer. Continuing, performing a lithography and etching process to pattern the hard mask layer on the second gate to form a first spacer on the side of the second gate and in the substrate on the side of the first spacer A groove is formed. Continued, an epitaxial layer is formed in the recess. Then, an etching process is performed to completely remove the remaining hard mask layer and the first spacer. Thereafter, a second spacer is formed on the sides of the first gate and the second gate, respectively.

The present invention provides a semiconductor process comprising the steps described below. First, a substrate is provided, having a first gate and a second gate, wherein the first gate includes a first gate layer on the substrate, a first nitride layer on the first gate layer, and a first gate layer The first oxide layer is on the first nitride layer, and the second gate includes a second gate layer on the substrate and a second nitride layer on the second gate layer. Then, a material layer is formed to completely cover the first gate and the second gate. Then, the material layer, the first gate and the second gate are etched back to expose the first nitride layer and the second nitride layer.

Based on the above, the present invention provides a semiconductor process that forms a cap layer different from the material of the hard mask layer on the gate, so that the hard mask layer can be completely removed without the cap layer being over-etched and exposed The problem of the gate layer. In addition, the present invention is to form a layer of material and then etch it back to planarly remove a plurality of cap layers having gates having different thicknesses so that the gates have the same thickness, thereby facilitating uniform polishing of the polishing process. The interlayer dielectric layer and the contact hole etch stop layer expose the gate layer.

1-13 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention. As shown in Fig. 1, a substrate 110 is provided. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a three-five-layer overlay substrate (eg, GaN-on-silicon), a graphene-on-silicon, or a silicon-on-silicone-on-silicon. A semiconductor substrate such as an insulator (SOI) substrate. An insulating structure 10 is formed in the substrate 110, wherein the insulating structure 10 is, for example, a shallow trench insulating structure, which can be formed by a shallow trench isolation technology. A dielectric layer 120' is formed on the substrate 110. In an embodiment using a Gate Last for High-K Last process, the dielectric layer 120' may be, for example, an oxide layer; In an embodiment of the Gate Last for High-K First process, the dielectric layer 120' may be, for example, a high-k dielectric layer, such as a high-k dielectric layer, for example It is a metal-containing dielectric layer, which may contain a hafnium oxide or a zirconium oxide, but the invention is not limited thereto. Furthermore, the high dielectric constant gate dielectric layer may be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and niobium oxynitride (hafnium). Silicon oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y _{2 )} O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO _{4 )} ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium A group consisting of titanate, Ba _x Sr _1-x TiO ₃ , BST), but the invention is not limited thereto. In addition, a buffer layer (not shown) may be selectively formed between the dielectric layer 120' and the substrate 110.

Next, a gate layer 130' is formed on the substrate 110. In this embodiment, the gate layer 130' is a sacrificial gate layer, which will be replaced by a metal gate in a subsequent process, but the invention is not limited thereto, and the sacrificial gate layer may be, for example, a polysilicon layer. . Then, a cap layer 142' is selectively formed on the gate layer 130' to form a cap layer 144' on the cap layer 142'. This embodiment includes two cover layers 142' and 144', but the cover layers of other embodiments may also be one or more layers, depending on actual needs. In this embodiment, the cap layer 142' is a nitride layer and the cap layer 144' is an oxide layer.

As shown in FIG. 2, the cap layer 144', the cap layer 142', the gate layer 130', and the dielectric layer 120' are sequentially patterned to form a first gate G1 and a second gate G2 on the substrate. 110 on. As such, the first gate G1 may include a first dielectric layer 120a and a first gate layer 130a stacked on the substrate 110 and a first cap layer 144a on the first gate layer 130a. The second gate G2 includes a second dielectric layer 120b and a second gate layer 130b stacked on the substrate 110 and a second cap layer 144b on the second gate layer 130b. In this embodiment, the first gate G1 may further include a third cap layer 142a between the first gate layer 130a and the first cap layer 144a, and the second gate G2 may further include a fourth cap layer. 142b is located between the second gate layer 130b and the second cap layer 144b. In this embodiment, the first cap layer 144a is a first oxide layer, and the second cap layer 144b is a second oxide layer; the third cap layer 142a is a first nitride layer, and the fourth cap layer 142b It is a second nitride layer, but the invention is not limited thereto. Furthermore, a side wall 150a, 150b is formed on the side of the first gate G1 and the second gate G2, respectively, wherein the sidewall spacers 150a and 150b can be formed, for example, by a thermal oxidation or deposition process.

As shown in FIG. 3, a hard mask layer 160 is formed to cover the first gate G1 and the second gate G2, wherein the hard mask layer 160 is different in material from the first cap layer 144a and the second cap layer 144b. In the present embodiment, the hard mask layer 160 is a tantalum nitride layer which is different from the material of the first cap layer 144a and the second cap layer 144b. The hard mask layer 160 is made of a material different from the first cap layer 144a and the second cap layer 144b for the subsequent lithography and etching process or etching process for the first cap layer 144a and the second cap layer 144b. The etch rate of the hard mask layer 160 is different, so that the hard mask layer 160 can be completely removed. It will be described in detail later.

As shown in FIG. 4, a lithography and etching process P1 is performed to pattern the hard mask layer 160 of the second gate G2. Specifically, a photoresist layer (not shown) may be overlaid and patterned to form a photoresist layer H covering only a first gate region A1 and exposing a second gate region A2. The hard mask layer 160 located on the second gate G2 is patterned to form a first spacer 160b on the side of the second gate G2, and the remaining hard mask layer 160a is left in the second gate region A2. . Then, the first spacer 160b is used as a hard mask, and is automatically aligned to form at least one groove R in the substrate 110 on the side of the first spacer 160b.

The material of the second cap layer 144b and the hard mask layer 160 used in the present invention are different. For example, the material having the etch rate of the second cap layer 144b is smaller than the etching rate of the hard mask layer 160 by using the lithography and etching process P1. In order to reduce the damage of the second cap layer 144b in the lithography and etching process, the first spacer 160b and the recess R can be completely formed. In detail, when the lithography and etching process P1 is performed, the hard mask layer 160 on the top of the second gate G2 has been removed, and the second gate G2 is exposed. In a general implementation, when the lithography and etching process P1 is performed, the second gate G2 is partially etched, causing the thickness t1 of the first gate G1 to be greater than the thickness t2 of the second gate G2. At this time, the difference in thickness between the two is a first thickness difference t3.

As shown in FIG. 5, an epitaxial layer 170 is formed in the recess R. In this embodiment, the epitaxial layer 170 may include a germanium epitaxial layer suitable for forming a PMOS transistor, and the first gate G1 is a gate of an NMOS transistor. Conversely, if the epitaxial layer 170 includes a germanium carbon epitaxial layer, the second gate G2 is the gate of an NMOS transistor, and the first gate G1 is a gate forming a PMOS transistor.

As shown in FIG. 6, an etching process P2 is performed on the substrate 110 in a comprehensive manner without using a mask to completely remove the remaining hard mask layer 160a and the first spacer 160b. The etching process P2 includes a wet etching process, which is, for example, a wet etching process containing phosphoric acid. The material of the second cap layer 144b and the hard mask layer 160 used in the present invention are different. For example, a material having an etching rate P2 for the second cap layer 144b and an etching rate lower than that of the hard mask layer 160 may be selected. The remaining hard mask layer 160a and the first spacer 160b are removed. When the etching process P2 is performed, the second gate G2 is partially etched, causing the thickness difference t4 of the first gate G1 and the second gate G2 to be greater than the first thickness difference t3.

It is emphasized herein that the present invention utilizes a second cap layer 144b different from the material of the hard mask layer 160, for example, the etching rate of the second cap layer 144b in the lithography and etching process P1 or the etching process P2 is lower than that of the hard layer. The mask layer 160 is completely removed to completely remove the remaining hard mask layer 160a and the first spacer 160b without leaving the first spacer 160b remaining, resulting in the definition of the width of the subsequent second spacer being inaccurate, or The problem caused by etching the gap. Moreover, there is no problem that the second cap layer 144b is excessively etched to expose the second gate layer 130b. In this embodiment, the first cap layer 144a and the second cap layer 144b are formed by the cap layer 144', so the materials of the two are the same, but in other embodiments, the first cap layer 144a and the second cap layer. The material of 144b can be different. The present invention can completely remove the first spacer 160b by separately selecting the material of the second cap layer 144b.

In this embodiment, the thickness of the third cap layer 142a is preferably smaller than the thickness of the first cap layer 144a, and the thickness of the fourth cap layer 142b is preferably smaller than the thickness of the second cap layer 144b. In a preferred embodiment, the thickness of the third cap layer 142a or the fourth cap layer 142b is, for example, 200 angstroms, and the thickness of the first cap layer 144a or the second cap layer 144b is, for example, 650 angstroms (angstroms). ). Alternatively, the thickness of the third cap layer 142a or the fourth cap layer 142b is, for example, 100 angstroms, and the thickness of the first cap layer 144a or the second cap layer 144b is, for example, 750 angstroms. Thus, the first cap layer 144a or the second cap layer 144b is not consumed when the first gate G1 and the second gate G2 are patterned. Therefore, in the lithography and etching process P1 or the etching process P2, the first gate layer 130a and the second gate layer 130b are prevented from being exposed, and the electrical quality of the gate is deteriorated.

As shown in FIG. 7, a second spacer 180 is formed on the side of the first gate G1 and the second gate G2, respectively. The second spacer 180 may include an oxide layer 182 on the outer side of the first gate G1 and the second gate G2, and a nitride layer 184 on the outer side of the oxide layer 182, but the invention is not limited thereto. Thereafter, a corresponding ion implantation process is performed to form a desired source and drain (not shown) in the substrate 110 on the side of the first gate G1 and the second gate G2, respectively.

As shown in FIG. 8, after the second spacer 180, the source and the drain are formed on the sides of the first gate G1 and the second gate G2, a cleaning process P3 may be performed to clean the first gate. G1, second gate G2, and the surface of the substrate 110. When the cleaning process P3 is performed, the second cap layer 144b is removed. P3 before cleaning processes comprising a washing process of metal silicide, such as an ammonia (NH ₃₎ and nitrogen trifluoride (NF ₃₎ cleaning processes. For example, the cleaning reaction of a cleaning process containing ammonia (NH ₃ ) and nitrogen trifluoride (NF3) can be as follows:

(1) Plasma reaction of mixed gas:

NF ₃ +NH ₃ →NH ₄ F+NH ₄ F ^‧ HF

(2) Etching reaction (generally carried out at 30 ° C):

NH ₄ F+NH ₄ F ^‧ HF+SiO ₂ →(NH ₄ ) ₂ SiF ₆ (s)+H ₂ O

(3) Sublimation reaction (generally carried out at more than 100 ° C):

(NH ₄ ) ₂ SiF ₆ (s)→SiF ₄ (g)+NH ₃ (g)

After the cleaning process P3 is performed, a metal germanide process can be performed to form the metal telluride layer 20 in the substrate 110.

As shown in FIG. 9, a protective layer 190 is selectively formed to completely cover the first gate G1 and the second gate G2. In this embodiment, the protective layer 190 is preferably the same material as the second spacer 180, the third cap layer 142a, and the fourth cap layer 142b, for example, a tantalum nitride layer, so as to be in a subsequent process. The nitride layer 184, the third cap layer 142a, and the fourth cap layer 142b of the second spacer 180 are removed together, but the invention is not limited thereto.

As shown in FIG. 10, a material layer F is formed to completely cover the first gate G1 and the second gate G2. The material layer F can be, for example, a photoresist layer.

As shown in FIG. 11, the material layer F of the portion, the protective layer 190, the first gate G1, and the second gate G2 are etched back to expose the third cap layer 142a and the fourth cap layer 142b. At this time, the first cap layer 144a above the first gate G1 is simultaneously removed. The etch back method may include a dry etching process including oxygen or fluorine, such as an oxygen plasma dry etching process, but the invention is not limited thereto.

As shown in FIG. 12, the remaining material layer F, the third cap layer 142a, the fourth cap layer 142b, and the nitride layer 184 in the second spacer 180 are sequentially removed. Since the protective layer 190 of the present embodiment is also a tantalum nitride layer, which is the same material as the nitride layer 184, the third cap layer 142a, and the fourth cap layer 142b, it can be removed together.

As shown in FIG. 13, a contact etch stop layer 30 (CESL) is formed to cover the first gate G1 and the second gate G2, and covers the first gate G1 and the second gate. The material or doping of the contact hole etch stop layer 30 of G2 may be different, and the first gate G1 and the second gate G2 may be formed on the subsequently formed transistor (for example, the first gate G1 may be used to form a PMOS transistor). And the second gate G2 can be used to form an NMOS transistor to apply different stresses. Furthermore, the contact hole etch stop layer 30 can be a single layer or a double layer, depending on actual needs. An interlayer dielectric layer 40 is formed to cover the contact hole etch stop layer 30. A planarization process P4 is performed, such as a chemical mechanical polishing process, planarizing a portion of the interlayer dielectric layer 40 and a portion of the contact hole etch stop layer 30 to expose the first gate layer 130a and the second gate layer 130b. The contact hole etch stop layer 30 may comprise a doped tantalum nitride layer and may generate different stresses for the gate channels C1, C2, and the interlayer dielectric layer 40 may be, for example, an oxide layer, but the invention is not limited thereto. this. Since the present invention forms the material layer F in advance and etches back the first gate G1 and the second gate G2 to have the same height, the polishing process P4 can uniformly polish a part of the interlayer dielectric layer 40 and a part of the contact hole. The stop layer 30 is etched to increase the electrical quality and process yield of the polished semiconductor structure 100.

Of course, the subsequent semiconductor process can be performed, for example, the first gate layer 130a and the second gate layer 130b are removed, and the barrier layer, the work function metal layer, and the main metal electrode layer are sequentially filled in, etc. The techniques well known in the art are not repeated here.

In addition, the present invention can also be applied to other semiconductor processes, taking a static random access memory as an example, and FIGS. 14-15 are schematic cross-sectional views of a static random access memory according to an embodiment. 16-19 are schematic cross-sectional views showing a static random access memory of another embodiment.

As shown in FIG. 14, an insulating structure 50, such as a shallow trench insulating structure, is located between an NMOS transistor 220 and a PMOS transistor 240. After the PMOS transistor 240 forms an epitaxial layer (not shown), the thickness of one of the cap layers 242 of the PMOS transistor 240 will be less than the thickness of one of the cap layers 244 of the NMOS transistor 220. Therefore, it is often necessary to perform a photolithography process to thin the cap layer 244. However, one of the photoresist layers 60 formed by the lithography process may cause a problem of misalignment, such as shifting to the right, resulting in repeated etching of the edge region B1. As shown in Fig. 15, a cap layer 246 of the edge region B1 has a thickness smaller than that of the cap layers 242, 244, exposing an upper portion 232p of a gate layer 232. The exposed upper half 232p causes subsequent metal halide formation thereon, causing the gate layer 232 to be difficult to remove or the gate layers 232 to be electrically connected to each other and shorted.

Conversely, as shown in FIG. 16, if it is shifted to the left, the problem of misalignment caused by the photoresist layer 60 formed by the lithography process may also cause the edge region B2 to be covered by the photoresist layer 60. A cap layer 248 and a hard mask layer 250 are not etched. As shown in FIG. 17, the thickness of the cap layer 248 of the edge region B2 is greater than that of the cap layers 242, 244, and the hard mask layer 250 for forming an epitaxial layer (not shown) remains on the cap layer 248. As shown in FIG. 18, because the hard mask layer 250 remains, a second spacer 260 which is subsequently formed on a gate 230 is directly formed on the hard mask layer 250, wherein the second spacer 260 includes a The oxide layer 262 is on the outside of the hard mask layer 250 and a nitride layer 264 is on the outside of the oxide layer 262. As shown in FIG. 19, when the second spacer 260 is removed, the hard mask layer 250 not covered by the oxide layer 262 is partially etched to form the notches d1 and d2, which reduces the static random access memory. Electrical quality.

According to the above, the problem of the misalignment at the junction caused by the use of the two lithography etching processes can be solved in the present invention. Similarly, as shown in FIG. 6, the present invention utilizes the hard mask layer 250 as a tantalum nitride layer, which is different from the material of the cap layer 242 and the cap layer 244, so that the substrate 110 can be comprehensively used without using a mask. Etching process. Thus, the static random access memory formed by the semiconductor process of the present invention does not have the problem of the notches d1, d2, because the present invention completely removes the hard mask layer 250 by using only one photolithography process.

In summary, the present invention provides a semiconductor process that forms a cap layer different from the material of the hard mask layer on the gate, thereby completely removing the hard mask layer (and the spacer formed thereby), and There is no problem with the cap layer being exposed to the underlying gate layer due to over-etching. Therefore, the present invention can improve the performance of the contact hole etch stop layer formed on the gate later. Moreover, the present invention can completely remove the hard mask layer by using only one photolithography etching process, so there is no problem of the alignment of the static random access memory.

In addition, the present invention is to form a layer of material and then etch it back to planarly remove a plurality of cap layers having gates having different thicknesses so that the gates have the same height, thereby facilitating uniform grinding of the polishing process. The interlayer dielectric layer and the contact hole etch stop layer expose the gate layer, thereby improving the electrical quality of the formed semiconductor structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Insulation structure

20. . . Metal telluride layer

30. . . Contact hole etch stop layer

40. . . Interlayer dielectric layer

50. . . Insulation structure

60, H. . . Photoresist layer

100. . . Semiconductor structure

110. . . Base

120’. . . Dielectric layer

120a. . . First dielectric layer

120b. . . Second dielectric layer

130’, 232. . . Gate layer

130a. . . First gate layer

130b. . . Second gate layer

142', 144', 242, 244, 246, 248. . . Cover

142a. . . Third cover

142b. . . Fourth cover

144a. . . First cover

144b. . . Second cover

150a, 150b. . . Side wall

160, 160a, 250. . . Hard mask layer

160b. . . First spacer

170. . . Epitaxial layer

180, 260. . . Second spacer

182, 262. . . Oxide layer

184, 264. . . Nitride layer

190. . . The protective layer

220. . . NMOS transistor

230. . . Gate

232p. . . Upper half

240. . . PMOS transistor

A1. . . First gate region

A2. . . Second gate region

B1, B2. . . Marginal zone

C1, C2. . . Gate channel

D1, d2. . . gap

F. . . Material layer

G1. . . First gate

G2. . . Second gate

P1. . . Photolithography and etching process

P2. . . Etching process

P3. . . Cleaning process

P4. . . Flattening process

R. . . Groove

T1, t2. . . thickness

T3. . . First thickness difference

T4. . . Thickness difference

1-13 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

14-15 are schematic cross-sectional views showing a static random access memory according to an embodiment.

16-19 are schematic cross-sectional views showing a static random access memory of another embodiment.

10‧‧‧Insulation structure

20‧‧‧metal telluride layer

30‧‧‧Contact hole etch stop layer

40‧‧‧Interlayer dielectric layer

100‧‧‧Semiconductor structure

110‧‧‧Base

130a‧‧‧First gate layer

130b‧‧‧second gate layer

150a, 150b‧‧‧ side wall

170‧‧‧ epitaxial layer

182‧‧‧Oxide layer

120a‧‧‧First dielectric layer

120b‧‧‧Second dielectric layer

A1‧‧‧ first gate area

A2‧‧‧second gate area

C1, C2‧‧‧ gate channel

G1‧‧‧ first gate

G2‧‧‧second gate

P4‧‧‧ Grinding process

Claims (17)

A semiconductor process includes: forming a first gate and a second gate on a substrate, wherein the first gate comprises a first gate layer on the substrate and a first cap layer is located on the substrate a gate layer, the second gate layer includes a second gate layer on the substrate, and a second cap layer on the second gate layer, wherein the first cap layer comprises a first oxide layer Located on the first gate layer, the second cap layer includes a second oxide layer on the second gate layer, and a first nitride layer is located on the first oxide layer and the first gate layer And a second nitride layer is between the second oxide layer and the second gate layer, the first nitride layer has a thickness smaller than a thickness of the first oxide layer, and the second nitride layer The thickness of the second oxide layer is smaller than the thickness of the second oxide layer; forming a hard mask layer covering the first gate and the second gate, wherein the hard mask layer and the first cap layer and the second cap layer Different materials; performing a lithography and etching process to pattern a hard mask layer on the second gate to form a first a spacer is formed on a side of the second gate, and a recess is formed in the substrate on the side of the first spacer; an epitaxial layer is formed on the recess; an etching process is performed, and the remaining portion is completely removed. The hard mask layer and the first spacer; and a second spacer formed on a side of the first gate and the second gate, respectively. The semiconductor process of claim 1, wherein the first gate is formed And the step of forming the second gate on the substrate, comprising: forming a gate layer on the substrate; forming a cap layer on the gate layer; and sequentially patterning the cap layer and the gate layer, Forming the first gate and the second gate on the substrate. The semiconductor process of claim 1, wherein the lithography and etching process has an etch rate for the second cap layer that is less than an etch rate of the hard mask layer. The semiconductor process of claim 1, wherein the etching process has an etch rate for the second cap layer that is less than an etch rate of the hard mask layer. The semiconductor process of claim 1, wherein the hard mask layer on the top of the second gate is removed while the lithography and etching process is performed to expose the second gate. The semiconductor process of claim 5, wherein the second gate is partially etched during the lithography and etching process, such that the thickness of the first gate is greater than the thickness of the second gate. And the difference in thickness between the two is a first thickness difference. The semiconductor process of claim 6, wherein the second gate is partially etched during the etching process, such that a difference in thickness between the first gate and the second gate is greater than the first thickness difference. The semiconductor process of claim 1, wherein the first nitride layer and the second nitride layer have a thickness of 200 angstroms, and the first oxide layer and the second oxide layer have a thickness. Contains 650 angstroms. The semiconductor process of claim 1, wherein the first nitride layer and the second nitride layer have a thickness of 100 angstroms, and the first oxide layer and the second oxide layer have a thickness. Contains 750 angstroms. The semiconductor process of claim 1, wherein after forming the second spacer on the side of the first gate and the second gate, further comprising performing a cleaning process to clean the first gate a pole, the second gate, and a surface of the substrate, and simultaneously removing the second oxide layer. The semiconductor process of claim 10, wherein the cleaning process comprises a metal telluride pre-cleaning process. The semiconductor process of claim 11, wherein the cleaning process comprises a cleaning process comprising ammonia (NH ₃ ) and nitrogen trifluoride (NF ₃ ). The semiconductor process of claim 1, wherein the etching process comprises a wet etching process comprising phosphoric acid. A semiconductor process includes: providing a substrate having a first gate and a second gate, wherein the first gate comprises a first gate layer on the substrate, and a first nitride layer is located on the substrate A first gate layer and a first oxide layer are disposed on the first nitride layer, and the second gate electrode includes a second gate layer on the substrate and a second nitride layer on the second gate Forming a material layer covering the first gate and the second gate; and etching back the material layer, the first gate and the second gate to expose the first nitride And a second nitride layer, wherein the material layer comprises a photoresist layer, and the etch back comprises a dry etching process comprising oxygen or fluorine. The semiconductor process of claim 14, wherein before forming the material layer, further comprising forming a protective layer covering the first gate and the second gate. The semiconductor process of claim 14, wherein the material layer, the first gate, and the second gate are etched back to expose the first nitride layer and the second nitride layer. The first oxide layer is simultaneously removed. The semiconductor process of claim 14, further comprising forming a second spacer, a side of the first gate and the second gate, and etching the material layer, After the first gate and the second gate, the method further includes: sequentially removing the remaining material layer and the second spacer; forming a contact hole etch stop layer, completely covering the first gate and the Second gate Forming an interlevel dielectric layer covering the contact hole etch stop layer; and planarizing a portion of the interlayer dielectric layer and a portion of the contact hole etch stop layer to expose the first gate layer and the second gate Floor.