TWI552209B - Method of fabricating semiconductor device - Google Patents

Description

Method of forming a semiconductor component

The present invention relates to a method of forming a semiconductor device, and more particularly to a method of simultaneously forming a high voltage transistor and a low voltage transistor.

As the size of MOS transistors continues to shrink, the polysilicon gates in conventional high-voltage or low-voltage components have reduced device performance due to boron penetration effects, increased gate dielectric (EOT) thickness, and gate capacitance. A drop in value leads to a decline in component drive capability. Therefore, the semiconductor industry has adopted a new gate material, such as the use of work function metal to replace the traditional polysilicon gate for control of high dielectric constant (High-K) gate dielectric layer. electrode.

Generally, the manufacturing method of the metal gate can be roughly divided into two categories: a gate first process and a gate last process. Among them, the front gate process will start the metal/gate bungee ultra-shallow junction activation and tempering and form a high-heat budget process such as metal telluride, which makes the selection and adjustment of materials face more challenges. In order to avoid the above-mentioned high thermal budget environment and obtain a wide choice of materials, the industry has proposed a method of replacing the front gate process by the gate process. In the conventional gate process, a sacrificial gate or a replacement gate is formed first, and after the fabrication of the general MOS transistor is completed, the sacrificial/replacement gate is removed to form a The gate trench is filled with different metals in the gate recess according to electrical requirements.

In today's semiconductor manufacturing process, it is a well-known technique to integrate a high voltage component and a low voltage component simultaneously. The operating voltage of the high voltage component is, for example, 1.8V, and the operating voltage of the low voltage component is, for example, 0.9V. . In general, high voltage transistors in high voltage components typically require a thicker gate dielectric layer. However, whether it is the front gate or the back gate process, there is little consideration to such a need, and a high voltage component having a thick gate dielectric layer and a low voltage component having a thin gate dielectric layer can be simultaneously formed.

The present invention thus proposes a method of forming a semiconductor device capable of simultaneously forming a high voltage transistor and a low voltage transistor.

According to an embodiment of the invention, the invention provides a method of forming a semiconductor component. First, a substrate is provided, and a first region and a second region are defined on the substrate. A first dielectric layer, a sacrificial layer and a sacrificial gate layer are sequentially disposed on the first region of the substrate; the sacrificial layer and the sacrificial gate layer are sequentially disposed on the second region of the substrate. A first etching step is then performed to remove the sacrificial gate layers in the first region and the second region. A second etching step is then performed to remove the sacrificial layers of the first region and the second region and expose the substrate of the second region. Finally, a second dielectric layer is formed on the substrate of the second region.

The present invention provides a method of forming a semiconductor device, which can simultaneously form a high voltage transistor and a low voltage transistor, and the thickness of the first dielectric layer in the high voltage transistor is not changed during the process, but can be appropriately controlled .

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 7 , which are schematic diagrams showing a method for fabricating a semiconductor device according to the present invention. First, a substrate 300 is provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a tantalum carbide substrate or a silicon-on-insulator (SOI). Basement, etc. The substrate 300 has a plurality of shallow trench isolation (STI) 302 thereon. The substrate 300 has a first region 400 and a second region 500. In a preferred embodiment of the present invention, the first region 400 is a high voltage device region, such as an input/output region, which can be subsequently formed to operate at 1.8 volts or higher. MOS transistor. The second region 500 is a low voltage device region, such as a core region, in which a MOS transistor operating at a voltage of 0.9 volts or less can be formed therein. A high voltage transistor 402 and a low voltage transistor 502 are formed on the substrate 300 of the first region 400 and the second region 500, respectively.

As shown in FIG. 1 , the high voltage transistor 402 includes a first dielectric layer 404 , a first sacrificial layer 405 , a first sacrificial gate 406 , a first cap layer 408 , a first sidewall sub 410 , and a first sidewall layer 410 . A first light doped drain (LDD) 412 and a first source/drain 414. In a preferred embodiment of the invention, the first dielectric layer 404 can be a cerium oxide (SiO ₂ ) layer having a thickness of substantially 30 angstroms. Preferably, the first sacrificial layer 405 is made of a material having a higher etching selectivity than the first sacrificial gate 406, the first dielectric layer 404, and the substrate 300, such as an etching selectivity ratio greater than or equal to 10:1; There may also be a preferred etch selectivity ratio between the sacrificial layer 405 and the first sidewall sub-410, such as greater than or equal to 4:1. For example, the first sacrificial layer 405 may comprise a high dielectric constant material, such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), niobium niobate oxynitride. (hafnium silicon oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta) ₂ O ₅ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ) , hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) or Barium Strontium Titanate (Ba _x Sr _1-x TiO ₃ , BST). In another embodiment of the present invention, the first sacrificial layer 405 may also be a metal/metal nitride layer, such as titanium nitride (TiN) or tantalum nitride (TaN), or a tantalum nitride (SiN) layer. . The first sacrificial gate 406 is, for example, a polysilicon gate, but may be a composite gate composed of a polycrystalline germanium layer, an amorphous silicon or a germanium layer. The first cap layer 408 is, for example, a tantalum nitride layer. The first sidewall 410 is preferably a tantalum nitride layer or a tantalum carbonitride (SiCN) layer, but may also be a composite film layer structure, which may include a high temperature oxide layer (HTO), Tantalum nitride, hafnium oxide, tantalum carbonitride (SiCN) or tantalum nitride (HCD-SiN) formed using hexachlorodisilane (Si ₂ Cl ₆ ). The first lightly doped drain 412 and the first source/drain 414 are formed with a suitable concentration of dopant.

The low voltage piezoelectric crystal 502 includes a second sacrificial layer 505, a second sacrificial gate 506, a second cap layer 508, a second sidewall sub-510, a second lightly doped drain 512, and a second source. / bungee 514. In the preferred embodiment of the present invention, the low voltage transistor 502 and the high voltage transistor 402 in FIG. 1 are formed using the same steps, so that the first sacrificial layer 405 and the second sacrificial layer 505 are made of the same material. The material of the first sacrificial gate 406 and the second sacrificial gate 506 will be the same. The implementation and formation method of the remaining components in the low voltage transistor 502 are substantially the same as those of the high voltage transistor 402, and will not be described herein. It is worth noting, however, that the low voltage transistor 502 does not have the first dielectric layer 404, that is, the second sacrificial layer 505 in the low voltage transistor 502 will directly contact the substrate 300. In addition, the preferred embodiment can also be used in conjunction with a strain 矽 process for a specific component such as the low voltage transistor 502 or a metal bismuth layer on the second source/drain 512. After the low voltage transistor 402 and the high voltage transistor 502 are formed, a contact etch stop layer (CESL) 306 and an inner dielectric layer (inter-layer dielectric) are sequentially formed on the substrate 300. , ILD) 308, overlying the high voltage transistor 402 and the low voltage transistor 502.

Next, as shown in FIG. 2, a planarization process, such as a chemical mechanical polish (CMP) process or an etch process, is performed to sequentially remove portions of the inner dielectric layer 308 and portions. The contact hole etch stop layer 306, a portion of the first sidewall sub-410, a portion of the second sidewall sub-510, and completely remove the first cap layer 408 and the second cap layer 508 until the first sacrificial gate is exposed The top surface of the pole 406 and the second sacrificial gate 506.

As shown in FIG. 3, a first etching step is performed to remove the first sacrificial gate 406 and the second sacrificial gate 506, and a first trench 416 is formed in the high voltage transistor 402, at a low level. A second trench 516 is formed in the piezoelectric crystal 502. The first etching step is, for example, a dry etching step and/or a wet etching step. The dry etching step is, for example, using an etching gas containing hydrogen bromide (HBr), nitrogen (N ₂ ) and nitrogen trifluoride (NF ₃ ), or boron trichloride (BCl ₃ ) gas, and the wet etching step is, for example, A tetramethyl ammonium hydroxide (TMAH) solution was used. In other embodiments of the present invention, different etching recipes may be selected according to different materials of the first sacrificial gate 406 and the second sacrificial gate 506. Since the materials of the first sacrificial layer 405 and the second sacrificial layer 505 have a better etching selectivity than the first sacrificial gate 406 and the second sacrificial gate 506, the first etching step stops at the first sacrificial layer. 405 and the second sacrificial layer 505, that is, the first etching step will use the first sacrificial layer 405 and the second sacrificial layer 505 as an etch stop layer.

As shown in FIG. 4, a second etching step is performed to remove the first sacrificial layer 405 and the second sacrificial layer 505 to expose the first dielectric layer 404 in the first trench 416 of the high voltage transistor 402, and The substrate 300 in the second trench 516 in the low voltage piezoelectric crystal 502. In the preferred embodiment of the present invention, the second etching step is a wet etching step, and the etching liquid is adjusted according to the materials of the first sacrificial layer 405 and the second sacrificial layer 505. For example, when the first sacrificial layer 405 and the second sacrificial layer 505 comprise a high dielectric constant material, the second etching step comprises using an etchant containing hydrofluoric acid (HF) and hydrochloric acid (HCl); When a sacrificial layer 405 and a second sacrificial layer 505 comprise a metal/metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), the second etching step comprises using an aqueous ammonia (NH ₄ OH), hydrogen peroxide (H) ₂ O ₂ ) and an etching solution of water (H ₂ O); and when the first sacrificial layer 405 and the second sacrificial layer 505 comprise tantalum nitride, the second etching step comprises using a phosphoric acid (H ₃ PO ₄ ) Etching solution. Since the materials of the first sacrificial layer 405 and the second sacrificial layer 505 have a better etching selectivity than the first dielectric layer 404 in the first trench 416 and the substrate 300 in the second trench 516, the second etching is performed. The substrate 300 in the second region 500 is exposed after the step, but the first dielectric layer 404 in the first region 400 is not removed, while the thickness of the first dielectric layer 404 is maintained.

Next, as shown in FIG. 5, a second dielectric layer 507 is formed in the second trench 516. In a preferred embodiment of the invention, the method of forming the second dielectric layer 507 includes performing a thermal oxidation process such that the substrate 300 exposed at the bottom of the second trench 516 forms a second dielectric layer 507 having hafnium oxide. In a preferred embodiment of the present invention, the thickness of the second dielectric layer 507 may be less than the first dielectric layer 404, for example, the second dielectric layer 507 is 10 angstroms, and the first dielectric layer 404 is 30 angstroms. Since the substrate 300 at the bottom of the first trench 416 has been covered by the first dielectric layer 404 containing 30 angstroms of cerium oxide, when the second dielectric layer 507 of 10 angstroms is formed in the second trench 516, the bottom of the first trench 416 The thickness of the first dielectric layer 404 hardly changes.

Then, as shown in FIG. 6, a high dielectric constant layer 317 and a work function metal layer 318 are uniformly deposited on the substrate 300, and are sequentially conformally filled into the first trench 416 and the second trench 516, but not completely. The first trench 416 and the second trench 516 are filled. Finally, a low-resistance metal layer 320 is completely deposited in the first trench 416 and the second trench 516. The high dielectric constant layer 317 includes a high dielectric constant material as described above. The work function metal layer 318 may be filled with a suitable metal depending on the electrical properties of the low voltage transistor 502, and may be, for example, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), or lanthanum aluminide. (TaAl) or hafnium aluminide (HfAl), or titanium nitride (TiN) or tantalum carbide (TaC), etc., but not limited to the above. The low-resistance metal layer 320 includes aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide. (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or a composite metal layer such as titanium and titanium nitride (Ti/TiN), but not limited thereto. In another embodiment of the present invention, the high dielectric constant layer 317 and the work function metal layer 318, or the work function metal layer 318 and the low resistance metal layer 320 may further comprise one or more barrier layers. For example, a titanium nitride layer or a tantalum nitride layer or the like.

Finally, as shown in FIG. 7, a planarization process is performed to simultaneously remove the first trench 416 and the high dielectric constant layer 317, the work function metal layer 318, and the low resistance metal layer 320 except the second trench 516. The first dielectric channel 416 and the high dielectric constant layer 317 and the work function metal layer 318 in the second trench 516 have a U-shaped cross section. At this time, the work function metal 318 and the low resistance metal layer 320 located in the first trench 416 form the first metal gate 418 of the high voltage transistor 402, and the high dielectric constant layer 317 and the first trench in the first trench 416. A dielectric layer 404 forms a first gate dielectric layer 420; and a work function metal layer 318 and a low resistance metal layer 320 in the second trench 518 form a second metal gate 518 of the low voltage transistor 502. The high dielectric constant layer 317 and the second dielectric layer 507 in the second trench 516 form a second gate dielectric layer 520. It is worth noting that the high voltage transistor 402 has a thicker first gate dielectric layer 420 than the low voltage transistor 502, and its operating voltage is greater than or equal to 1.8 volts.

In summary, the present invention provides a method of forming a semiconductor device in which a high voltage transistor having a metal gate and a low voltage transistor having a metal gate can be simultaneously formed. Since the appropriate material is selected as the first sacrificial layer and the second sacrificial layer, the first sacrificial layer and the second sacrificial layer may be used as the etch stop layer in the first etching step, and may be exposed in the second etching step. The substrate in the low voltage transistor is removed and the first dielectric layer in the high voltage transistor is retained. Therefore, the subsequent second dielectric layer will be formed only on the substrate of the low voltage transistor without affecting the thickness of the first dielectric layer in the high voltage transistor. With the method of the present invention, the thickness of the first dielectric layer in the high voltage transistor can be appropriately controlled without affecting the performance of the device.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300. . . Base

302. . . Shallow trench isolation

416. . . First ditches

418. . . First metal gate

306. . . Contact hole etch stop layer

308. . . In-layer dielectric layer

317. . . High dielectric constant layer

318. . . Work function metal layer

320. . . Low resistance metal layer

400. . . First area

402. . . High voltage crystal

404. . . First dielectric layer

405. . . First sacrificial layer

406. . . First sacrificial gate

408. . . First cover

410. . . First side wall

412. . . First lightly doped bungee

414. . . First source/dip

420. . . First gate dielectric layer

500. . . Second area

502. . . Low voltage crystal

505. . . Second sacrificial layer

506. . . Second sacrificial gate

507. . . Second dielectric layer

508. . . Second cover

510. . . Second side wall

512. . . Second lightly doped bungee

514. . . Second source/dip

516. . . Second ditches

518. . . Second metal gate

520. . . Second gate dielectric layer

1 to 7 are schematic views showing the steps of forming a semiconductor device of the present invention.

300. . . Base

302. . . Shallow trench isolation

306. . . Contact hole etch stop layer

308. . . In-layer dielectric layer

400. . . First area

404. . . First dielectric layer

410. . . First side wall

412. . . First lightly doped bungee

414. . . First source/dip

416. . . First ditches

500. . . Second area

510. . . Second side wall

512. . . Second lightly doped bungee

514. . . Second source/dip

516. . . Second ditches

Claims (20)

A method of forming a semiconductor device, comprising: providing a substrate having a first region and a second region defined thereon, the first region of the substrate sequentially having a first dielectric layer, a sacrificial layer, and a sacrificial layer a gate layer, the sacrificial layer and the sacrificial gate layer are sequentially disposed on the second region of the substrate; performing a first etching step to remove the sacrificial gate located in the first region and the second region a second etching step to simultaneously remove the sacrificial layer of the first region and the second region and expose the substrate of the second region; and form a substrate on the substrate of the second region Second dielectric layer. The method of forming a semiconductor device according to claim 1, wherein the second region does not have the first dielectric layer on the substrate. The method of forming a semiconductor device according to claim 1, wherein the sacrificial layer has an etching selectivity ratio of substantially equal to or greater than 10:1 for the sacrificial gate layer, the first dielectric layer, and the substrate. The method of forming a semiconductor device according to claim 1, wherein the first dielectric layer, the sacrificial layer, and the sidewall of the sacrificial gate of the first region have a first sidewall, the second region The sacrificial layer and the sidewall of the sacrificial gate have a second sidewall, wherein the sacrificial layer is opposite to the first sidewall and the second sidewall The wall has an etch selectivity ratio of substantially greater than or equal to 4:1. The method of forming a semiconductor device according to claim 4, wherein the first sidewall and the second sidewall include tantalum nitride. The method of forming a semiconductor device according to claim 1, wherein the sacrificial layer comprises a high dielectric constant material. The method of forming a semiconductor device according to claim 1, wherein the high dielectric constant material comprises hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and tannic acid. Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), yttrium oxide ( Tantalum oxide, Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide , ZrSiO ₄ ), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _{1- x} O ₃ , PZT) or Barium Strontium Titanate (Ba _x Sr _1-x TiO ₃ , BST). The method of forming a semiconductor device according to claim 6, wherein the second etching step comprises using an etching solution containing hydrofluoric acid (HF) and hydrochloric acid (HCl). The method of forming a semiconductor device according to claim 1, wherein the sacrificial layer comprises titanium nitride (TiN) or tantalum nitride (TaN). The method of forming a semiconductor device according to claim 9, wherein the second etching step comprises using an etching solution containing ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O). . The method of forming a semiconductor device according to claim 1, wherein the sacrificial layer comprises tantalum nitride. The method of forming a semiconductor device according to claim 11, wherein the second etching step comprises using an etching solution containing phosphoric acid (H ₃ PO ₄ ). The method of forming a semiconductor device according to claim 1, wherein the substrate comprises a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a tantalum carbide substrate or A silicon-on-insulator (SOI) substrate. The method of forming a semiconductor device according to claim 1, wherein the first dielectric layer comprises cerium oxide (SiO ₂ ). A method of forming a semiconductor device as described in claim 1, wherein the sacrifice The polar layer of the gate contains polysilicon. The method of forming a semiconductor device according to claim 1, wherein the first etching step uses the sacrificial layer as an etch stop layer. The method of forming a semiconductor device according to claim 1, wherein the first dielectric layer is further provided on the substrate of the first region after the second etching step. The method of forming a semiconductor device according to claim 1, wherein the second dielectric layer comprises ruthenium oxide. The method of forming a semiconductor device according to claim 1, wherein the method of forming the second dielectric layer comprises a thermal oxidation process. The method for forming a semiconductor device according to claim 1, further comprising forming a high dielectric constant layer and a high dielectric constant layer on the first dielectric layer of the first region and the second dielectric layer of the second region Metal layer.