TWI509713B - Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods - Google Patents

Description

Method of forming a bonded semiconductor structure and semiconductor structure formed by the method

Embodiments of the invention relate generally to methods for forming bonded semiconductor structures, and to resulting bonded semiconductor structures formed using such methods.

Three-dimensional (3D) integration of two or more semiconductor structures can yield several benefits for microelectronic applications. For example, 3D integration of microelectronic components can result in improved electrical performance and power consumption while reducing device footprint. See, for example, P. Garrou et al. "The Handbook of 3D Integration", Wiley-VCH (2008).

The 3D integration of the semiconductor structure can be performed by a semiconductor die to one or more additional semiconductor dies (ie, die-to-die (D2D)), a semiconductor die to one or more semiconductor wafers (ie, , die-to-wafer (D2W) and a combination of a semiconductor wafer to one or more additional semiconductor wafers (ie, wafer-to-wafer (W2W)) or a combination thereof.

In general, individual semiconductor structures (eg, dies or wafers) can be relatively thin and difficult to handle by means of equipment for processing semiconductor structures. Thus, so-called "carrier" dies or wafers can be attached to the actual semiconductor structure in which the active and passive components of the semiconductor device are operated. The carrier die or wafer typically does not contain any active or passive components that are intended to form one of the semiconductor devices. Such carrier dies and wafers are referred to herein as "carrier substrates." The carrier substrate is processed to process the semiconductor structure attached thereto (which will contain the active and passive components of the semiconductor device to be fabricated thereon) Active and/or passive component devices increase the overall thickness of the semiconductor structure and facilitate handling of the semiconductor structure (by providing structural support for relatively thinner semiconductor structures). In this document, an active and/or passive component of a semiconductor device to be fabricated thereon or which will ultimately comprise an active and/or passive component of a semiconductor device to be fabricated upon completion of the fabrication process is herein It is called "device substrate".

The bonding technique used in bonding one semiconductor structure to another semiconductor structure can be classified in different ways, one whether an intermediate material layer is provided between the two semiconductor structures to bond them together, and the second system bonding interface Whether electrons (ie, current) are allowed to pass through the interface. The so-called "direct bonding method" is a method in which a direct solid to solid chemical bond is established between two semiconductor structures to bond them together without using an intermediate bonding material between the two semiconductor structures. integrate. Direct metal to metal bonding methods have been developed for bonding metal materials at the surface of one of the first semiconductor structures to the metal material at one of the surfaces of a second semiconductor structure.

Direct metal to metal bonding methods can also be classified according to the temperature range in which each method is implemented. For example, certain direct metal to metal bonding processes are performed at relatively high temperatures, resulting in at least partial melting of the metallic material at the bonding interface. Such direct bonding processes may not be desirable for use in conjunction with processed semiconductor structures that include one or more device structures, as relatively high temperatures can adversely affect earlier formed device structures.

The "hot compression" bonding method is a direct combination of the following: in the range of 200 degrees Celsius (200 ° C) and about 500 degrees Celsius (500 ° C) (and usually between about A pressure is applied between the bonding surfaces at an elevated temperature between 300 degrees (300 ° C) and about 400 degrees Celsius (400 ° C).

Additional direct bonding methods have been developed that can be implemented at temperatures of 200 degrees Celsius (200 ° C) or less than 200 degrees Celsius. Such direct bonding processes carried out at temperatures of 200 degrees Celsius (200 ° C) or less than 200 degrees Celsius are referred to herein as "ultra-low temperature" direct bonding methods. The ultra-low temperature direct bonding method can be carried out by carefully removing surface impurities and surface compounds (for example, natural oxides) and by increasing the close contact area between the two surfaces on an atomic scale. The intimate contact zone between the two surfaces is typically achieved by polishing the bonding surface to reduce the surface roughness to a value close to the atomic scale; applying pressure between the bonding surfaces to cause deformation of the plastic; or The bonding surface is polished and pressure is applied to obtain the plastic deformation.

Some ultra-low temperature direct bonding methods can be carried out without applying pressure between the bonding surfaces at the bonding interface, but in other ultra-low temperature direct bonding methods, pressure can be applied between the bonding surfaces at the bonding interface to achieve a bonding interface. Suitable for bonding strength. Ultra-low temperature direct bonding methods in which pressure is applied between bonding surfaces are commonly referred to in the art as "surface assisted bonding" or "SAB" methods. Thus, as used herein, the terms "surface assisted bonding" and "SAB" mean and include any direct bonding process in which a first material is abutted against a second material and at 200 degrees Celsius (200 degrees Celsius). The first material is directly bonded to the second material by applying pressure between the bonding surfaces at the bonding interface at a temperature of °C) or less than 200 degrees Celsius.

A binder is typically used to attach the carrier substrate to the device substrate. Can also A similar bonding method is used to secure one semiconductor structure including active and/or passive components of one or more semiconductor devices to another semiconductor structure that also includes active and/or passive components of one or more semiconductor devices.

The semiconductor die may have electrical connections that do not match the connections on other semiconductor structures to which it is to be connected. An insert (i.e., an additional structure) can be placed between the two semiconductor structures or between any of the semiconductor dies and a semiconductor package to reroute and align the appropriate electrical connections. The insert can have one or more conductive traces and vias for proper contact between the desired semiconductor structures.

Embodiments of the present invention can provide methods and structures for forming semiconductor structures, and more particularly, methods and structures for forming bonded semiconductor structures. The present invention is provided to introduce a selection of concepts in the detailed description of the embodiments of the invention in a simplified form. The present invention is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

In certain embodiments, the invention comprises a method of forming a bonded semiconductor structure. According to such methods, a first semiconductor structure comprising one of at least one device structure is provided. A second semiconductor structure is bonded to the first semiconductor structure at a temperature below about 400 ° C or at a temperature. Passing through the second semiconductor structure and into the first semiconductor structure to the at least one device structure forming at least one through-wafer interconnect. Bonding the second semiconductor structure to a third semiconductor on one side thereof opposite the first semiconductor structure Body structure.

In an additional embodiment of the method of forming a bonded semiconductor structure, a first semiconductor structure comprising one of at least one device structure is provided. The ions are implanted into a second semiconductor structure to form an ion implantation plane within the second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure and the second semiconductor structure is broken along the ion implantation plane. A portion of the second semiconductor structure remains bonded to the first semiconductor structure. The at least one through-wafer interconnect is formed through the portion of the second semiconductor structure that remains bonded to the first semiconductor structure, into the first semiconductor structure, and to the at least one device structure. The second semiconductor structure is bonded to a third semiconductor structure on a side thereof opposite the first semiconductor structure.

In other embodiments, the invention encompasses semiconductor structures formed as part of the methods set forth herein. For example, a bonded semiconductor structure includes: a first semiconductor structure including at least one device structure; and a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes a portion of a relatively thick semiconductor structure that is broken. At least one through-wafer interconnect extends through the second semiconductor structure, at least partially through the first semiconductor structure, and extends to the at least one device structure.

Embodiments of the present invention can be more fully understood from the following detailed description and appended claims.

The illustrations presented herein are not intended to be a specific material, The actual views of the embodiments, which are merely illustrative of the embodiments of the invention.

The use of any of the headings herein is not to be construed as limiting the scope of the embodiments of the invention as defined by the appended claims. Throughout the specification, the concepts set forth in any particular heading generally apply to other parts.

Any reference to a reference to the subject matter claimed herein, regardless of how it is characterized herein, is not admitted as prior art.

As used herein, the term "semiconductor structure" means and encompasses any structure used in forming a semiconductor device. For example, a semiconductor structure includes a die and a wafer (for example, a carrier substrate and a device substrate) and an assembly or composite of two or more dies and/or wafers that are three-dimensionally integrated with each other. structure. The semiconductor structure also includes a fully fabricated semiconductor device and an intermediate structure formed during fabrication of the semiconductor device.

As used herein, the term "processed semiconductor structure" means and includes any semiconductor structure that includes one or more at least partially formed device structures. A subset of the semiconductor structure semiconductor structures are processed, and all of the processed semiconductor structures are semiconductor structures.

As used herein, the term "bonded semiconductor structure" means and includes any structure comprising two or more semiconductor structures attached together. The bonded semiconductor structure is a subset of the semiconductor structure, and all of the bonded semiconductor structures are semiconductor structures. In addition, a semiconductor structure comprising a combination of one or more processed semiconductor structures is also a processed semiconductor structure.

As used herein, the term "device structure" means and includes any portion of a processed semiconductor structure, that is, includes or defines at least one active or passive component of a semiconductor device to be formed on or in a semiconductor structure. portion. For example, the device structure includes active and passive components of the integrated circuit, such as transistors, converters, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

As used herein, the term "through-wafer interconnect" or "TWI" means and includes any conductive via extending through at least a portion of a first semiconductor structure for crossing the first An interface between a semiconductor structure and a second semiconductor structure provides a structure and/or an electrical interconnection between the first semiconductor structure and the second semiconductor structure. Through-wafer interconnects are also referred to in the art as other terms such as "via/substrate vias" or "TSVs" and "through-wafer vias" or "TWVs". The TWI typically extends through the semiconductor structure in a direction generally perpendicular to one of the generally planar major surfaces of a semiconductor structure (in a direction parallel to one of the Z axes).

As used herein, the term "active surface", when used in connection with a treated semiconductor structure, means and includes one of the processed semiconductor structures exposed to the major surface, the processed semiconductor structure has been processed or will be processed to be processed in the process. One or more device structures are formed in and/or on the exposed major surface of the semiconductor structure.

As used herein, the term "back surface", when used in connection with a treated semiconductor structure, means and includes one of the treated semiconductor structures exposed to the major surface, the exposed major surface being located opposite the active surface of the semiconductor structure. One side of the treated semiconductor structure.

As used herein, the term "III-V type semiconductor material" means and includes one or more elements (B, Al, Ga, In, and Ti) from Group IIIA of the periodic table and VA from the periodic table. Any of a number of elements (N, P, As, Sb, and Bi).

As used herein, the term "coefficient of thermal expansion" when used in reference to a material or structure means the average linear coefficient of thermal expansion of the material or structure at room temperature.

Embodiments of the invention include methods and structures for forming semiconductor structures, and more particularly semiconductor structures including bonded semiconductor structures and methods of forming such bonded semiconductor structures. Through-wafer interconnects may be formed within such semiconductor structures, and such through-wafer interconnects may be used in place of separate interposers between structures. The through-wafer interconnects may be completely formed from an active surface, or the through-wafer interconnects may be formed hierarchically from both the active surface and the back surface.

In some embodiments, through-wafer interconnects and/or electrically isolated thermal management structures can be used to improve the thermal resistance in bonded semiconductor structures. In some embodiments, a through-wafer interconnect and/or an electrically isolated thermal management structure can be used to improve the mismatch in thermal expansion coefficient between a semiconductor structure and other structures to which the semiconductor structure can be attached. Embodiments of the methods and structures of the present invention may be utilized for a variety of purposes, such as 3D integration processes and for forming 3D integrated structures. The plurality of semiconductor structures formed by the method of the embodiments of the present invention may be stacked one on another to connect the active or back surface of one semiconductor structure to the active or back surface of another semiconductor structure. The remaining surface of each structure can be attached to an additional structure.

Exemplary embodiments of the present invention are described below with reference to FIGS. 1 through 39.

In one embodiment, the invention includes providing a first semiconductor structure 100 having an active surface 102 and a back surface 104, as shown in FIG. The active surface 102 can be located on a first side of the first semiconductor structure 100 with the back surface 104 on a second opposing side. The first semiconductor structure 100 can include at least one device structure 108 formed in and/or over a substrate 106. For example, substrate 106 can include one or more semiconductor materials such as germanium (Si), germanium (Ge), a III-V semiconductor material, and the like. Additionally, substrate 106 can comprise a single crystalline semiconductor material and can include one or more epitaxial layers of semiconductor material. In additional embodiments, substrate 106 may comprise one or more dielectric materials such as an oxide (for example, cerium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), a nitride (for example, , tantalum nitride (Si ₃ N ₄ ), boron nitride (BN), and the like.

Referring briefly to FIG. 5, a second semiconductor structure 112 can be provided over (eg, over) the active surface 102 of the first semiconductor structure 100 to form a bonded semiconductor structure 500. The second semiconductor structure 112 can include a relatively thin layer of material, such as any of the materials mentioned above in connection with the substrate 106. By way of example and not limitation, second semiconductor structure 112 can have an average thickness of about 1 micron or less, about 0.5 micron or less than 0.5 micron, or even about 0.07 micron or less than 0.07 micron.

As a non-limiting example, may be referred to as a SMART-CUT ^TM using the process of the process in the art to the action of the first upper surface 102 of the semiconductor structure 100 provides a second semiconductor structure 112. For example, as shown in FIG. 3, a semiconductor structure 300 including a bonding layer 110 can be formed. Bonding layer 110 can include one or more layers of bonding material, such as hafnium oxide, tantalum nitride, and mixtures thereof. Bonding layer 110 can be formed over active surface 102 of first semiconductor structure 100 to form a planarized surface, thereby improving the bonding to subsequent semiconductor structures.

The bonding layer 110 can be disposed between the active surface 102 of the first semiconductor structure 100 and another semiconductor material layer 111 and can be used to bond the first semiconductor structure 100 to the semiconductor material layer 111. The bonding layer 110 can be used to bond the first semiconductor structure 100 to the semiconductor material layer 111 at a temperature of about 400 ° C or less or even about 350 ° C or less than 350 ° C to avoid causing the first semiconductor structure 100 to be The device structure 108 is thermally damaged.

In certain embodiments of the invention, the layer of semiconductor material 111 may comprise an integral semiconductor substrate, such as germanium, germanium or a III-V compound semiconductor. In some embodiments, the layer of semiconductor material 111 can include one or more epitaxial layers disposed on one another to form a semiconductor layer structure. In some embodiments of the invention, the layer of semiconductor material 111 can be attached to an optional sacrificial substrate 115, as shown in the ghost image of FIG. The sacrificial substrate 115 may be attached to the semiconductor material layer 111 on one side thereof opposite to the first semiconductor structure 100.

A portion 113 of the semiconductor material layer 111 (along with the sacrificial substrate 115) may be removed from the semiconductor material layer 111, leaving a second semiconductor structure 112. In other words, the semiconductor structure 200 (FIG. 2) and the second semiconductor structure 112 can be removed from the portion 113 of the semiconductor material layer 111 (in conjunction with the optional sacrificial substrate 115) to form an intermediate structure 400, as in FIG. Shown.

By way of example and not limitation, the SMART-CUT ^(TM) process can be used to separate portions 113 of semiconductor material layer 111 (and sacrificial substrate 115 (where utilized) from semiconductor structure 200 and semiconductor structure 112. For example, such processes are described in detail in the following patents: U.S. Patent No. RE 39,484, issued to Bruel, issued on Feb. 6, 2007, and U.S. Patent No. 6,303,468, issued to Aspar et al. U.S. Patent No. 6,335,258 issued to Aspar et al. (issued Jan. 1, 2002), U.S. Patent No. 6,756,286 to Morriceau et al. (issued on June 29, 2004), and U.S. Patent No. 6,809,044 to Aspar et al. (Promulgated on October 26, 2004), and U.S. Patent No. 6,946,365 to Aspar et al. (September 20, 2005).

In short, a plurality of ions (eg, one or more of hydrogen ions, helium ions, or inert gas ions) may be implanted into the semiconductor material layer 111. In some embodiments of the invention, the plurality of ions may be implanted into the layer of semiconductor material 111 prior to bonding the layer of semiconductor material 111 to the semiconductor structure 200. For example, an ion source (not shown) that is self-localized on one side of the layer of semiconductor material 111 adjacent the surface 105 can be implanted into the layer of semiconductor material 111 prior to bonding, as illustrated in FIG.

The ions may be implanted in a direction substantially perpendicular to one of the layers of the semiconductor material 111. As is known in the art, the depth of implantation of the plasma into the layer of semiconductor material 111 is at least partially a function of the energy with which the plasma is implanted into the layer of semiconductor material 111. In general, ions implanted with less energy will be implanted at a relatively shallow depth, while ions implanted with higher energy will be implanted at a relatively deeper depth.

The ions can be implanted into the semiconductor material layer 111 by a predetermined energy, The predetermined energy is selected to implant the plasma at a desired depth within one of the layers of semiconductor material 111. The plasma may be implanted into the semiconductor material layer 111 before or after the semiconductor material layer 111 is bonded to the first semiconductor structure 100. As a specific, non-limiting example, the ion implantation plane 117 can be disposed within the semiconductor material layer 111 at a depth from one of the surfaces 105 such that the average thickness of the second semiconductor structure 112 is between about 1000 nm (1000 nm) ) extends to a range of approximately 100 nanometers (100 nm). As is known in the art, inevitably, at least some of the ions may be implanted at a depth other than the desired implant depth, and with the exposed surface 105 of the semiconductor material layer 111 (eg, prior to bonding) A graph of ion concentration as a function of depth in the layer of semiconductor material 111 may exhibit a generally bell-shaped (symmetric or asymmetrical) curve having a maximum at a desired implant depth.

When ions are implanted into the layer of semiconductor material 111, the plasma can define an ion implantation plane 117 (illustrated as a dashed line in FIG. 3) within the layer of semiconductor material 111. The ion implantation plane 117 can include a layer or region within the layer of semiconductor material 111 that is aligned (e.g., centered) with the plane having the greatest ion concentration within the semiconductor structure 300. The ion implantation plane 117 can define a weakened partition within the semiconductor structure 300 along which the thinned semiconductor structure 300 can be cracked or broken during a subsequent process. For example, the semiconductor structure 300 can be heated to cause the semiconductor structure 300 to crack or break along the ion implantation plane 117. However, during this cleavage process, the temperature of the semiconductor structure 300 can be maintained at about 400 ° C or less, or even at about 350 ° C or less, to avoid damaging the first semiconductor structure 100. Any device structure 108 in it. Optionally, a force can be applied to the semiconductor structure 300 to cause or assist in rupturing the semiconductor structure 300 along the ion implantation plane 117.

In an additional embodiment, the first semiconductor structure 100 can be bonded to the first semiconductor structure 100 and then to the first semiconductor from the relatively thick material layer by a relatively thick layer of material (eg, one having an average thickness of greater than about 100 microns) The structure 100 is thinned relative to the side to provide a second semiconductor structure 112 over the active surface 102 of the first semiconductor structure 100. For example, as shown in FIG. 2, a bonding layer 110 (such as an oxide layer) including one or more bonding materials may be provided over (eg, over) the active surface 102 of the first semiconductor structure 100. As shown in FIG. 4, a bonding surface 114 of a second semiconductor structure 112 can be bonded to the bonding layer 110 on the active surface 102. In an additional embodiment, the bonding layer 110 can be provided on the bonding surface 114 of the second semiconductor structure 112 or on both the active surface 102 of the first semiconductor structure 100 and the bonding surface 114 of the second semiconductor structure 112.

The second semiconductor structure 112 can be thinned by exposing the primary surface removal material from one of the second semiconductor structures 112, for example, a chemical process (eg, a wet or dry chemical etch process), The second semiconductor structure 112 is thinned by a mechanical process (e.g., a grinding or buffing process) or by a chemical-mechanical polishing (CMP) process. These processes can be performed at a temperature of about 400 ° C or less or even about 350 ° C or less than 350 ° C or at a temperature to avoid damaging any device structure 108 in the first semiconductor structure 100 .

In still other embodiments, the action table of the first semiconductor structure 100 can be A second semiconductor structure 112 is formed in situ over the face 102 (eg, thereon). For example, a material of the second semiconductor structure 112 (such as one or more of germanium, polysilicon or amorphous germanium) may be deposited on the active surface 102 of the first semiconductor structure 100 to a desired thickness. Two semiconductors 112. By way of example and not limitation, second semiconductor structure 112 can have an average thickness of about 1 micron or less, about 0.5 micron or less than 0.5 micron, or even about 0.3 micron or less than 0.3 micron. In such embodiments, the deposition process can be performed at a temperature of about 400 ° C or less or even about 350 ° C or less than 350 ° C or at a temperature to avoid damaging any device structure 108 in the first semiconductor structure 100 . . For example, a low temperature deposition process for forming a second semiconductor structure 112 can be performed by utilizing a plasma enhanced chemical vapor deposition process, as is known in the art.

As shown in FIG. 5, at least one through-wafer interconnect 116 can be formed structurally and electrically connected through the second semiconductor structure 112 to the first semiconductor structure 100 and a conductive device structure 108. In other words, each through-wafer interconnect 116 can extend to one or more device structures 108 such that physical and electrical contact is established between the through-wafer interconnect 116 and one or more device structures 108.

The hole or via may be etched through the second semiconductor structure 112 to the first semiconductor structure 100 and then filled with one or more conductive materials or formed by any other method known in the art. Wafer interconnect 116. Optionally, another bonding layer 118 (such as one) may be provided on the exposed major surface of the second semiconductor structure 112 in a low temperature process (eg, about 400 ° C or less or even about 350 ° C or less than 350 ° C). The oxide layer) forms the semiconductor structure 500 of FIG. Can form at least one A bonding layer 118 is formed over the second semiconductor structure 112 prior to the through wafer interconnect 116. Likewise, each of the processes for forming the through-wafer interconnects 116 can be performed at a temperature of about 400 ° C or less or even about 350 ° C or less than 350 ° C (including forming the hole) Or through holes and fill the holes or vias with a conductive material to avoid damaging the device structure 108.

As shown in FIG. 6, a third semiconductor structure 120 can be bonded to the active surface 102' of the semiconductor structure 500 through the bonding interface 119 to form a bonded semiconductor structure 600. This bonding process can be carried out at a low temperature of about 400 ° C or less or even about 350 ° C or less than 350 ° C to avoid damaging the device structure 108. In some embodiments, the third semiconductor structure 120 can be at least substantially similar to the semiconductor structure 500 shown in FIG. 5 (and can be formed as described above in connection with the semiconductor structure 500). The third semiconductor structure 120 can be at least substantially similar to the semiconductor structure 500, but can include a different configuration of one of the device structures 108'.

The third semiconductor structure 120 can have one of the active surfaces on one of the first sides of the third semiconductor structure 120 and one of the back surfaces on a second opposing side. The third semiconductor structure can include a substrate 106' and at least one device structure 108' formed in and/or over the substrate 106'. The second semiconductor structure 112 can serve as an interposer between the third semiconductor structure 120 and the first semiconductor structure 100. As shown in FIG. 6, the third semiconductor structure 120 may also include a second semiconductor structure 112' as described above, and the second semiconductor structure 112' may also serve as a relationship between the third semiconductor structure 120 and the semiconductor structure 500. An insert.

The third semiconductor structure 120 can be interpenetrated with at least one of the semiconductor structures 500 The round interconnect 116 makes electrical contact. For example, the through-wafer interconnect 116' of the third semiconductor structure 120 can be bonded to the through-wafer interconnect 116 (eg, structurally coupled and electrically coupled thereto) through the bonding interface 119 to form the semiconductor structure 500. .

In some embodiments, the through-wafer interconnect 116' can be bonded to the through-wafer interconnect 116 in the following manner: in the through-wafer interconnect 116' and the through-wafer interconnect 116 Providing a metal material conductive bump or ball (for example, a solder alloy) on one or both; and heating the metal material conductive bump or ball to cause the conductive bump or the metal material in the ball to melt and reflow; The metal material can then be cooled and cured to form a bond between the through wafer interconnect 116' and the through wafer interconnect 116. In such embodiments, the metal material conductive bump or metal material in the ball may have a melting point below about 400 ° C or even below about 350 ° C to allow the bonding process to be performed at this relatively low temperature to avoid damage to the device. Structures 108, 108'.

In additional embodiments, the through-wafer interconnect 116' can be bonded directly to the through-wafer interconnect 116 in a direct metal-to-metal bonding process without the need to provide any adhesive or other bonding material therebetween. For example, the direct bonding process can include any of a thermal compression direct bonding process, an ultra-low temperature direct bonding process, and a surface assisted direct bonding process, as previously defined herein.

In some embodiments, the bonding layer 118 (such as an oxide layer) or other bonding material can be used to bond the third semiconductor structure 120 to the semiconductor structure 500. Likewise, the bonding process can be carried out at temperatures below about 400 ° C or even below about 350 ° C or at several temperatures to avoid damaging the device junction. Structure 108, 108'.

In one embodiment, the semiconductor structure 500 can be placed in electrical contact with another substrate 122, such as a circuit board, as shown in FIG. The semiconductor structure 500 can have conductive bumps 123 that connect the semiconductor structure 500 to the substrate 122. Conductive bumps 123 may be made of gold, copper, silver, or another conductive metal and may be deposited onto the vial interconnect 116 by depositing material onto the substrate 122 or by the art. Formed by any other method known. In this embodiment, the second semiconductor structure 112 also serves as an interposer between the first semiconductor structure 100 and the substrate 122.

In another embodiment, shown as semiconductor structure 800 in FIG. 8, at least one thermal management structure 124 can be formed in second semiconductor structure 112. The thermal management structure 124 can be formed by etching a hole or via in the second semiconductor structure 112 and then filling the hole or via with one or more conductive materials or by any other method known in the art. The thermal management structure 124 can extend into the first semiconductor structure 100 or into the first semiconductor structure 100, as shown in FIG.

FIG. 9 illustrates an additional embodiment of one of the semiconductor structures 900 similar to the semiconductor structure 800, but in the semiconductor structure 900 the thermal management structure 124 is completely disposed within the second semiconductor structure 112. In semiconductor structures 800 and 900, thermal management structure 124 can include at least one "dummy" pad or structure formed from a relatively thermally conductive material, such as a metal that is electrically isolated from any device structure 108.

Figure 10 is a diagram illustrating the attachment of a third semiconductor structure 120 to the semiconductor structure 800 of Figure 8 (or the semiconductor of Figure 9) as previously described. Structure 900) is a method of forming the resulting semiconductor structure 1000 of one of the ones shown in FIG. The third semiconductor 120 itself may comprise a fourth semiconductor structure 112' bonded to one of the active surfaces of the third semiconductor structure 120. The at least one through wafer interconnect 116 can connect the semiconductor structure 500 to the third semiconductor structure 120 through the second semiconductor structure 112 and the fourth semiconductor structure 112'.

Thermal management structure 124 can be used to improve thermal management of the system by balancing vertical thermal resistance with lateral thermal diffusion. The thermal expansion coefficient exhibited by the insert including the second semiconductor structure 112 having the thermal management structure 124 can be tailored to a desired value by varying the size, number, composition, placement, shape or depth of the thermal management structure 124.

For example, the thermal expansion coefficient of the insert can be trimmed to at least substantially match the coefficient of thermal expansion of the first semiconductor structure 100 to which the insert is attached, or at least substantially match the semiconductor structure 800 or 900 to which it can be attached The coefficient of thermal expansion of a structure (e.g., the third semiconductor structure 120 of FIG. 10). Thermal management structure 124 may be formed from one or more metals, such as copper, tungsten, aluminum, or any other material based on one or more of these metals or relatively thermally conductive. The size, number, composition, placement, shape or depth of the through-wafer interconnects 116 can also be varied to cause the insert to exhibit a desired coefficient of thermal expansion. In some embodiments, the ratio of the thermal expansion coefficient of the interposer (the second semiconductor structure 112 having the thermal management structure 124) to the thermal expansion coefficient of the first semiconductor structure 100 can range from about 0.67 to about 1.5. Within, extending from about 0.9 to about 1.1 or the ratio may be about 1.0. That is, the coefficient of thermal expansion of the insert can be at least substantially equal to the coefficient of thermal expansion of the first semiconductor structure 100.

In some embodiments of the invention, two sets of through-wafer interconnects can be formed from opposite sides of a semiconductor structure. That is, one can be formed through the active surface as set forth above and the other can be formed through a back surface. The through-wafer interconnects can be connected to one another within the semiconductor structure and can transmit electrical signals to other device structures through the semiconductor structures.

For example, a semiconductor structure 1100 (shown in FIG. 11) has one of the active surfaces 202 on a first side of the semiconductor structure 1100 and one back surface 204 on a second opposite side of the semiconductor structure 1100. The semiconductor structure 1100 can have at least one device structure 208 formed in and/or over a substrate 206. The substrate 206 can include a semiconductor 210 and an insulator 212. Substrate 206 may further include one or more additional layers 214, such as an additional layer of semiconductor material. Semiconductor 210 can include one or more layers of a semiconductor material such as germanium (Si), germanium (Ge), a III-V semiconductor material, and the like. Additionally, substrate 206 can comprise a single crystal material or a layer of epitaxial semiconductor material. The insulator 212 may include one or more layers of dielectric material such as an oxide (for example, cerium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), a nitride (for example, tantalum nitride ( Si ₃ N ₄ ) or boron nitride (BN)).

At least one first through wafer interconnect 216 can be formed through the semiconductor structure 1100 to form the semiconductor structure 1200, as shown in FIG. At least one first through-wafer interconnect 216 can be formed from the active surface 120 in part through the substrate 206 in connection with the at least one device structure 208. In other words, each first through-wafer interconnect 216 can extend to one or more device structures 208 such that physical and electrical contact is established between the first through-wafer interconnect 216 and one or more device structures 208 . A hole or via can be etched through the semiconductor structure 1100 The via or via is then filled with one or more conductive materials or the first through wafer interconnect 216 is formed by any other method known in the art. These processes can be carried out at a temperature of about 400 ° C or less or even less than 350 ° C or less than 350 ° C or several temperatures, as previously discussed.

Optionally, one or more additional layers 217 may be added to the active surface of the semiconductor structure 1200, as shown in FIG. One or more additional layers 217 can include several additional bonding layers. The additional bonding layers can be utilized to planarize the active surface 202 of the semiconductor structure 1200 to help bond the semiconductor structure 1200 to a carrier substrate 220. When additional layer 217 is added, the last added layer includes active surface 202. The active surface 202 can be bonded to one of the bonding surfaces 218 of the carrier substrate 220 to form the semiconductor structure 1300 of FIG. Where the carrier substrate 220 provides structural support, the material may be removed from the substrate 206 of the semiconductor structure 1300 by, for example, a chemical mechanical polishing (CMP) process or any other method known in the art. The substrate 206 is thinned. These processes may also be carried out at a temperature of about 400 ° C or less or even less than about 350 ° C or less than 350 ° C or several temperatures, as previously discussed.

As shown in FIGS. 14 and 15, at least one second through-wafer interconnect 222 can be formed through a portion of the thinned substrate 206. The second through-wafer interconnect 222 can be positioned and oriented such that physical and electrical contact is established between the second through-wafer interconnect 222 and the first through-wafer interconnect 216. Thus, an electrical connection is established between the device structure 208 and the second through-wafer interconnect 222 through the first through-wafer interconnect 216.

The second through wafer interconnect 222 can have a different than the first through wafer interconnect One of the cross-sectional sizes and/or shapes of 216. For example, the second through-wafer interconnect 222 can be smaller in cross-sectional size than the first through-wafer interconnect 216, as illustrated in the semiconductor structure 1400 of FIG. In an additional embodiment, the second through-wafer interconnect 222 can be larger in cross-sectional size than the first through-wafer interconnect 216, as illustrated in the semiconductor structure 1500 of FIG. In still other embodiments, the second through-wafer interconnect 222 can have the same cross-sectional size as the first through-wafer interconnect 216. The size and number of both the first through wafer interconnect 216, the second through wafer interconnect 222 or the first through wafer interconnect 216 and the second through wafer interconnect 222 can be changed by The thermal expansion coefficients of the semiconductor structures 1400 and 1500 are tailored to a desired value by composition, placement, and/or depth.

Forming a second through-wafer interconnect separately from the first through-wafer interconnect 216 is compared to forming a through-wafer interconnect through the substrate 206 that completely passes through the semiconductor structure 1100 (FIG. 11) in a single step Piece 222 can produce a higher yield. Forming the second through-wafer interconnect 222 separately from the first through-wafer interconnect can be achieved by reducing the aspect ratio (AR) of the etch process and because the second through-wafer interconnect 222 can pass completely through A single homogeneous material is formed to improve yield.

The second through-wafer interconnect 222 can be formed at a temperature of about 400 ° C or less or even less than about 350 ° C or less than 350 ° C or a number of temperatures using the methods set forth previously.

In some embodiments, a first through-wafer interconnect 216 can be formed to a different depth within a semiconductor structure. That is, the first through wafer interconnect 216 can be formed through more or less layers of material than those set forth above. A second through wafer interconnect 222 can then be formed such that it touches the first through wafer The piece 216 is in electrical contact.

For example, as shown in FIG. 16, semiconductor structure 1600 has one of active surface 202 on one of the first sides of semiconductor structure 1600 and one back surface 204 on one of the second opposite sides of semiconductor structure 1600. The semiconductor structure 1600 can have at least one device structure 208 formed in and/or over a substrate 206. The substrate 206 can include a semiconductor 210 and an insulator 212. Substrate 206 may further include one or more additional layers 214, such as an additional layer of semiconductor material. Semiconductor 210 can include one or more layers of a semiconductor material such as germanium (Si), germanium (Ge), a III-V semiconductor material, and the like. Additionally, substrate 206 can comprise a single crystal material or a layer of epitaxial semiconductor material. The insulator 212 may include one or more layers of dielectric material such as an oxide (for example, cerium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), a nitride (for example, tantalum nitride ( Si ₃ N ₄ ) or boron nitride (BN)).

A first through wafer interconnect 216 can be formed through the semiconductor structure 1600 (through the semiconductor 210 from the active surface 202 and at least partially through the insulator 212). The first through wafer interconnect 216 can be formed as described above and can extend through one or more device structures 208 or to one or more device structures 208.

Optionally, one or more additional layers 217 (eg, additional bonding layers) may be added to the active surface 202 of the semiconductor structure 1600 to form the semiconductor structure 1700 shown in FIG. When additional layer 217 is added, the last added layer includes active surface 202. The active surface 202 can be bonded to one of the bonding surfaces 218 of a carrier substrate 220 to form a semiconductor structure 1700. Where structural support is provided by the carrier substrate 220, for example, chemical mechanical sectioning may be used Light or any other method known in the art thins the substrate 206 by removing material from the substrate 206 of the semiconductor structure 1700.

At least one second through-wafer interconnect 222 can then be formed through one or more additional layers 214 and insulator 212 to form semiconductor structures 1800 and 1900 of FIGS. 18 and 19. The second through wafer interconnect 222 can have a cross-section that is different from a cross-section of the first through-wafer interconnect 216 in at least one of size and shape. For example, the cross-section of the second through-wafer interconnect 222 can be smaller than the cross-section of the first through-wafer interconnect 216 (as in the semiconductor structure 1800 of FIG. 18) or larger than the first through-wafer interconnect 216. The profile (as in the semiconductor structure 1900 of Figure 19). In additional embodiments, the second through-wafer interconnect 222 can have a cross-section that is the same size and shape as the cross-section of the first through-wafer interconnect 216. The thermal expansion coefficients of the semiconductor structures 1800 and 1900 can be tailored by varying the size, number, composition, placement, shape or depth of the first through wafer interconnect 216, the second through wafer interconnect 222, or both. For an expected value.

The first through wafer interconnect 216 and the second through wafer interconnect 222 may be formed at a temperature of about 400 ° C or less or even about 350 ° C or less than 350 ° C or a plurality of temperatures to avoid damage to the device structure 208, as previously discussed.

20 shows an enlarged view of one of the portions of the semiconductor structure 1800 of FIG. 18, and FIG. 21 shows an enlarged view of a portion of the dotted circle shown in FIG. As shown in FIG. 21, in some embodiments, an etch stop 224 can be disposed between the semiconductor 210 and the insulator 212 to help form the first through wafer interconnect 216 and the second through wafer interconnect. 222, as discussed below.

The first through wafer interconnect 216 can be formed in a manner similar to that previously described with reference to FIG. However, in the embodiments set forth below, the addition of an etch stop 224 can aid in the fabrication of the through-wafer interconnect. For example, a patterned mask layer (not shown) can be applied to the active surface 202 to protect areas that are not to be etched. The structure exposed through the patterned mask layer can then be subjected to a selective etchant using a wet chemical etching process, a dry reactive ion etching process, or any other etching process known in the art. The structure can be selectively etched to etch stop 224 to form a hole or via in the structure. In other words, the etch process will etch through the semiconductor structure 1800 and selectively stop on the etch stop 224. Etch stop 224 can include a layer of material that will not be etched or will be etched at a rate substantially lower than one of the surrounding materials. By way of example and not limitation, etch stop 224 may comprise a layer of a nitride material such as tantalum nitride (Si ₃ N ₄ ). Etch stop 224 may be located between several layers of substrate 206, in which case one or more layers may be etched with the structure. Once a hole or via has been etched into the structure to the etch stop 224, the hole or via may be filled with one or more conductive materials to form the first through wafer interconnect 216.

The second through wafer interconnect 222 can be formed in a similar manner. First, a patterned mask layer (not shown) can be applied to the back surface 204 to protect areas that are not to be etched. The substrate 206 exposed through the patterned mask layer can then be subjected to a selective etchant using a wet chemical etching process, a dry reactive ion etching process, or any other etching process known in the art. Substrate 206 can be selectively etched to etch stop 224. The etch process etches through the semiconductor structure and selectively stops at the etch stop 224. To connect the second through wafer interconnect to the first through wafer interconnect, the material of the etch stop 224 exposed within the via or hole can be removed. As previously mentioned, the etch stop 224 can be made of a material that is substantially impermeable to one of the etchants used to form holes or vias through the structure and substrate 206. In other words, the etch rate of a selected etch process through the etch stop can be substantially slower than the etch rate through the structure and substrate 206. To remove the etch stop 224 and allow electrical connection between the through wafer interconnect 216 and the through wafer interconnect 222, a different etch process or chemical process can be selected. The different etch process can be substantially higher than a rate removal etch stop 224 for the etch rate of the etch process used to form holes or vias through the structure and substrate 206. This different etching process may be ineffective for etching the structure and other materials of the substrate 206.

In FIG. 21, an example of device structure 208 is shown as a transistor 208' that includes a source region 230, a gate electrode 231, and a drain region 232. These features are by way of example only and are not intended to limit the type of device structure 208 in semiconductor structure 1800. At least one shallow trench isolation structure 226 can be disposed adjacent (eg, around) the first through wafer interconnect 216. Shallow trench isolation structure 226 can isolate through-wafer interconnects 216 and 222 from at least one device structure 208 and isolate additional device structures (not shown) from device structure 208'.

In some embodiments, at least a portion of the second through-wafer interconnect 222 can extend laterally and overlap a portion of the semiconductor 210, and the second through-wafer interconnect 222 can extend laterally beyond the shallow trench isolation structure 226 A peripheral boundary, as shown in FIG.

In some embodiments, the shallow trench isolation structure 226 can be wider than the second transgranular One of the widths of the circular interconnects 222. For example, in FIG. 22, the second through-wafer interconnect 222 can be narrower than the shallow trench isolation structure 226 in a lateral cross-section and thus can form the first through-wafer interconnect 216 and shallow trench isolation without overlapping. The semiconductor 210 remaining after the structure 226. In other embodiments, shown in FIG. 23, the second through-wafer interconnect 222 can be narrower than the first through-wafer interconnect 216 in a lateral cross-section. In other words, the cross-sectional area of the second through-wafer interconnect 222 can be smaller than the cross-sectional area of the first through-wafer interconnect 216. Portions of the etch stop 224 remaining after forming the second through wafer interconnect 222 may thus be overlaid on a portion of the first through wafer interconnect 216, as shown in FIG.

In other embodiments, the semiconductor structure can have a different number of material layers. For example, when compared to the substrate 206 of the semiconductor structure 1800 of FIG. 20, the substrate of the semiconductor structure 2400 (shown in FIG. 24) lacks an additional layer 214. However, through-wafer interconnects 216 and 222 can be formed in at least substantially similar manner. The semiconductor structure 2400 without the additional layer 214 may be formed or the additional layer 214 may be completely removed prior to forming the at least one second through wafer interconnect 222. One advantage of having no additional layer 214 is that the etching process can be performed through a single homogeneous material rather than through two or more different layers. Etchants that pass through different materials can have different etch rates. Thus, etching through a homogenous material can be more etched than etching through different materials. As illustrated with reference to FIG. 21, the second through-wafer interconnect 222 can extend laterally beyond one of the lateral perimeters of the shallow trench isolation structure 226, as shown in FIG. In other embodiments, the second through-wafer interconnect 222 may not extend laterally beyond one of the lateral perimeters of the shallow trench isolation structure 226 but may be wider than the first through-wafer interconnect 216, as shown in FIG. . Second through wafer interconnect 222 can also have a smaller cross-sectional area than the first through-wafer interconnect 216, as shown in FIG.

Certain embodiments of the invention may also have at least one thermal management structure 234 formed in the substrate 206. 28 and 29 show semiconductor structures 2800 and 2900 having thermal management structures 234 formed only in substrate 206. The thermal management structures can be formed in a manner similar to forming one of the through-wafer interconnects, as previously discussed herein. For example, a patterned mask layer (not shown) can be applied to substrate 206 to protect areas that are not to be etched. The structure exposed through the patterned mask layer can then be subjected to an etchant. The resulting holes can be filled with a material to form the thermal management structure 234. The material from which the thermal management structure is formed need not be electrically conductive, but it may be electrically conductive. The material can be selected to have the desired heat transfer properties (e.g., properties that cause the overall semiconductor structure to have a desired coefficient of thermal expansion).

Thermal management structures 234 may also be formed across two or more layers, such as across substrate 206 and insulator 212, as shown in semiconductor structures 3000 and 3100 of FIGS. 30 and 31. Regardless of placement, the thermal management structure 234 can include at least one dummy metal pad that is electrically isolated from the device structure 208. Electrical isolation may be a result of one of the physical barriers between the thermal management structure 234 and the device structure 208 or the low conductivity of the material of the thermal management structure 234.

Thermal management structure 234 can improve thermal management of the system by balancing vertical thermal resistance with lateral thermal diffusion. The thermal expansion coefficient can be tailored to a desired value by varying the size, number, composition, placement, shape or depth of the thermal management structure 234. The desired coefficient of thermal expansion can be selected to match another semiconductor junction to which the semiconductor structures 2800, 2900, 3000, and 3100 can be later bonded. The coefficient of thermal expansion of the structure. Thermal management structure 234 may be formed from one or more metals (such as copper, tungsten, aluminum, tin, silver) or based on one or more alloys of one or more of these metals or any other material that is relatively more thermally conductive than substrate 206. The change in size, number, composition, placement, shape, or depth of the first through-wafer interconnect 216 and the second through-wafer interconnect 222 may be used in conjunction with or in combination with the changes to the thermal management structure 234 to achieve A desired coefficient of thermal expansion.

In some embodiments, one or more conductive interconnect layers 236 can be formed over the substrate 206 to change the position of the electrical contacts. For example, in FIGS. 32 and 33, semiconductor structures 3200 and 3300 each have a plurality of conductive interconnect layers 236 on top of substrate 206 of semiconductor structures 1500 and 1400, respectively. One conductive interconnect layer 236 can have a conductive material in contact with the second through wafer interconnect 222. Each of the conductive interconnect layers 236 can have a conductive material in contact with another conductive interconnect layer 236. Conductive interconnect layer 236 can collectively provide electrical connections between various points on the surface of semiconductor structure 200 to device structure 208.

Conductive interconnect layer 236 can be formed by any method known in the art. For example, one or more additional dielectric layers can be deposited on substrate 206. A patterned mask layer can be applied to the additional dielectric layers to protect areas that are not to be etched. The additional dielectric layer can then be subjected to a selective etchant by using a wet chemical etch process, a dry reactive ion etch process, or any other etch process known in the art through the patterned mask layer. . The formed holes or voids (generally referred to as vias) may then be filled with one or more electrically conductive materials to form a conductive interconnect layer 236.

Conductive metal interconnect layer 236 can be used to reroute electrical contacts to With other semiconductor structure contacts. The use of a conductive interconnect layer avoids the need to use a separate insert. Avoiding the use of a separate insert can reduce production and maintenance costs by limiting the number of different components required and by limiting thermal mismatch issues. The conductive interconnect layer 236 can have a coefficient of thermal expansion that is tailored to match the thermal expansion coefficients of the semiconductor structures 1500 and 1400 or other semiconductor structures to which the semiconductor structures 3200 and 3300 can be attached.

The various methods set forth above can be combined in a single semiconductor structure. For example, FIG. 34 shows a through wafer interconnect 316 having a through wafer interconnect 316 formed through an active surface (as shown in FIG. 8) and being formed hierarchically across both the active and back surfaces. One of the semiconductor structures 3400 is combined (as shown in FIG. 32). Any of the through wafer interconnects 316 can be coupled to the device structure 308 in place of the separate interposer and can contribute to the desired coefficient of thermal expansion of one of the semiconductor structures 3400.

As explained with reference to previous embodiments, semiconductor structure 3400 can have a back surface 304 and can include at least one device structure 308 formed in and/or over a substrate 306. At least one through wafer interconnect 316 can be formed through the back surface 304 in connection with the device structure 308. The semiconductor structure 3400 can include a semiconductor 310 and an insulator 312. In addition, through-wafer interconnects 316 can be formed through semiconductor 310 and insulator 312. One or more conductive interconnect layers 336 can be formed on substrate 306 and can be connected to through-wafer interconnect 316. There may be at least one thermal management structure 324 formed within the semiconductor structure 3400 to help achieve a desired coefficient of thermal expansion.

In still another embodiment shown in FIG. 35, semiconductor structure 3400 can be placed in electrical contact with another substrate 320, such as a circuit board. Semiconductor structure The 3400 can have conductive bumps 344 that connect the semiconductor structure 3400 to the substrate 320. Conductive bumps 344 can be formed by any method known in the art, such as by depositing one or more metals. An additional semiconductor structure 346 can be placed on one side opposite the substrate 320 in electrical contact with the semiconductor structure 3400. There may be metal bond points 348 that connect the semiconductor structure 300 to the additional semiconductor structure 346. These metal bond points 348 can be formed by depositing conductive bumps or balls and reflowing them, as previously described herein. In such a manner, the bonding process can be carried out at a temperature of about 400 ° C or less or even about 350 ° C or less than 350 ° C or a number of temperatures to avoid thermal damage to the device structure. In additional embodiments, a direct metal to metal bonding process can be used without the use of any intermediate binders or other bonding materials to form the metal bond points. For example, the direct bonding process can include any of a thermal compression direct bonding process, an ultra-low temperature direct bonding process, and a surface assisted direct bonding process, as previously defined herein.

In some embodiments, the semiconductor structure can be formed to have a thicker layer than desired in the final product. This can be done to avoid problems associated with handling very thin wafers. Later, the semiconductor structures can be thinned after forming through-wafer interconnects and other features. For example, embodiments of the present invention may utilize semiconductor structure 1100 (FIG. 11). The thickness of the semiconductor structure 1100, and in particular the substrate 206, can be formed to have a thicker layer than is desired in the final product. For example, the insulator layer 212 can have a thickness of at least about 100 μm, at least about 300 μm, or even at least about 500 μm. By increasing the layer thickness of the insulator 212, the problem of handling very thin semiconductor structures can be avoided And better control of aspect ratio etching may be possible.

The invention also includes forming an active surface 402 on a first side of the semiconductor structure 3600 and a back surface 404 on a second opposite side of the semiconductor structure 3600 and including on and/or over a substrate 406 One of the at least one device structure 408 is a semiconductor structure 3600 (as shown in FIG. 36). Substrate 406 can include a structure similar to that of substrate 206 (FIG. 11), that is, including semiconductor 410, an insulator 412, and one or more additional layers 414 (such as an additional layer of semiconductor material). In some embodiments, substrate 406 can also include one or more additional insulator layers 415 and one or more additional semiconductor layers 416. Layers 410, 414, and 416 can include one or more semiconductor materials such as germanium (Si), germanium (Ge), a III-V semiconductor material, and the like. Additionally, substrate 406 can comprise a semiconductor material single crystal or a semiconductor material epitaxial layer. Insulator layers 412 and 415 may include one or more layers of dielectric material such as an oxide (for example, cerium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), a nitride (for example, nitrogen) Plutonium (Si ₃ N ₄ ) or boron nitride (BN)).

As previously explained with reference to FIG. 5, the semiconductor structure 3600 (the semiconductor layer 410, the insulating layer that passes through the substrate 406 from the active surface 402) may be passed through the semiconductor structure 3600 by etching as described above or by any other method known in the art. 412 and one or more additional layers 414) form at least one through wafer interconnect 416. The through wafer interconnect 416 can be coupled to the device structure 408. By adding a semiconductor and insulator layer, the problem of handling very thin semiconductor structures can be avoided and better control of aspect ratio etching can be possible. For example, the one or more semiconductor layers may preferably be etched over one or more of the insulator layers by a selective etching process and a chemical process. In other words, one or more insulations can be utilized The bulk layer acts as an etch stop to help form the through wafer interconnect 416.

The through wafer interconnect 416 can be formed through the plurality of semiconductor layers 410 and 414 and through the insulator layer 412, as shown in FIG. In another embodiment, the through wafer interconnect 416 can be formed through a single semiconductor layer 410 to stop at an insulator 412, as shown in the semiconductor structure 3700 of FIG. The active surface 402 of the semiconductor structure 3700 can be bonded to a carrier substrate 422, as illustrated in FIG. The material can be thinned from the semiconductor structure 3700 using a chemical mechanical polishing process or any other method known in the art. In some embodiments, a complete semiconductor layer 416 and a complete insulator 415 can be removed, as shown in semiconductor structure 3800 in FIG. Thinning the semiconductor structure 400 maintains the through-wafer interconnect 416 exposed, as shown by the semiconductor structure 3900 in FIG. In such embodiments, other semiconductor structures (not shown) may be electrically connected to the exposed through wafer interconnect 420.

In the methods set forth herein above, each of the various manufacturing processes may be performed at a temperature of about 400 ° C or less, or even about 350 ° C or less than 350 ° C or at several temperatures. To avoid thermal damage to previously fabricated device structures in the semiconductor structure being processed. In other words, in the methods set forth herein above, it may be carried out as part of various manufacturing processes without exposing the semiconductor structure to temperatures above about 400 ° C or even above about 350 ° C. Each avoids causing thermal damage to previously fabricated device structures in the semiconductor structure being processed.

100‧‧‧First semiconductor structure

102‧‧‧Action surface

102'‧‧‧ action surface

104‧‧‧Back surface

105‧‧‧ Surface

106‧‧‧Substrate

106'‧‧‧Substrate

108‧‧‧Device structure

108'‧‧‧ device structure

110‧‧‧ bonding layer

111‧‧‧Semiconductor material layer

112‧‧‧Second semiconductor structure/semiconductor structure/second semiconductor

112'‧‧‧Second semiconductor structure/fourth semiconductor structure

113‧‧‧ Section

114‧‧‧Bound surface

115‧‧‧Selected sacrificial substrate/sacrificial substrate

116‧‧‧through wafer interconnects

116'‧‧‧through wafer interconnects

117‧‧‧Ion implantation plane

118‧‧‧bonding layer

119‧‧‧ combination interface

120‧‧‧ Third semiconductor structure / third semiconductor

122‧‧‧Substrate

123‧‧‧ Conductive bumps

124‧‧‧ Thermal management structure

200‧‧‧Semiconductor structure

202‧‧‧Action surface

204‧‧‧Back surface

206‧‧‧Substrate

208‧‧‧ device structure

208'‧‧‧Optoelectronic / device structure

210‧‧‧Semiconductor

212‧‧‧Insulator/Insulator Layer

214‧‧‧Additional layer

216‧‧‧First through wafer interconnect/through wafer interconnect

217‧‧‧ additional layers

218‧‧‧ bonding surface

220‧‧‧ Carrier substrate

222‧‧‧Second-through wafer interconnect/through-wafer interconnects

224‧‧‧ etching stop

226‧‧‧Shallow trench isolation structure

230‧‧‧ source area

231‧‧‧ gate electrode

232‧‧‧Bungee area

234‧‧‧ Thermal management structure

236‧‧‧Transitive interconnect layer/conductive metal interconnect layer

300‧‧‧Semiconductor structure

304‧‧‧Back surface

306‧‧‧Substrate

308‧‧‧Device structure

310‧‧‧Semiconductor

312‧‧‧Insulator

316'‧‧‧through wafer interconnects

316‧‧‧through wafer interconnects

320‧‧‧Substrate/Board

324‧‧‧ Thermal management structure

336‧‧‧Transitive interconnect layer

344‧‧‧ Conductive bumps

346‧‧‧Additional semiconductor structure

348‧‧‧Metal joints

400‧‧‧Intermediate structure; semiconductor structure

402‧‧‧Action surface

404‧‧‧Back surface

406‧‧‧Substrate

408‧‧‧ device structure

410‧‧‧Semiconductor layer/semiconductor/layer

412‧‧‧Insulator/Insulator/Insulation

414‧‧‧Additional layer/extra semiconductor material layer/layer/semiconductor layer

415‧‧‧Additional insulator/insulator/insulator

416‧‧‧Additional semiconductor layer/through wafer interconnect/semiconductor layer/layer

422‧‧‧ Carrier substrate

500‧‧‧Semiconductor structure

600‧‧‧Semiconductor structure

800‧‧‧Semiconductor structure

900‧‧‧Semiconductor structure

1000‧‧‧Semiconductor structure

1100‧‧‧Semiconductor structure

1200‧‧‧ semiconductor structure

1300‧‧‧Semiconductor structure

1400‧‧‧Semiconductor structure

1500‧‧‧Semiconductor structure

1600‧‧‧Semiconductor structure

1700‧‧‧Semiconductor structure

1800‧‧‧Semiconductor structure

1900‧‧‧ semiconductor structure

2400‧‧‧Semiconductor structure

2800‧‧‧Semiconductor structure

2900‧‧‧Semiconductor structure

3000‧‧‧Semiconductor structure

3100‧‧‧Semiconductor structure

3200‧‧‧Semiconductor structure

3300‧‧‧Semiconductor structure

3400‧‧‧Semiconductor structure

3600‧‧‧Semiconductor structure

3700‧‧‧Semiconductor structure

3800‧‧‧Semiconductor structure

3900‧‧‧Semiconductor structure

1 through 10 are simplified schematic cross-sectional views of a semiconductor structure and illustrate an exemplary embodiment of the present invention and a combined semiconductor structure for forming a bonded semiconductor structure; FIGS. 11 through 33 A simplified schematic cross-sectional view of a semiconductor structure and illustrating additional exemplary embodiments of the present invention for forming additional exemplary embodiments of the present invention and a bonded semiconductor structure including a bonded semiconductor substrate; FIG. 34 and 35 is a simplified schematic cross-sectional view of a semiconductor structure and illustrates an exemplary embodiment of the present invention for combining the methods of the previous figures to form a bonded semiconductor structure; and FIGS. 36-39 are simplified schematic cross-sectional views of the semiconductor structure and Other example embodiments of the invention for forming a bonded semiconductor structure are illustrated.

104‧‧‧Back surface

106‧‧‧Substrate

108‧‧‧Device structure

110‧‧‧ bonding layer

112‧‧‧Second semiconductor structure/second semiconductor/semiconductor structure

112'‧‧‧Second semiconductor structure/fourth semiconductor structure

114‧‧‧Bound surface

116‧‧‧through wafer interconnects

119‧‧‧ combination interface

120‧‧‧ Third semiconductor structure / third semiconductor

124‧‧‧ Thermal management structure

400‧‧‧Intermediate structure/semiconductor structure

500‧‧‧Semiconductor structure

1000‧‧‧Semiconductor structure

Claims (17)

A method of forming a bonded semiconductor structure, comprising: providing a first bonded semiconductor structure comprising: providing a first processed semiconductor structure comprising at least one device structure; using a direct bonding process at less than 400 ° C a first thin material layer having an average thickness of one micron or less than one micron; and passing through a surface of one of the first processed semiconductor structures at a temperature or a plurality of temperatures; Forming the first thin material layer into the first processed semiconductor structure to the at least one device structure to form at least one first through-wafer interconnect; providing a second bonded semiconductor structure comprising: providing at least a second processed semiconductor structure of a device structure; bonding a second thin material layer over one of the active surfaces of the second processed semiconductor structure using a direct bonding process at a temperature of less than 400 ° C or a plurality of temperatures The second thin material layer has an average thickness of 1 micron or less; and passes through the second thin material layer and enters the second meridian Forming at least one second through-wafer interconnect in the semiconductor structure; after providing the first bonded semiconductor structure and the second bonded semiconductor structure, using a direct metal-to-metal bonding process to the at least one second a through-wafer interconnect bonded to the at least one first through-wafer interconnect Attaching the first bonded semiconductor structure to the second bonded semiconductor structure; wherein the first thin material layer and the second thin material layer define the first bonded semiconductor structure and the second An insert between the bonded semiconductor structures. The method of claim 1, wherein bonding the first thin material layer over the active surface of the first processed semiconductor structure comprises: bonding a relatively thick semiconductor structure to the first processed semiconductor structure; A relatively thick semiconductor structure is thinned to form the first thin material layer, the first thin material layer including a relatively thin portion of the relatively thick semiconductor structure that remains bonded to the first processed semiconductor structure. The method of claim 2, wherein thinning the relatively thick semiconductor structure to form the first thin material layer comprises: implanting ions into the relatively thick semiconductor structure along an ion implantation plane; and causing the relative The thicker semiconductor structure breaks along the ion implantation plane. The method of claim 3, wherein implanting ions into the relatively thick semiconductor structure comprises implanting ions into the relatively thick semiconductor structure prior to bonding the relatively thick semiconductor structure to the first processed semiconductor structure in. The method of claim 3, wherein the breaking the relatively thick semiconductor structure along the ion implantation plane comprises after the relatively thick semiconductor structure is bonded to the first processed semiconductor structure, the relatively thicker semiconducting The bulk structure breaks along the ion implantation plane. The method of claim 5, wherein the breaking the relatively thick semiconductor structure along the ion implantation plane comprises heating the relatively thick semiconductor structure to a temperature of less than 400 ° C or a plurality of temperatures to cause the relatively thicker The semiconductor structure breaks along the ion implantation plane. The method of claim 1, further comprising selecting the first thin material layer to be at least substantially comprised of tantalum. The method of claim 7, further comprising selecting the first thin material layer to consist of a single crystal germanium. The method of claim 1, further comprising passing the first thin material layer and entering the first processed semiconductor structure into the first processed semiconductor structure at a temperature below 1000 ° C or at a temperature to form the at least one device structure A through-wafer interconnect. The method of claim 1, further comprising forming at least one thermal management structure in the first thin material layer. The method of claim 10, wherein forming the at least one thermal management structure comprises forming at least one dummy metal pad electrically isolated from the at least one of the first processed semiconductor structures. The method of claim 10, further comprising trimming a coefficient of thermal expansion of the one of the inserts by changing at least one of a size, a number, a composition, a position, and a shape of the at least one thermal management structure. The method of claim 12, further comprising trimming the coefficient of thermal expansion of the insert such that a ratio of the coefficient of thermal expansion of the insert to one of the coefficients of thermal expansion of the first processed semiconductor structure is between 0.67 and 1.5 between. The method of claim 13, further comprising trimming the coefficient of thermal expansion of the insert such that the ratio is between 0.9 and 1.1. The method of claim 14, further comprising trimming the thermal expansion coefficient of the insert to at least substantially equal to a coefficient of thermal expansion of the first processed semiconductor structure. The method of claim 1, further comprising bonding the first bonded semiconductor structure to the second bonded semiconductor structure at a temperature of less than 400 ° C or a plurality of temperatures. The method of claim 1, further comprising: forming at least one third through-wafer interconnect in the first processed semiconductor structure, the at least one third through-wafer interconnect being connected to the first processed The at least one device structure of the semiconductor structure; the conductive interconnect structure formed on one side of the second processed semiconductor structure, the conductive interconnect structure including at least the first processed semiconductor structure A conductive material such that the at least one conductive material of the conductive interconnect structure is in contact with the at least one third through-wafer interconnect of the first processed semiconductor structure.