CN111128695A - Preparation method of on-chip single crystal semiconductor material - Google Patents
Preparation method of on-chip single crystal semiconductor material Download PDFInfo
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- CN111128695A CN111128695A CN201911278684.0A CN201911278684A CN111128695A CN 111128695 A CN111128695 A CN 111128695A CN 201911278684 A CN201911278684 A CN 201911278684A CN 111128695 A CN111128695 A CN 111128695A
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- 239000000463 material Substances 0.000 title claims abstract description 130
- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 239000013078 crystal Substances 0.000 title claims abstract description 79
- 238000002360 preparation method Methods 0.000 title abstract description 37
- 238000002513 implantation Methods 0.000 claims abstract description 44
- 238000000137 annealing Methods 0.000 claims abstract description 23
- 238000002347 injection Methods 0.000 claims abstract description 20
- 239000007924 injection Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 50
- 230000008569 process Effects 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000000678 plasma activation Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 4
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims 1
- 238000012545 processing Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 25
- 238000005530 etching Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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Abstract
The invention discloses a preparation method of an on-chip single crystal semiconductor material, which comprises the following steps: providing a monocrystalline semiconductor material; wherein the single crystal semiconductor material has a doped implantation surface; carrying out doping injection treatment on the monocrystalline semiconductor material on the doping injection surface so as to form a doping layer at a preset depth of the monocrystalline semiconductor material; annealing the formed structure; providing a chip; wherein the chip has a bonding interconnection face; carrying out low-temperature bonding treatment on the doping injection surface of the single crystal semiconductor material and the bonding interconnection surface of the chip; and thinning the other surface of the single crystal semiconductor material opposite to the doping injection surface until the doping layer is removed. The preparation method adopts the monocrystalline semiconductor material with the doped layer therein to realize the preparation of the on-chip material, thereby reducing the preparation cost and difficulty, and when the monocrystalline semiconductor material and the chip are processed relatively, the high-temperature processing technology is not needed, and the chip is not influenced.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a preparation method of an on-chip single crystal semiconductor material.
Background
With the continuous development of the CMOS integrated circuit scale, the micro system integration based on the CMOS integrated circuit is also developed from three-dimensional packaging, system-in-package, and multi-chip three-dimensional system integration toward single-chip three-dimensional integration, so as to continuously reduce the micro system size, circuit delay, and circuit power consumption, and greatly improve the system performance.
The existing preparation methods of on-chip materials for realizing monolithic 3D-IC (Three-dimensional integrated circuit) integration include the following methods:
1. the preparation of the on-chip material is realized by low-temperature bonding of the chip and the high-mobility germanium-based material such as SOI or GOI; the material prepared by the method has good quality and higher mobility, but the preparation process has high cost and great preparation control difficulty.
2. The preparation of the on-chip material is realized by depositing materials such as polysilicon and the like on the chip at low temperature; although the method is low in cost, the prepared material is polycrystalline, has a plurality of defects and low mobility, so that the finally prepared three-dimensional integrated circuit is poor in performance.
3. Selectively opening holes on the surface of the chip, and then realizing the preparation of the on-chip material on the formed structure by low-temperature selective lateral epitaxy; the on-chip material formed in the mode has more defects and grain boundaries, and the influence on the chip circuit at the bottom layer is larger due to higher process temperature in the preparation process, so that the finally prepared three-dimensional integrated circuit has poorer performance.
The continuous development of CMOS integrated circuits puts higher and higher requirements on the preparation of on-chip materials, and therefore, how to realize the preparation of on-chip materials with high quality and low cost is a problem to be solved urgently.
Disclosure of Invention
The invention provides a preparation method of an on-chip single crystal semiconductor material, aiming at overcoming the technical problems that the cost of the existing preparation method of the on-chip material is high, or the prepared on-chip material has a plurality of defects, low mobility, polycrystalline state and the like.
The preparation method of the on-chip single crystal semiconductor material comprises the following steps:
providing a monocrystalline semiconductor material; wherein the single crystal semiconductor material has a doped implantation surface;
carrying out doping injection treatment on the monocrystalline semiconductor material on the doping injection surface so as to form a doping layer at a preset depth of the monocrystalline semiconductor material;
annealing the formed structure;
providing a chip; wherein the chip has a bonding interconnection face;
carrying out low-temperature bonding treatment on the doping injection surface of the single crystal semiconductor material and the bonding interconnection surface of the chip;
and thinning the other surface of the single crystal semiconductor material opposite to the doping injection surface until the doping layer is removed.
Preferably, the monocrystalline semiconductor material is a bulk silicon wafer material.
Preferably, the implantation element of the doping implantation treatment is any one of P, As, B or In.
Preferably, the implantation dose of the doping implantation process is 1e14cm-2To 1e16cm-2。
Preferably, the predetermined depth is 10nm to 5000 nm.
Preferably, the annealing temperature of the annealing treatment is 800 ℃ or higher.
Preferably, the annealing time of the annealing treatment is 1s or more.
Preferably, after the chip is provided and before the low temperature bonding process is performed; and carrying out plasma activation treatment on the doping injection surface and the bonding interconnection surface.
Preferably, in subjecting the dopant implantation surface to a low temperature bonding process with the bonding interconnect surface, a mechanical pressing process is performed on the other surface of the single crystal semiconductor material opposite the dopant implantation surface.
Preferably, a silicon-silicon direct bonding process is adopted to carry out low-temperature bonding treatment on the doping injection surface and the bonding interconnection surface;
and thinning the other surface of the single crystal semiconductor material by adopting a wet etching process.
In summary, in the method for preparing a single crystal semiconductor material on a chip according to the present invention, before bonding interconnection, a doping implantation process is performed on a single crystal semiconductor material subsequently bonded to a chip at a doping implantation surface, and a doping layer is formed at a predetermined depth of the single crystal semiconductor material; and sequentially carrying out annealing treatment and low-temperature bonding treatment, and then taking the doped layer as a corrosion barrier layer when thinning the other surface of the single crystal semiconductor material, so that the single crystal semiconductor material meeting the thickness requirement is reserved on the chip, and the preparation of the material on the high-quality chip is realized.
Compared with the prior art, the preparation of the on-chip material is realized by adopting the single crystal semiconductor material, the preparation cost of the process is reduced compared with the preparation by adopting SOI or GOI, meanwhile, the preparation thickness of the on-chip material is accurate and higher by using the doped layer as an etching stop layer for thinning treatment, and the high-temperature treatment process is not needed when the single crystal semiconductor material and the chip are subjected to related treatment after the single crystal semiconductor material is annealed, so that the chip is not influenced; the problems of polycrystalline state, low mobility and the like of the materials prepared on the chip can not be caused.
Drawings
FIG. 1 is a flow chart of a method for fabricating single-crystal semiconductor material on a wafer according to the present invention;
FIGS. 2 to 7 are structural views corresponding to each step of a method for manufacturing a single crystalline semiconductor material on a wafer according to the present invention;
wherein, 1 is a single crystal semiconductor material, 11 is a doping injection surface, 12 is a doping layer, 2 is a chip, and 21 is a bonding interconnection surface.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
In order to overcome the technical problems of high cost of the existing preparation method of the on-chip material, or more defects, low mobility, polycrystalline state and the like of the prepared on-chip material, the invention provides a preparation method of on-chip single crystal material transfer; specifically, the preparation of the material on the chip is realized by adopting the monocrystalline semiconductor material with the doped layer, the doped layer is used as a corrosion barrier layer when thinning treatment is carried out, an SOI (silicon on insulator) substrate or a GOI (germanium on insulator) substrate with high cost is not required to be adopted, the preparation cost and the preparation difficulty of the process are reduced, and a high-temperature treatment process is not required to be adopted when the monocrystalline semiconductor material and the chip are subjected to related treatment, so that the chip is not influenced.
The preparation method of the on-chip single crystal semiconductor material disclosed by the invention comprises the following steps as shown in figure 1:
s1, as shown in fig. 2, providing a single crystal semiconductor material 1; wherein the monocrystalline semiconductor material 1 has a doped implantation surface 11;
in the step, a single crystal semiconductor material 1 which needs to be bonded and interconnected with a chip 2 is provided; wherein, the monocrystalline semiconductor material 1 is a bulk silicon wafer material; alternatively, any of the existing single crystal semiconductor materials 1 satisfying the operation requirements; the doping implantation surface 11 is a surface on the single crystal semiconductor material 1, and specifically, the doping implantation surface 11 is a surface on which a doping implantation process is subsequently performed on the single crystal semiconductor material 1.
By adopting the technical scheme, compared with the adoption of materials with good quality such as SOI or GOI, the cost of the single crystal semiconductor material 1 is lower, and meanwhile, the single crystal semiconductor material 1 also has the advantage of higher mobility, so that the preparation quality of the materials on the chip can be ensured.
S2, as shown in fig. 3, performing doping implantation treatment on the single crystal semiconductor material 1 at the doping implantation surface 11 to form a doping layer 12 at a predetermined depth of the single crystal semiconductor material 1;
in the step, before bonding interconnection is carried out on the chip 2 and the single crystal semiconductor material 1, doping implantation treatment needs to be carried out on the single crystal semiconductor material 1 on a doping implantation surface 11; the doped layer 12 is formed at the preset depth of the single crystal semiconductor material 1, and the doped layer 12 can be used as an etching stop layer in the subsequent thinning treatment process, so that on-chip materials meeting the thickness requirement can be reserved on the chip 2 after the thinning treatment, and the control difficulty is reduced.
Specifically, the implantation element of the doping implantation treatment is any one of P, As, B, or In; the implantation dose is 1e14cm-2To 1e16cm-2(ii) a The preset depth is 10nm to 5000 nm; the selection of the implantation elements, the implantation dose and the preset depth may be set according to actual conditions, and is not specifically limited herein.
S3, annealing the formed structure;
in this step, when the single crystal semiconductor material 1 is subjected to doping implantation treatment, some lattice atoms are displaced by high-energy incident ions, resulting in a large number of vacancies; therefore, the annealing process is required to be performed on the single crystal semiconductor material 1 after the doping implantation process to restore the crystal structure and eliminate defects, thereby improving the manufacturing quality.
Wherein the annealing temperature of the annealing treatment is more than or equal to 800 ℃; the annealing time of the annealing treatment is more than or equal to 1 s; the specific annealing temperature value and the annealing time are set according to actual conditions, and are not particularly limited herein.
S4, as shown in fig. 4, providing a chip 2; wherein the chip 2 has a bonding interconnect face 21;
in this step, the chip 2 is any one of the chips which need to be three-dimensionally integrated; the bonding interconnection face 21 is a surface on the chip 2, and specifically, the bonding interconnection face 21 is a face of the chip 2 which is subjected to a subsequent face-to-face low-temperature bonding process with the doping implantation face 11.
As an example, the chip 2 may be a two-dimensional chip to be integrated.
S5, carrying out low-temperature bonding treatment on the doping injection surface 11 of the single crystal semiconductor material 1 and the bonding interconnection surface 21 of the chip 2;
in the step, the single crystal semiconductor material 1 is inverted on the bonding interconnection surface 21 of the chip 2 through the doping injection surface 11, namely, the doping injection surface 11 is in surface-to-surface contact with the bonding interconnection surface 21; and bonding and interconnecting the doping injection surface 11 and the bonding and interconnecting surface 21 by adopting a low-temperature bonding process so as to tightly connect the single-crystal semiconductor material 1 and the chip 2 together.
Specifically, if the single crystal semiconductor material 1 is a bulk silicon wafer material, a silicon-silicon direct bonding process may be adopted to perform low-temperature bonding processing on the doped implantation surface 11 and the bonding interconnection surface 21; of course, any existing bonding process that meets the operational requirements may be used.
The method comprises the following specific steps of carrying out low-temperature bonding treatment on the doped injection surface 11 and the bonding interconnection surface 21 by adopting a silicon-silicon direct bonding process:
s51, after the bonding interconnection surface 21 of the chip 2 is sequentially subjected to planarization treatment and cleaning treatment, a layer of single-layer water molecules is reserved on the bonding interconnection surface 21;
in the step, before the low-temperature bonding treatment, in order to ensure the subsequent bonding quality, the bonding interconnection surface 21 of the chip 2 is subjected to planarization treatment, so that the bonding interconnection surface 21 is globally or locally highly flat; after the planarization treatment, the bonding interconnection face 21 is subjected to a cleaning treatment to remove impurity particles remaining thereon after the planarization treatment.
Further, before the low-temperature bonding treatment is carried out; the doping implantation surface 11 and the bonding interconnection surface 21 can be subjected to plasma activation treatment; that is, after step S4 and before step S5, the doping implantation surface 11 and the bonding interconnection surface 21 of the bonding interconnection are subjected to plasma activation treatment to further remove impurity particles on both surfaces and improve the bonding effect.
S52, oxidizing the doped injection surface 11 of the single crystal semiconductor material 1;
s53, as shown in fig. 5, inverting the single crystal semiconductor material 1 on the bonding interconnection face 21 of the chip 2 through the doping implantation face 11;
s54, as shown in fig. 6, performing a low temperature bonding process on the doped implantation surface 11 of the single crystal semiconductor material 1 and the bonding interconnection surface 21 of the chip 2;
in this step, the temperature range of the low-temperature bonding treatment is 500 ℃ or less.
And S55, carrying out low-temperature annealing treatment on the formed structure to realize bonding interconnection of the single-crystal semiconductor material 1 and the chip 2.
Further, in the low-temperature bonding process of the impurity implantation surface 11 and the bonding interconnection surface 21, that is, in step S5, a mechanical pressing process is performed on the other surface of the single crystal semiconductor material 1 opposite to the impurity implantation surface 11 to further improve the bonding effect; wherein, the pressure intensity range of the mechanical pressing is as follows: 0 to 10kg/cm2。
S6, as shown in fig. 7, the other surface of the single crystal semiconductor material 1 facing the doped implantation surface 11 is thinned until the doped layer is removed.
In this step, after the single crystal semiconductor material 1 and the chip 2 are bonded and interconnected, the back surface of the single crystal semiconductor material 1 needs to be thinned, so that the thickness of the single crystal semiconductor material 1 finally remaining on the chip 2 meets the requirements of actual conditions.
Specifically, a wet etching process may be used to thin the other surface of the single crystal semiconductor material 1, and during the etching process on the back surface of the single crystal semiconductor material 1, the doped layer 12 may serve as an etching barrier, i.e., the etching until the doped layer 12 stops etching the underlying single crystal semiconductor material 1, which is convenient for control.
For example, if the single crystal semiconductor material 1 is a bulk silicon wafer material, the back surface of the single crystal semiconductor material 1 may be thinned by using TMAH solution.
In summary, in the method for preparing the single crystal semiconductor material 1 on the chip according to the present invention, before the bonding interconnection, the doping implantation process is performed on the doping implantation surface 11 on the single crystal semiconductor material 1 which is subsequently bonded to the chip 2, and the doping layer 12 is formed at the predetermined depth of the single crystal semiconductor material 1; annealing treatment and low-temperature bonding treatment are sequentially carried out, and the doped layer 12 can be used as a corrosion barrier layer when the other surface of the single crystal semiconductor material 1 is thinned, so that the semiconductor material meeting the thickness requirement is reserved on the chip 2, and the preparation of the high-quality on-chip material is realized.
Compared with the prior art, the preparation of the on-chip material is realized by adopting the single crystal semiconductor material 1, the preparation cost of the process is reduced compared with the preparation by adopting SOI or GOI, meanwhile, the preparation thickness of the on-chip material can be more accurate by taking the doped layer 12 as an etching stop layer for thinning treatment, and after the annealing treatment is carried out on the single crystal semiconductor material 1, the high-temperature treatment process is not needed when the single crystal semiconductor material 1 and the chip 2 are subjected to related treatment, and the influence on the chip 2 is avoided; the problems of polycrystalline state, low mobility and the like of the materials prepared on the chip can not be caused.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for preparing a single crystal semiconductor material on a chip, comprising the steps of:
providing a monocrystalline semiconductor material; wherein the single crystal semiconductor material has a doped implanted face;
performing doping implantation treatment on the single crystal semiconductor material on the doping implantation surface to form a doping layer at a preset depth of the single crystal semiconductor material;
annealing the formed structure;
providing a chip; wherein the chip has a bonding interconnect face;
carrying out low-temperature bonding treatment on the doping injection surface of the single crystal semiconductor material and the bonding interconnection surface of the chip;
and thinning the other surface of the single crystal semiconductor material opposite to the doping injection surface until the doping layer is removed.
2. The method of fabricating an on-chip monocrystalline semiconductor material as recited in claim 1, wherein the monocrystalline semiconductor material is a bulk silicon wafer material.
3. The method for preparing an on-chip single crystal semiconductor material As claimed In claim 1, wherein an implantation element of the doping implantation treatment is any one of P, As, B or In.
4. The method of claim 1, wherein the dopant implantation process is performed at an implant dose of 1e14cm-2To 1e16cm-2。
5. The method of fabricating an on-chip monocrystalline semiconductor material as recited in claim 1, wherein the predetermined depth is 10nm to 5000 nm.
6. The method for producing an on-chip single crystal semiconductor material as claimed in claim 1, wherein an annealing temperature of the annealing treatment is 800 ℃ or higher.
7. The method for producing an on-chip single crystal semiconductor material as claimed in claim 1, wherein an annealing time of the annealing treatment is 1s or more.
8. The method of claim 1, wherein after providing the die and before performing the low temperature bonding process; and carrying out plasma activation treatment on the doping injection surface and the bonding interconnection surface.
9. A method of producing a single crystal semiconductor material on a chip as claimed in claim 1, wherein in the low temperature bonding process of the dopant implantation surface and the bonding interconnection surface, a mechanical pressing process is performed on the other surface of the single crystal semiconductor material opposite to the dopant implantation surface.
10. The method for preparing a single crystal semiconductor material on a chip as claimed in claim 1, wherein the low temperature bonding process is performed on the doped implantation surface and the bonding interconnection surface by using a silicon-silicon direct bonding process;
and thinning the other surface of the single crystal semiconductor material by adopting a wet etching process.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032084A1 (en) * | 2005-08-08 | 2007-02-08 | Silicon Genesis Corporation | Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process |
| CN102738025A (en) * | 2011-03-31 | 2012-10-17 | Soitec公司 | Method of forming bonded semiconductor structure, and semiconductor structure formed by such method |
| CN103077885A (en) * | 2013-01-31 | 2013-05-01 | 上海新傲科技股份有限公司 | Controlled thinning method and semiconductor substrate |
| CN107636810A (en) * | 2015-05-08 | 2018-01-26 | 高通股份有限公司 | The making based on etch stop region of bonding semiconductor structure |
-
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- 2019-12-13 CN CN201911278684.0A patent/CN111128695A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032084A1 (en) * | 2005-08-08 | 2007-02-08 | Silicon Genesis Corporation | Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process |
| CN102738025A (en) * | 2011-03-31 | 2012-10-17 | Soitec公司 | Method of forming bonded semiconductor structure, and semiconductor structure formed by such method |
| CN103077885A (en) * | 2013-01-31 | 2013-05-01 | 上海新傲科技股份有限公司 | Controlled thinning method and semiconductor substrate |
| CN107636810A (en) * | 2015-05-08 | 2018-01-26 | 高通股份有限公司 | The making based on etch stop region of bonding semiconductor structure |
Non-Patent Citations (1)
| Title |
|---|
| 施敏，李明逵: "《半导体器件物理与工艺 第3版》", 30 April 2014 * |
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Inventor after: Yin Huaxiang Inventor after: Lin Xiang Inventor after: Luo Yanna Inventor after: Liu Zhanfeng Inventor before: Yin Huaxiang Inventor before: Lin Xiang Inventor before: Luo Yanna Inventor before: Liu Zhanfeng |
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Application publication date: 20200508 |