TWI417719B - Method, apparatus and computer program product providing instruction monitoring for reduction of energy usage and energy reduction when storing data in a memory - Google Patents

Description

Method, apparatus and computer program product for providing instructions for monitoring reduction in energy use and energy reduction when storing data in memory

Exemplary embodiments of the present invention are generally directed to data storage and retrieval, and more particularly to high energy efficiency techniques for storing data in a computer readable medium.

A write operation of an MRAM is disclosed in U.S. Patent Publication No. 2004/0042292 to Al.S.A., the disclosure of which is incorporated herein by reference. The write operation includes comparing the input data with the read data read from a memory cell array and encoding the input data using a data encoder to form the write data. It is also disclosed to use a data decoder to decode the read data to form an output data. In a non-volatile semiconductor memory, the number of bits to be written during a write operation can be reduced, and the current consumption can also be reduced.

A method and apparatus for reducing the power required to update a dynamic random access memory in a computing system is disclosed in U.S. Patent No. 6,633,951, the entire disclosure of which is incorporated herein by reference. One character to evaluate. For each 8-bit data character, if the number exceeds four, each bit of the data character is inverted, and a data reverse indicator bit is set to a logical one to indicate that the data has been Reverse. This allows the material to be properly stored in the minimum number of data presentations. Due to the power required to update the data stored in the DRAM, the storage The minimum amount of data can reduce power consumption. The reading of the data determines whether the data has been reversed at the time of storage, and if so, the read data is returned to its original format.

A method and system is disclosed in U.S. Patent No. 5,873,112, the entire disclosure of which is incorporated by the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire disclosure An erased cell to a flash memory array, wherein writing a cell having a first value to an erased cell consumes less than writing a bit having a second value to the cell Power. A count signal is generated for the original bit of each packet to indicate the number of bits of the packet having the first (or second) value, the count signal being processed to generate a control signal that determines the packet's The encoding, and the original bits of the packet are encoded according to a scheme determined by the control signal. Each erased cell can indicate a binary value of "1", and the count signal produces a control signal relative to a reference value (representing X/2), which can determine whether the packet must be reversed in polarity, and The packet is inverted (or not inverted) based on the value of the control signal. The count signal can be generated for a bit of each packet to be written to an array of erased cells (where the count signal indicates that the number of bits in the packet has a particular value), and each packet Coding is performed in a manner determined by the corresponding count signal to reduce the power required to write the coded bits to the erased cells. Flag cells indicating the encoding of each packet are generated, and the flag bits (and the encoded packets) are stored in cells of the flash memory array.

Other techniques for controlling memory power consumption are revealed in IBM technology. Abstracts, Volume 30, Issue 1, June 1987, pp. 304-305, "Power Reduction Scheme with Data-Dependent Write"; IBM Technical Abstracts, pp. 11-89, pp. 415-416, "High Performance Memory Reduced Power for High Performance Memory; and in the IEEE paper, Marcello Duhalde et al. (1995), 1057-1060, "A High Performance Modular Embedded ROM Architecture" (A High Performance Modular Embedded) ROM Architecture).

Improvements to these conventional techniques are needed to further reduce the power consumption in currently available and future data storage devices and systems, as well as the resulting thermal load due to power consumption.

In accordance with the exemplary embodiments of the present invention, the foregoing and other problems have been overcome and other advantages are realized.

A first aspect of an exemplary embodiment of the present invention provides a method of operating a memory device. The method includes, prior to overwriting a data of a first unit at a location in the memory device using data of a second unit, determining to write the second unit to the second unit by using at least one unit having the reversed bit Data, whether it is required to write the data of the second unit requires more energy; if it is decided to use less than one unit with the reverse bit to write the data of the second unit, less energy is needed, and at least the reverse bit is utilized. a unit that overwrites the data of the first unit with a data of the modified second unit, and writes at least one bit to indicate that the reverse bit is present A position in the data of the correction unit of the secondary unit.

Another aspect of an exemplary embodiment of the present invention provides an apparatus for operating a memory device including a memory control unit configured to utilize a second unit of data in a memory device Before the location of the data of the first unit is overwritten, it is determined that it is less energy to write the data of the second unit than the data written to the second unit by using at least one unit having the reversed bit; The memory control unit is further configured to respond to the data written to the second unit by using at least one unit having the reversed bit, and the data written to the second unit requires less energy to determine An indicator field for transmitting, by the at least one unit having the reverse bit, a data of the modified second unit, wherein the indicator field includes at least one bit to indicate that the reverse bit is present A position of the data of the correction unit of the data of the sub-unit.

Another aspect of an exemplary embodiment of the present invention provides a computer readable memory medium capable of storing computer program instructions, the operations of which are performed by: utilizing a second unit of data in a memory device Before the information of the first unit is overwritten at the middle position, it is determined that whether the data of the second unit is written into the second unit is more energy than the data written to the second unit by using at least one unit having the reversed bit. If it is decided that the data written to the second unit by at least one unit having the reverse bit requires less energy, then the at least one unit having the reversed bit is used to overwrite the data of the second unit with a correction. The data of the first unit is matched with at least one bit to indicate a position in the data of the correction unit of the secondary unit having the reversed bit.

Yet another aspect of an exemplary embodiment of the present invention provides a method of operating a memory control unit. The method includes: reading current data stored in a memory location; comparing input data to be written with the current data, and calculating a mutual exclusion between execution of the current data and the input data Or (exclusive OR)", and add the number of "1"s in the result of the mutual exclusion, the new data overwrites the number of bit conversions that occurred at the current data, wherein the summation result sum1 represents if the input data The number of bit conversions that will occur when overwriting the current data; comparing sum1 with a predetermined threshold, and if sum1 equals or exceeds the threshold, denying all or part of the input data, performing one with the current data Mutually exclusive, and calculate a second sum2, wherein if the value of sum2+1 of the negative input data is less than sum1, the number of bit conversions will be if the negative input data is written into the memory location Lowering; and in a corresponding indicator field, setting at least one indicator bit to indicate whether the input data is stored, or whether all or a part of the negative version of the input data is stored in the In the memory location.

Another aspect of an exemplary embodiment of the present invention provides a method of operating a power adapter. The method includes reading a first set of instructions; reading a data bus; and reading a register value stored in the at least one data register. This information is analyzed for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

Yet another aspect of an exemplary embodiment of the present invention provides an apparatus coupled to an instruction register, a data bus, and at least one Material register. The device reads the first instruction set; reads the data bus; and reads the value of the register stored in the data register. The device analyzes this information for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

Another aspect of an exemplary embodiment of the present invention provides a computer readable memory medium capable of storing computer program instructions, the operations caused by the operations include: reading a first instruction set; reading a data stream Row; and read the scratchpad value stored in at least one data register. This information is analyzed for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

Yet another aspect of an exemplary embodiment of the present invention provides an apparatus. The device has means for reading a first set of instructions; reading a data bus; and reading a register value stored in the at least one data register. The device analyzes this information for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

Yet another aspect of an exemplary embodiment of the present invention provides a method of operating a power adapter. The method includes reading a first set of instructions; reading a data bus; and reading a register value stored in the at least one data register. This information is analyzed for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

Yet another aspect of an exemplary embodiment of the present invention provides an apparatus coupled to an instruction register, a data bus, and at least one data register. The device reads the first instruction set; reads the data bus; and reads the value of the register stored in the data register. The device analyzes this information for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

In another aspect of an exemplary embodiment of the present invention, a computer readable memory medium is provided, which can store computer program instructions, and the operations caused by the execution include: reading a first instruction set; reading a data Bus; and reads the value of the scratchpad stored in at least one data register. This information is analyzed for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

Another aspect of an exemplary embodiment of the present invention provides an apparatus. The device has means for reading a first set of instructions; reading a data bus; and reading a register value stored in the at least one data register. The device analyzes this information for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set.

The use of an exemplary embodiment of the present invention can reduce the amount of energy required to store information in a memory device.

Techniques utilized by exemplary embodiments of the present invention can reduce the number of digital data conversions (1 to 0 or 0 to 1), thus reducing the amount of energy consumed in storing a data in a memory device. The use of an exemplary embodiment of the present invention is advantageous for a memory device in which the energy to change the state of the memory is the primary energy item. In a first exemplary embodiment, data previously stored in a unit in a memory device is read prior to writing to determine whether a portion of the data of the unit or the portion of the data for the unit Negative versions of the shares can be stored with less conversion and therefore with lower energy. If it determines that a portion of the unit's data can be stored with fewer conversions, that is, storing one or more indicators to specify which part or portions of the unit's data will be in the reversed version To store. The (etc.) indicator can be obtained later when the unit's data is read to restore the unit's data to its original version.

In another exemplary embodiment, a statistical deviation for the binary value O is established in the data of the stored unit such that the number of conversions can be reduced when the data is previously written to a memory location using the previously stored data. .

By way of introduction, FIG. 1 is a simplified block diagram of a data processing system 10 suitable for use in practicing the present invention. System 10 includes at least one processor 12 coupled to at least one memory 14. The memory 14 is a memory control unit 16 that is constructed and operative in accordance with an exemplary embodiment of the present invention to help reduce the number of transitions when the material is stored for analysis to be stored in the memory 14. Information in the middle. For the sake of simplicity, the details of the various busbars 18A, 18B, and 18C interconnecting these components are not shown (eg, address, data, and control bus details).

Please note that in some embodiments, processor 12 may be coupled to memory 14 only through memory control unit 16, and in this example bus bar 18A may not be present. It should also be noted that in some embodiments, all or a portion of the memory 14 can be located remotely from the processor 12, which can be the associated memory control unit 16. In this example, one or more of the busbars 18A, 18B, 18C may be regional electrical or optical busbars, or may be remote, such as a local area network (LAN, "Local area network"), wired or wireless, Or a wide area network, like the Internet.

The data processing system 10 can assume any suitable type, such as a host computer, a workstation, a desktop (eg, personal) computer, a laptop or laptop, or one embedded in another device. Data processing system. Processor 12 can be any type of data processor, including a plurality of components, or in an integrated form within a single integrated circuit, such as a microprocessor. Processor 12 can have a single core or a multi-core architecture. The memory 14 can be any kind of suitable memory, and can be embodied in one or more semiconductor memories, such as a semiconductor static random access memory (RAM, "Random access memory") or dynamic RAM. Or it may be embodied as a magnetic storage medium such as a disc or a magnetic tape. In other embodiments, memory 14 can be a semiconductor-based technology based on magnetic principles such as magnetoresistive RAM. In summary, exemplary embodiments of the present invention are particularly useful for those types of data storage memories in which a non-negligible amount of energy is required to change the state of a data storage location, that is, to store a zero bit. The data storage location is converted by storing one bit and/or by storing one bit to one zero.

The memory control unit 16 can be integrated into the memory 14, or it can be a separate unit. It can also have additional functionality, such as operating as a DRAM control unit, or as a disc or tape controller.

Please note that in some embodiments, all of the components shown in Figure 1 can be integrated into the same integrated circuit. Please note that in some embodiments, at least some of the memory 14 may be part of the internal memory of the processor 12, including but not limited to the processor 12 RAM, the scratchpad, and the scratchpad. file.

According to an exemplary embodiment of the present invention and also referring to FIG. 2, the memory control unit 16 is configured to introduce one or more indicator bits (indicators) into a data stream at a certain interval, which is to be written based on the comparison. The data (input data) entered into a specific location in the memory 14 and the data currently stored in the specific location (current data).

For example, suppose a situation is: input data = 10000111 current data = 1111111

For example, a comparison unit 16A of the memory control unit 16 is configured to selectively control the individual bits of the memory of the inverter 16B to reverse some of the bits of the new data to be written to the memory 14 to The number of low-order conversions and the generation of indicator bits to represent the new data. In this non-limiting example, assuming that a data unit is a one-bit tuple (8-bit), a register 20 can be provided to hold the current data read from the memory 14 (eg, All are 1), and the input data, where D7 is 1, D6-D3 is 0, and D2-D0 is 1. Obviously, writing the input data directly to the memory 14 will result in a conversion of four bits (D6-D3). In order to avoid this, the comparing unit 16A detects that the number of bits to be used for conversion equals or exceeds a certain predetermined threshold (for example, 2, 3 or 4), and responds to set the inverter control signal line 16C to The inverter 16B in the path of the bit D7-D3 is caused to reverse the corresponding bit (assuming that if a reverse control signal line 16C is not set, the corresponding inverter 16B simply transmits the same The bit passes but does not reverse it, or a switch only crosses the inverter. The result in this example is that the new data is taken to the memory 14 as follows: new data = 0111111, which is only 8 bits The result of the conversion in one of the bits (in this case, D7). The three indicator bits I2, I1, I0 can be used to indicate the starting point of the pairing inversion in the new data. In a non-restricted example The sequence 000 indicates no change, and the remaining sequences may represent a number from 1 to 7, indicating which one is the start bit (eg, 011 indicates that the third bit and above are changed, and 001 indicates that all bits are changed) In this example, I2 is switched to 1, causing the indicator bit to read as 100 to indicate The four-bit (D3) and above are reversed. Even with this extra bit switch, there is a net reduction in the total number of bits being switched. As is known, the energy required to write the new data to the memory is clearly It is lower than the energy required to write the data directly without reversing any bits.

In order to be able to read this material from the memory 14 and restore it to the original pattern, it is important to set an indicator to notify the reading unit 16D of the memory control unit 16 when the data is stored. Being reversed (if any). This indicator can be used in a number of different styles. In the example illustrated in FIG. 2, the most significant bit position (eg, counted by D7) in the data unit to which the bit is reversed is encoded into a 3-bit value, which should be transmitted to the memory 14 as an index bit. , for storage associated with the stored data unit. In the non-limiting example above, the indicator value will be 4 (100). Then, when the data unit is read back from the memory 14, the reading unit 16D performs the complementary operation to reverse all the values of the bits to the index (in this case, the bits D7-D4), thereby restoring the The data is sent to its original format, thereby providing the output data to the processor 12 or some other component.

In this particular embodiment, it is possible to add an additional indicator bit to specify whether the three indicator bits must be interpreted as being counted by D0 (the LSB of the data unit) or counted from D7 (the MSB of the data unit) .

In the presently described example, the boundaries in the data unit to which the inverse is applied vary with different data units, based on the results obtained by the comparison unit 16A. In another embodiment, the data unit can be partitioned into predetermined sub-units (e.g., 4-bit sub-units in the presently described example), and then an indicator bit is provided for each sub-unit to indicate Whether the corresponding secondary unit is reversed or not reversed. In the above example, it is assumed that the input data = 1000 0111 current data = 1111 1111, Then applying the comparison threshold to each sub-unit will only cause the leftmost sub-unit to be reversed, resulting in: new data = 0111 0111.

The indicator field in this example only needs 2 bits long to represent the matching of each sub-unit, and can have the following value = 10.

Indicates that the leftmost subunit has been reversed.

In other embodiments, the width of each sub-unit may be 2 bits, and then the width of the indicator field will be 4 bits to indicate whether each corresponding 2-bit of the data unit has been inverted. Or not reversed. Continue with the above example: input data = 10 00 01 11 current data = 11 11 11 11, then apply the comparison threshold (in this case, 2) to each sub-unit will only cause the second leftmost sub-unit Being reversed, resulting in: new information = 10 11 01 11.

In this example, the indicator field length is only 4 bits, and its value is index=0100.

Indicates that the second leftmost subunit has been reversed.

In another example, the indicator bit field can be made as wide as the data unit (in this case, 8-bit), wherein individual bits in the indicator field are set or reset. Indicates that the corresponding bits in the data unit are reversed or not reversed, respectively.

It can be appreciated that there are many possible ways to implement the specific embodiments of the present invention. In another example, and referring again to the aforementioned 8-base indicator representation, more than two such 3-bit fields may be provided to indicate the selective application of more than two positions of the bit inversion. In addition, inverter 16B may be replaced by some sort of logic gate, such as a mutual exclusion, or its operation will cause a selective reverse to be written to the desired bit in the bits of memory 14. In order to reduce the number of conversions.

Furthermore, it must be understood that the exemplary embodiments of the present invention are not limited to data units having a width of 8 bits, as described above, which can be applied to any data unit requiring a width (for example, 64-bit, 256-bit units). Wait).

Referring to Figure 3A, a non-limiting example of the operation of memory control unit 16 is now provided.

Step A: reading the current data stored in a memory location; step B: comparing the input data to be written with the current data, and counting If the new data is overwritten by the mutual exclusion of the current data and the input data, and the number of "1"s in the total exclusion or the result is overwritten, the summation result sum1 represents The number of bit transitions that will occur if the input data overwrites the current data; step C: compares sum1 with a predetermined threshold, and if sum1 equals or exceeds the threshold, negates all or part of the input data Executing a mutual exclusion or the current data, and calculating a second sum2, wherein if the value of the negative input data of sum2+1 is less than sum1, the number of bit conversions will be if the negative input data is written to The memory location is lowered; and step D: setting at least one indicator bit in a corresponding indicator field to indicate whether the input data is stored, or a negative pattern of all or a part of the input data Whether it is stored in this memory location.

Another step E includes subsequently reading the data stored in the memory location and the corresponding indicator field, and selectively or not reversing the bit according to the bit set in the corresponding indicator field. The bit to read the data.

In step B, the energy required to write the material is represented by E _write * Sum + E _Read * 8.

The foregoing example is shown in Figure 3B, where the example assumes that the current data is all zero and the value of the data ranges from 250 to 255. In this example, an indicator bit is used in an 8-bit character. A one-bit is added to indicate that the change in the pair is displayed in Sum Xor+1, which represents the total number of bits to be switched after the pairing change.

Figure 4 illustrates an operation 1 in accordance with an exemplary embodiment of the present invention. Description of the method of the memory device. The method includes, in block 4A, determining whether to write data of the second unit to at least one unit before overwriting a data of the first unit with a data of the second unit at a position in the memory device. The data of the second unit in which the locator reverses will require more energy. If it is determined that writing data using the second unit that reverses the bit in at least one of the cells would require less energy, the method further includes correcting the bit inversion in at least one of the cells in block 4B. The data of the second unit overwrites the data of the first unit, and writes at least one bit to indicate the position in the data of the unit of the correction of the data of the secondary unit having the reversed bit.

The plurality of blocks shown in FIGS. 3A and 4 may be considered as method steps, and/or as jobs, due to execution results of computer code stored in a computer readable medium, and/or A plurality of coupled logic circuit elements that perform the relevant functions are constructed. It is also noted that some or all of the functions of the memory control unit 16 shown in FIG. 2 can be implemented by executing computer code stored in a computer readable medium, either alone or in combination with a hardware circuit.

It must also be noted that the indicator field can be stored in relation to the corresponding data bit in the same memory 14, or it can be stored in another memory of the same or different kind, which is addressed and synchronized to the address and The (data) memory 14 is read for reading.

Please note that the specific embodiment of the present invention provides a safe level of the data stored in the memory 14, which does not require the corresponding information stored in the indicator field, which would be more difficult to read and Interpret the information (with Selectively multiple bits in the entire reverse).

Particular embodiments of the invention are also directed to hard disk drives having patterned media.

An exemplary embodiment of the present invention can be applied to a hard disk drive in which a long stream of data is stored in a magnetic zone. Currently, the disk drive stores approximately 512 bytes in a magnetic region, while the magnetic regions are substantially rewritten in blocks. However, other disk media are projected and patterned in such a way that each bit exists in an individual discrete portion of the patterned media and can be individually written. The write current can be reduced by reducing the number of transitions from 1 to 0 or vice versa. In a very long stream of data, the indicator bits can be applied.

A magnetic zone is the basic unit for data storage on a hard disk drive. The term "magnetic region" is derived from mathematical terminology, which is referred to as a circular segment of angular shape, bounded by a radius on both sides, and the third side is bounded by the circumference of the circle. In essence, a hard disk includes a group of predetermined magnetic regions forming a circle, and a given circle of the predetermined magnetic region is defined as a single track. A concentric group (track) defines a single surface of a disc. Each track position of an early hard disk drive has the same number of magnetic regions, and the number of magnetic regions in each track is substantially standard between different models. When a hard disk drive is prepared with its preset value, each magnetic zone can store 512 bytes of data. Current advances in hard disk drive technology have allowed the number of magnetic zones ("SPT", "Sector per track") per track to vary significantly.

The benefits of an exemplary embodiment of the present invention can be applied to both a hard disk drive having a fixed number of magnetic regions per track and a hard disk drive having a variable number of tracks per track. Exemplary embodiments of the present invention may also be used to improve based on A hard disk drive for patterning media in which individual bits can be recorded separately (which is relative to at least one entire magnetic zone recorded per write job).

The indicator field of the data of a magnetic zone can be stored at the beginning or end of the magnetic zone as needed. Additionally, one or more magnetic regions of a given track may be dedicated to index fields stored in all of the magnetic regions of the track. Other configurations of indicator information relative to the stored disk data may also be used.

It is noted that in a data storage implementation implemented using a disk array, the array has a specific embodiment such as a "Redundant array of inexpensive disks" ( As a non-limiting example, 8 drives can be used to store the data, and a ninth disk drive can be used to store the indicator information for error detection and correction. It is also possible for some other RAID-style organizations.

Exemplary embodiments of the present invention may be used in other ways to pre-process data to be written to memory. For example, in some applications, data can be rewritten frequently. A non-limiting example is an application in which transaction information for a plurality of clients can be archived within one day. Referring to FIG. 5, a data buffer 30, such as a first in first out (FIFO) buffer, can be provided for being used before the client information is transferred to the memory 14. Store. By reading and pre-processing the information stored in the data buffer 30, the number of conversions can be reduced in the material actually written to the memory 14. For example, recognizing that the previous data byte #2 matches the current data, the conversions need not be reversed, which will be written to the memory 32 first, then the data byte, when the data byte #2 is first written. #1, then the current data byte occurs.

Current data 00001111 data byte group #1 11111111 data byte group #2 00001111

In this example, and when the current data matching data byte #2 is detected, only the current data needs to be written, not the data bytes #2 and #1 (or only the data byte # 2 is transferred to the memory 14, and the data byte #1 and the current data byte can be erased).

Note that when the buffer 30 is described as storing the data to be written to the same location in the memory 32, in other embodiments, the buffer 30 can store the arithmetic logic unit (ALU) to be applied to the processor 12. , "Arithmetic logic unit").

Figure 6 shows a simplified view of a portion of a data processor, such as microprocessor 60, which includes ALU 70, registers A72, B74, and C68, instruction decoder 62, and instruction register 66. , counter 76 and address latch 78. Counter 76 and address latch 78 are coupled to address bus 80. Microprocessor 60 can execute a set of instructions, a subset of which is shown below.

. LOAD A - Loading of a value to a memory address register A. LOAD B - B register to load a value of a memory address. CON A - loading a predetermined value to register A. CON B - predetermined value loaded into register B. CON C - loading a predetermined value to the register C. SAVE B - Stores the value in register B to a memory address . SAVE C - Stores the value in register C to a memory address . ADD - Adds the value in register A to the value in register B and stores the result in register C. SUB- the value obtained by subtracting the value in the register B in the register A, and stores the result to the register C. MUL - the value in register A is multiplied by the value in the register B, and stores the result to the register C. DIV - Divide the value in register A by the value in register B and store the result in scratchpad C

A program is a set of serialized instructions. Microprocessor 60 consumes energy to change the state of the bits in the circuitry of ALU 70 or registers 68, 72, and 74. A method that reduces the number of bits that are changed can reduce the overall energy of the operation. One method that can accomplish this is to include a power adapter 64 in the microprocessor 60 that can inspect the command and data busbars 82 to minimize the number of transitions and thus the power required.

In a non-limiting example, adding 1 and 255 causes a change of 0000 0000 1111 1111 to 0000 0001 0000 0000, which requires a conversion of 9 bits from 0 to 1 or 1 to 0. This change can be performed by the following instruction set: LOAD A 200 (in this case, the value loaded into register A in memory locations 200-255) CON B 1 (loading the number "1" to the scratchpad B) ADD (add the value in register A and the value in register B and store it in register C)

The power dispatcher 64 monitors the instruction register 66, the data bus 82, and the registers 68, 72, and 74 can replace the instructions of certain instruction sequences with a reduced energy instruction set, for example: CON C 256 Enter the number "256" into the scratchpad C)

This instruction (CON C 256) eliminates or reduces the processing that will occur in the ALU 70, and the bit changes in the registers A 72 and B 74 to save energy.

FIG. 7 is a description of a method of operating power adapter 64 in accordance with an exemplary embodiment of the present invention. The method includes: in block 100, reading a first set of instructions; in block 110, reading a data bus; and in block 120, reading the stored in at least one data register The scratchpad value. The method further provides that the power adapter 64 in block 130 analyzes the first instruction set, data bus, and scratchpad values for energy usage purposes. In block 140, if a second set of instructions is determined to provide the same result as the first set of instructions with lower energy usage, it is used to replace the first set of instructions. The resulting set of instructions can then be applied to the ALU 70.

The method of operating the power adapter 64 can be implemented only on a hardware, or in a soft body, including a firmware, or a combination of hardware and software, including a firmware.

Exemplary embodiments of the invention may also be implemented using a power class. In some aspects related to the prior embodiments, power consumption can be reduced and further reduced by the use of memory buffer 30, which preferably consumes less power per conversion than memory 14. To maintain the information you want to store.

The skilled artisan can clearly see a variety of corrections and adjustments when reading the previous descriptions and reading them in conjunction with the accompanying drawings and the scope of the patent application. For example, other similar or equivalent memory devices, circuit and system architectures, data widths, and the like may be used by those skilled in the art. However, all such and similar modifications of the teachings of the present invention will still fall within the scope of the present invention.

In another example, it is possible to use more than two levels of logic in a system/memory architecture (eg, it is possible to use three levels of logic levels), and the indicator bits can be placed directly in the data stream. And decoding the image is the material read from the memory device.

In this example, for example, the data is stored using two logical levels, and the indicator bits are stored using a third logical level. In this case, the indicator field can be considered to be scattered throughout the entire data that is stored and read back.

Moreover, the use of certain features of the examples of the invention may be advantageous without the corresponding use of other features. Accordingly, the foregoing description is to be considered as illustrative of

10‧‧‧Data Processing System

12‧‧‧ Processor

14‧‧‧ memory

16‧‧‧Memory Control Unit

16A‧‧‧Comparative unit

16B‧‧‧ reverser

16C‧‧‧Inverter control signal line

16D‧‧‧Reading unit

18A‧‧‧ busbar

18B‧‧‧ Busbar

18C‧‧‧ busbar

20‧‧‧ register

30‧‧‧Data buffer

60‧‧‧Microprocessor

62‧‧‧ instruction decoder

64‧‧‧Power adapter

66‧‧‧ instruction register

68‧‧‧Scratchpad C

70‧‧‧Arithmetic Logic Unit

72‧‧‧Storage A

74‧‧‧Register B

76‧‧‧ counter

78‧‧‧ address latch

80‧‧‧ address bus

82‧‧‧ data bus

The foregoing and other aspects of these techniques are apparent from the following detailed description of the preferred embodiments of the preferred embodiments, in which: FIG. 1 is a simplified block of a data processing system suitable for use in the practice of the present invention. Figure.

Figure 2 is a simplified block diagram of a portion of a memory control unit of Figure 1 in accordance with an exemplary embodiment of the present invention.

Figure 3A is a logic flow diagram of a non-limiting example of a method of operating the memory control unit of Figure 1.

Figure 3B is a table of various examples of input data for current data having the same value, which reflects the operation of the method of Figure 3A.

Figure 4 is a logic flow diagram of a non-limiting example of a method in accordance with the present invention.

Figure 5 is a data buffer managed in accordance with an exemplary embodiment of the present invention.

Figure 6 is a simplified block diagram of a portion (such as a microprocessor) suitable for use in implementing the data processor of the present invention.

Figure 7 is a logic flow diagram of a non-limiting example of a method in accordance with the present invention.

14‧‧‧ memory

16‧‧‧Memory Control Unit

16A‧‧‧Comparative unit

16B‧‧‧ reverser

16C‧‧‧Inverter control signal line

16D‧‧‧Reading unit

20‧‧‧ register

Claims (35)

A method of operating a memory device, comprising the steps of: determining whether to write data of the second unit to a second unit before overwriting data of a first unit at a location in the memory device; Correcting the data of the second unit requires more energy, wherein the data of the modified second unit includes at least one unit having a reverse bit and the second unit having at least one other sub-unit having no reverse bit Data; in response to determining that the data to be written into the second unit of the correction requires less energy, the data of the first unit is overwritten with the data of the modified second unit, and at least one bit is written to indicate Correcting a position of the at least one unit of the second unit having the reverse bit. The method of claim 1, further comprising: subsequently reading the data of the modified second unit and the at least one bit, and causing the bit to be indicated as any sub-unit having the reverse bit The meta is reversed to provide output data. The method of claim 1, wherein the data of one unit comprises N bits, wherein N is an integer, and wherein the primary unit comprises one bit to N bits. The method of claim 1, wherein the at least one bit comprises a plurality of bits that are encoded into a group to indicate a value. The method of claim 1, wherein the at least one bit comprises a plurality of bits, wherein the individual bits of the plurality of bits Specifies the individual subunits corresponding to one of the plurality of subunits. The method of claim 1, wherein the memory device comprises a semiconductor memory device. The method of claim 1, wherein the memory device comprises a disc or a tape type memory device. The method of claim 1, wherein the at least one bit is the same as the memory device in which the data of the modified second unit is written. The method of claim 1, wherein the at least one bit is written to a memory device different from the memory device in which the data of the modified second unit is written. The method of claim 1, further comprising buffering the data of the second unit before writing the data of the second unit to the memory device. An apparatus for operating a memory device, comprising: a memory control unit configured to determine whether to write the first unit before the data of the first unit is overwritten by a second unit of data at a location in the memory device The data of the two units requires less energy than the data of the modified second unit, wherein the data of the modified second unit includes at least one unit having the reversed bit and at least one other time having the unverted bit. Data of the second unit of the unit; the memory control unit is further configured to respond to the decision to write the modified second unit to require less energy, and to transmit the correction to the memory device in conjunction with an indicator field The second unit of information, where the finger The target field includes at least one bit to indicate a position of the modified second unit of the at least one unit having the reversed bit. The device of claim 11, wherein the memory control device further comprises: configured to respond to the reading of the corrected second unit data and the corresponding indicator field, wherein the indication is After the bit of any sub-unit having the reverse bit is inverted, the output data is provided. The device of claim 11, wherein the data of one unit comprises N bits, wherein N is an integer, and wherein the primary unit comprises one bit to N bits. The device of claim 11, wherein the indicator field comprises a plurality of bits, which are encoded into a group to indicate a value. The device of claim 11, wherein the indicator field comprises a plurality of bits, wherein the individual bits of the plurality of bits specify an individual sub-unit corresponding to one of the plurality of sub-units. The device of claim 11, wherein the memory device comprises a semiconductor memory device. The device of claim 11, wherein the memory device comprises a disc or a tape type memory device. The device of claim 11, wherein the indicator field is the same as the memory device in which the data of the modified second unit is written. The device of claim 11, wherein the indicator field is written to a memory device different from the memory device to which the data of the modified second unit is written. The device described in claim 11 is specifically embodied as an integrated circuit. The device of claim 11, which is embodied as an integrated circuit having a data processor and having the memory device. The device of claim 21, wherein the memory device comprises a portion of the data processor. The device of claim 11, further comprising a buffer for listing the data of the second unit before writing the data of the second unit to the memory device. A memory medium storing computer program instructions, which may be caused by an operation of: determining whether to write the first unit before overwriting a first unit of data with a second unit of data at a position in the memory device The data of the two units requires more energy than writing the data of the second unit, wherein the data of the modified second unit includes at least one unit having the reverse bit and at least one other time having the unverted bit. Data of the second unit of the unit; in response to determining that the data written to the second unit of the correction requires less energy, the data of the first unit is overwritten with the data of the modified second unit, and at least one is written a bit to indicate a position of the at least one unit having the reverse bit in the data of the modified second unit. The memory medium according to claim 24 of the patent application, further comprising a And a job, in response to successively reading the data of the modified second unit and the at least one bit, such that the bit indicated as having any sub-unit of the reverse bit is inverted to provide output data. The memory medium of claim 24, wherein the data of one unit comprises N bits, wherein N is an integer, and wherein the primary unit comprises one bit to N bits. The memory medium of claim 24, wherein the at least one bit comprises a plurality of bits encoded as a group to indicate a value. The memory medium of claim 24, wherein the at least one bit element comprises a plurality of bits, wherein the individual bits of the plurality of bits specify an individual sub-unit corresponding to one of the plurality of sub-units . The memory medium of claim 24, wherein the memory device comprises a semiconductor memory device. The memory medium of claim 24, wherein the memory device comprises a disc or a tape type memory device. The memory medium of claim 24, wherein the at least one bit is the same as the memory device in which the data of the modified second unit is written. The memory medium of claim 24, wherein the at least one bit is written to a memory device different from the memory device in which the data of the modified second unit is written. The memory medium according to claim 24, further comprising: buffering before writing the data of the second unit to the memory device Information on the second unit. A method of operating a memory control unit, comprising the steps of: reading current data stored in a memory location; comparing input data to be written with the current data, and calculating if by executing the current data a "exclusive OR" between the input data, and summing the number of "1"s in the mutually exclusive result, the number of bit conversions occurring when the input data overwrites the current data, The summation result sum1 represents the number of bit conversions that will occur if the input data overwrites the current data; comparing sum1 with a predetermined threshold, in response to determining that sum1 equals or exceeds the threshold, by negating the input At least a portion of the data to produce a negative input data, wherein at least one other portion of the input data is not negated; the negative input data is compared with the current data, and if the current data is executed by the negative Enter a "mutual exclusion" between the data and add the number of "1"s in the result of the exclusive exclusion. The negative input data overwrites the bit rotation that occurred when the current data was overwritten. The number of substitutions, wherein the summation result sum2 represents the number of bit conversions that will occur if the negative input data overwrites the current data; a value corresponding to the decision sum2+1 is less than sum1, in a corresponding indicator field And setting at least one indicator bit to indicate that a part of the negative pattern of the input data is stored in the memory location. For example, the method described in claim 34, and the subsequent reading The data stored in the memory location and the corresponding indicator field, and the bit of the read data is selectively inverted or not inverted according to the bit set in the corresponding indicator field.