TW200912642A - Method, apparatus and computer program product providing instruction monitoring for reduction of energy usage and energy reduction when storing data in a memory - Google Patents

Abstract

A method is disclosed to operate a memory device. The method includes, prior to overwriting a first unit of data at a location in a memory device with a second unit of data, determining if more energy is required to write the second unit of data than to write the second unit of data with at least one sub-unit thereof having bits that are inverted. If it is determined that less energy is required to write the second unit of data with the at least one sub-unit thereof having bits that are inverted, the method further includes overwriting the fast unit of data with a modified second unit of data with the at least one sub-unit thereof having bits that are inverted, in conjunction with writing at least one bit memory for indicating a location in the modified unit of data of the sub-unit of data having the inverted bits. Moreover, a method is disclosed to operate a power advisor. The method includes, reading a fast instruction set; reading a data bus; and reading register value(s) stored in at least one data register. ' This information is analyzed for energy usage purposes. If a set of instruction can provide the same result with a lower energy usage, the fast instruction set is replaced with the lower power usage instruction set. An apparatus and computer program product are also disclosed.

Description

200912642 IX. Description of the Invention: [Technical Field of the Invention] Exemplary embodiments of the present invention are generally related to, and more particularly to, storage of data in a computer high energy efficiency technique. [Prior Art] A write operation of an MRAM is disclosed in U.S. Patent Publication No. U.S. Patent No. 5, the entire disclosure of which is incorporated herein by reference. The write operation includes comparing the input data with the read data read by the self-column and using a data encoder to form the write data. It also discloses the use of a data decoding material to form an output data. The number of bits to be written during a non-volatile semiconductor write operation can be reduced or reduced. A method and apparatus for updating dynamic random access memory in a computing system is reduced in Cohen's U.S. Patent No. 6,633,951. In one embodiment, the data to be stored is evaluated in one character at a time. For each 8 bits, if the number exceeds four, each bit data reverse indicator bit of the data character is set to a logical one to indicate the reverse. This allows the material to be properly presented as a material. Since the data stored in the DRAM is required to be stored and the magnetic content of the readable TJ component of the media can be read, the memory cell array is consumed to decode the read memory. And the current consumption reveals a meta-data character for the body to be stored in the DRA, is reversed, and shows that the data has been stored by a minimum number of powers, storing 200912642 the minimum number of data can reduce the power Consumption. The reading of the data determines whether the data has been reversed at the time of storage, and if so, the read data is returned to its original format.

A method and system is disclosed in U.S. Patent No. 5,873,112, the entire disclosure of which is incorporated herein by reference to the entire disclosure of the entire disclosure of the entire disclosure of the disclosure of An erased cell to a flash memory array, wherein writing a cell having a first value to an erased cell consumes less than writing a bit having a second value to the cell Power. A count signal is generated for the original bit of each packet to indicate the number of bits of the packet having the first (or second) value, the count signal being processed to generate a control signal that determines the packet's The encoding, and the original bits of the packet are encoded according to a scheme determined by the control signal. Each erased cell can indicate a binary value of "1", and the count signal produces a control signal relative to a reference value (representing X/2), which can determine whether the packet must be reversed in polarity, and The packet is inverted (or not inverted) based on the value of the control signal. The count signal can be generated for a bit of each packet to be written to an array of erased cells (where the count signal indicates that the number of bits in the packet has a particular value), and each packet Coding is performed in a manner determined by the corresponding count signal to reduce the power required to write the coded bits to the erased cells. Flag cells indicating the encoding of each packet are generated, and the flag bits (and the encoded packets) are stored in the cells of the flash memory array. Other techniques for controlling memory power consumption are disclosed in IBM Technology 200912642 Abstract 30, Issue 1, June 1987, pages 304-305, "Power Reduction Scheme with Data-Dependent Write"; IBM Technical Abstracts 11-89, 415-416, "Reduced Power for High Performance Memory"; and in the IEEE paper, Marcello Duhalde' et al. (1995), 1057-1 060 "One High-Performance Modular Embedded ROM Architecture (A High Performance Modular Embedded ROM Architecture) ° c? Improvements to these conventional technologies are needed to further reduce power consumption in currently available and future data storage devices and systems And the resulting thermal load due to power consumption. SUMMARY OF THE INVENTION The foregoing and other problems have been overcome and other advantages are realized in accordance with the exemplary embodiments of the invention. A first aspect of an exemplary embodiment of the present invention provides a method of operating a memory device by a square Q method. The method includes: prior to overwriting a first cell of data at a location in the memory device using data from a second cell, determining to write to the second cell compared to using at least one cell having a reverse bit Data, whether it is required to write the data of the second unit requires more energy; if it is decided to use less than one unit with the reverse bit to write the data of the second unit, less energy is needed, and at least the reverse bit is utilized. The primary unit 'overwrites the data of the first unit with a modified second unit data, and writes at least one bit to indicate the correction unit of the secondary unit having the reversed bit 7 200912642 A location in the data.

Another aspect of an exemplary embodiment of the present invention provides an apparatus for operating a memory device including a memory control unit configured to utilize a second unit of data in a memory device Before the location of the data of the first unit is overwritten, it is determined that it is less energy to write the data of the second unit than the data written to the second unit by using at least one unit having the reversed bit; The memory control unit is further configured to respond to the data written to the second unit by using at least one unit having the reversed bit, and the data written to the second unit requires less energy to determine An indicator field for transmitting, by the at least one unit having the reverse bit, a data of the modified second unit, wherein the indicator field includes at least one bit to indicate that the reverse bit is present A position of the data of the correction unit of the data of the sub-unit. Another aspect of an exemplary embodiment of the present invention provides a computer readable memory medium capable of storing computer program instructions, the operations of which are performed by: utilizing a second unit of data in a memory device Before the information of the first unit is overwritten at the middle position, it is determined that whether the data of the second unit is written into the second unit is more energy than the data written to the second unit by using at least one unit having the reversed bit. If it is decided that the data written to the second unit by at least one unit having the reverse bit requires less energy, then the at least one unit having the reversed bit is used to overwrite the data of the second unit with a correction. The data of the first unit is matched with at least one bit to indicate a position in the data of the correction unit of the secondary unit having the reversed bit. 8 200912642

Yet another aspect of an exemplary embodiment of the present invention provides a method of operating a memory control unit. The method includes: reading current data stored in a memory location; comparing input data to be written with the current data, and calculating a mutual exclusion between execution of the current data and the input data Or (e X c 1 usive 0 R)", and add the number of "1"s in the result of the mutual exclusion, the number of bit conversions that occur when the new data overwrites the current data, wherein the sum result sum 1 represents the number of bit transitions that will occur if the input data overwrites the current data; compares sum 1 with a predetermined threshold, and if suml equals or exceeds the threshold, denies all or part of the input data Executing a mutual exclusion with the current data, and calculating a second sum2, wherein if the value of the sum2+l of the negative input data is less than sum1, the number of bit conversions will be if the negative input data is When it is written to the memory location, it is lowered; and in a corresponding indicator field, at least one indicator bit is set to indicate whether the input data is stored, or whether all or part of the input data is input. Negative patterns are stored in the memory location. Another aspect of an exemplary embodiment of the present invention provides a method of operating a power adapter. The method includes reading a first set of instructions; reading a data bus; and reading a register value stored in the at least one data register. This information is analyzed for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power use instruction set. Yet another aspect of an exemplary embodiment of the present invention provides an apparatus coupled to an instruction register, a data bus, and at least one of the 2009-1242 first instruction sets; reading the data bus; The register value in the device is for the device. If a set of instructions can provide a lower material register. The scratch is read and the information stored in the data temporary storage is used to analyze the information.

The phonogram is the same, and the result 'the first * 4t A 4 曰 · 7 episode is replaced by the lower power use instruction set.

Another aspect of the exemplary embodiment of the present invention provides a computer readable memory medium capable of storing computer program instructions, the operations caused by the execution include: reading a first instruction set; reading a data bus丨 and read the scratchpad value stored in at least one data register. This information is for the purpose of energy use. If a set of instructions can provide the same result using lower energy, the first instruction set is replaced by the lower power usage instruction set. Yet another aspect of an exemplary embodiment of the present invention provides an apparatus. The device has means for reading a first instruction set; reading a data bus; and reading a temporary value stored in at least one data register. The device analyzes this information for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power use instruction set. Yet another aspect of an exemplary embodiment of the present invention provides a method of operating a power adapter. The method includes reading a first set of instructions; reading a data bus; and reading a register value stored in the at least one data register. This information is analyzed for energy usage purposes. If a set of instructions provides the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set. 10 200912642 Yet another aspect of an exemplary embodiment of the present invention provides a device coupled to an instruction register, a data bus, and at least one data register. The device reads the first instruction set; reads the data bus; and reads the value of the register stored in the data register. The device analyzes this information for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power usage instruction set. In another aspect of an exemplary embodiment of the present invention, a computer readable memory medium is provided, which can store computer program instructions, and the operations caused by the execution include: reading a first instruction set; reading a data Bus; and reads the value of the scratchpad stored in at least one data register. This information is analyzed for energy use purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power use instruction set. Another aspect of an exemplary embodiment of the present invention provides an apparatus. The device has means for reading a first set of instructions; reading a data bus; and reading the value of the register stored in the at least one data register. The device analyzes this information for energy usage purposes. If a set of instructions can provide the same result using lower energy, the first set of instructions is replaced by the lower power use instruction set. [Embodiment] The use of an exemplary embodiment of the present invention can reduce the amount of energy required to store information in a memory device. 11

200912642 Exemplary embodiments of the present invention utilize techniques that reduce the number of digital material conversions (1 to 〇 or 〇 to 1), thus reducing the amount of energy consumed in storing a data device. The use of an exemplary embodiment of the present invention is advantageous for a memory device in which the energy of the memory is to be changed as a primary energy item. In a first exemplary implementation, data previously stored in a unit in a memory device is read prior to writing to determine whether a portion of the data of the unit or the portion of the unit is Negative patterns can utilize fewer conversions and therefore are stored with lower amounts. If it is determined that a portion of the data of the unit can be stored with less conversion, that is, one or more indicators are stored to specify which part or portions of the unit data will be stored in the reversed version. . The indicator can be obtained subsequently when the data of the unit is read for restoring the original version of the unit's data. In another exemplary embodiment, for establishing a pair in the stored unit material The statistical deviation of the binary value 0 makes it possible to reduce the number of conversions when the data is first written to a memory location by using the first stored data. By way of introduction, FIG. 1 is a simplified diagram of the data processing system 10 suitable for implementing the present invention. Block diagram. System 10 includes at least one processor 12 that is coupled to at least one memory 14. The memory associated with memory 14 is a memory control unit 16, which is constructed in accordance with an exemplary embodiment of the present invention. In order to reduce the number of conversions when the data is stored, the data to be stored in the memory 14 is divided. For the sake of simplicity, a plurality of busbars interconnecting these pieces are connected to the 8 8 A, 1 8 B And the details of 1 8 C are not shown (such as the details of the address, data and control bus). The capital is in the form of the material can be compared to the previous one.

200912642 Please note that in some embodiments, the processor 1 2 control unit 16 is coupled to the memory 14 and may not be present in this example. It should also be noted that in whole or in part some embodiments may be located remotely from the processor 12, which may be in the memory control unit 16. In this example, one or more of busbars 18C may be regional electrical or optical busbars, or may be a remote network (LAN, "Local area network"), wired or wireless, such as the Internet. The data processing system 1 can assume any suitable type, such as a computer, a workstation, a desktop (e.g., personal) computer, a notebook computer, or a system embedded in another device. Processor 12 can be any type of data processor, packaged, or integrated in a single integrated circuit. Processor 12 can have a single core or architecture. The memory 14 can be any kind of suitable memory, and in one or more semiconductor memories, such as a semiconductor memory (RAM, "Random access memory") or 1 or it can be embodied as a magnetic Storage Media, Such as Discs In other embodiments, the memory 14 may be a semiconductor-based technology based on magnetically resistive RAM. In summary, the embodiments of the present invention are particularly useful for those types of data storage memories to change the amount of energy to change a data storage location, that is, to store a zero bit to store a bit and/or to One zero bit to convert the data storage location. Only through the memory bus 1 8 A, the memory 1 4 is related to the record 18 A, 1 8B, like the area, or the WAN is a host type one laptop or data processing consists of multiple groups , like a multi-core rack can be implemented statically random state RAM, or tape. In the case of magnetic (such as magnetic specific example, the required state, also by storing a bit 13 200912642 memory control unit 16 can be integrated into the memory 14, or it can be a stand-alone unit. It can also have Additional functionality, such as operating as a DRAM control unit, or becoming a disc or tape controller.

It is noted that in some embodiments, all of the components shown in Figure 1 can be integrated into the same integrated circuit. Please note that in some embodiments, at least some of the memory 14 may be part of the internal memory of the processor 12, including but not limited to the processor 1 2 RA 暂, the register And the scratchpad file. According to an exemplary embodiment of the present invention and also referring to FIG. 2, the memory control unit 16 is configured to introduce one or more indicator bits (indicators) into a data stream at a certain interval, which is based on comparison The data (input data) written to a specific location in the memory 14 is associated with the poor material (current data) currently stored in the specific location. For example, suppose a condition is: Input data = 1 0000 1 1 1 Current data = 11111111 For example, a comparison unit 16 of the memory control unit 16 is used to selectively control the inverter 16 6 B - the individual of the memory bank The bit, in reverse, is written to certain bits in the new data of the memory 14 to reduce the number of bit conversions and generate indicator bits to represent the new data. In this non-limiting example, assuming that a data unit is one-tuple (8-bit) in length, a register 20 can be provided to hold the current data read from the memory 14 (eg, 14).

200912642 is all 1), and the input data, where D7 is 1, D6-D3 is D 2 - D 0 is 1. Obviously, writing the input data directly to memory j results in a conversion of four bits (D 6 - D 3 ). In order to avoid this situation, it is detected that the number of bits to be used for conversion equals or exceeds a certain threshold (for example, 2, 3 or 4), and responds to set the inverter control 16C > The inverter 16B in the path of the bit D7-D3 corresponds to the corresponding bit (assuming that if a reverse control signal line 16 C is determined, the corresponding inverter 16 B simply transmits the bit through It reverses, or a switch only crosses the inverter. In this example, the new data is taken to the memory 14 as follows: New data = 01111111 > is only one bit in 8 bits (in In this case, the result of the change in D 7). The three indicator bits 12, 11, 10 can be used to indicate the starting point of the pairing inversion in the material. In a non-restricted example, the order indication is unchanged, while the rest The sequence may represent the number of bits from 1 to 7 as the start bit (eg 0 1 1 indicates the third bit and change, and 0 0 1 indicates that all bits change). In this case, switch to 1 , so that the indicator bit is read as 1 0 0 to indicate that the fourth bit and above are reversed. Even with this extra bit switch, There is a net reduction in the total number of tangents. As is known, the energy required to write the new data is significantly lower than the energy required to write directly to the data without reversing it. 0, and I 14 will Compared with the predetermined signal line of the unit, the reverse direction is not set, but the result is that the new resource column 0 0 0 is indicated, indicating that the bit memory replaced by the 12 yuan (D3) is replaced by the bit memory 15 200912642

In order to be able to read this data from the memory 14 and restore it to the original type, it is important to set an indicator to notify the reading unit 16 of the memory control unit 16 that the data is stored. When those bits are reversed (if any). This indicator can be used in a number of different styles. In the example illustrated in Figure 2, the most significant bit position (e.g., counted by D 7) in the data unit in which the bit is reversed is encoded into a 3-bit value, which should be transmitted to the memory as an indicator bit. 1 4, for storage associated with the stored data unit. In the above non-limiting example, the indicator value will be 4 (100). Then, when the data unit is read back from the memory 14, the reading unit 16 6 D performs the complementary operation to reverse the values of all those bits to the index (in this case, the bits D7-D4), In order to restore the data to its original form, thereby providing the output data to the processor 12 or some other component. In this particular embodiment, it is possible to add an additional indicator bit to specify whether the three indicator bits must be interpreted as being counted by D 0 (the LSB of the data unit) or counted from D7 (the MSB of the data unit) ). In the presently described example, the boundaries in the data unit to which the inverse is applied vary with different data units, based on the results obtained by the comparison unit 16 A. In another embodiment, the data unit can be partitioned into predetermined sub-units (e.g., 4-bit sub-units in the presently described example), and then an indicator bit is provided for each sub-unit to indicate Whether the corresponding secondary unit is reversed or not reversed. Assume in the above example: Input data = 1 000 0 1 1 1 Current data = 11111111, 16 200912642 Then applying the comparison threshold to each sub-unit will only cause the leftmost sub-unit to be reversed, resulting in: New Information = 01110111.

L In this example, the indicator field only needs 2 bits long to represent the matching of each sub-unit, and can have the following values: =1 0. Indicates that the leftmost subunit has been reversed. In other embodiments, the width of each sub-unit may be 2 bits, and then the width of the indicator field will be 4 bits to indicate whether each corresponding 2-bit of the data unit has been inverted. Or not reversed. Continue with the previous example: Input data = 1 0 00 01 1 1 Current data = 11111111, then apply the comparison threshold (in this case 2) to each sub-unit will only cause the second leftmost sub-unit to be Reverse, causing: New data = 10110111. 17 200912642 In this example, the indicator is only 4 bits long and its value is indicator = 0100. Indicates that the second leftmost subunit has been reversed.

In another example, the indicator bit field can be made as wide as the data unit (in this case, 8-bit), wherein individual bits in the indicator field are set or reset. Indicates that the corresponding bits in the data unit are reversed or not reversed, respectively. It will be appreciated that there are many possible ways to implement specific embodiments of the invention. In another example, and referring again to the aforementioned 8-based indicator representation, more than two such 3-bit barriers can be provided to indicate the selective application of more than two locations of the bit inversion. In addition, the inverter 16B can be replaced by some kind of logic gate, such as a mutual exclusion, or its operation will cause a selective reverse to be written to the desired bit in the bits of the memory 14. In order to reduce the number of conversions. Furthermore, it must be understood that the exemplary embodiments of the present invention are not limited to data units having a width of eight bits, as described above, which can be applied to any data unit requiring a width (eg, 64 bits, 2 5 6 bits, etc.). Referring to Figure 3A, a non-limiting example of the operation of the memory control unit 16 is now provided. Step A: reading the current data stored in a memory location; Step B: comparing the input data to be written with the current data, and counting 18

200912642 If the new data is overwritten by the execution of the mutual exclusion of the current data and the input data, and the total number of "1"s in the mutually exclusive or results, the summation result sum 1 represents The number of bit conversions that will occur when the input data is overwritten with the current data; Step C: Compare suml with a predetermined threshold, and if suml or exceeds the threshold, negate all or part of the input data to the data Executing a mutual exclusion or, and calculating a second sum2, wherein if the value of sum2 +1 of the rounded data is less than sum 1, the bit conversion destination will be if the negative input data is written to the memory The position is lowered; and step D: setting at least one indicator bit in a corresponding indicator to indicate whether the input data is stored, or whether a negative version of the input data or a part of the input data is stored in the memory location . Another step E includes subsequently reading the data stored in the memory location and the corresponding indicator block, and selectively reversing or not reversing the read data according to the bit in the corresponding indicator field. Bits In step B, the energy required to write the data is represented by Ewrite* + ERead * 8. The foregoing example is shown in Figure 3B, where the example assumes that the object is all 0 and the value of the data ranges from 2 50 to 2 5 5 . In this example, an indicator bit is used in an 8-bit character. Adding a bit indicates that the change in the pairing is displayed at S u m X 〇 r + 1, which represents the total number of bits that will be switched after the pairing is changed. Figure 4 is a diagram showing the fact that the field in the exemplary embodiment in accordance with the exemplary embodiment of the present invention is equal to the current negative number in the field, all of the phases are set in the Sum predecessor, and the change is made as a 19 200912642 Description of the method of the memory device. The method includes, in block 4 A, determining whether the data written to the second unit is used at least once before overwriting a data of the first unit with a data of the second unit at a position in the memory device. The data in the second unit that reverses the bit in the cell will require more energy. If it is determined that writing data using the second unit that reverses the bit in at least one of the cells would require less energy, the method further includes correcting the bit inversion in at least one of the cells in block 4B. The data of the second unit overwrites the data of the first unit, and writes at least one bit to indicate the position in the data of the unit of the correction of the data of the secondary unit having the reversed bit. The plurality of blocks shown in FIGS. 3A and 4 may be considered as method steps, and/or as jobs, due to execution results of computer code stored in a computer readable medium, and/or A plurality of coupled logic circuit elements that perform the relevant functions are constructed. It is also noted that some or all of the functions of the memory control unit 16 shown in Fig. 2 can be implemented by executing computer code stored in a computer readable medium, either alone or in combination with a hardware circuit. It must also be noted that the indicator block can be stored in relation to the corresponding data bit in the same memory 14, or it can be stored in another memory of the same or different kind, which is addressed and synchronized to the address. And read the (data) memory 1 4 to read. Please note that the specific embodiment of the present invention provides a safe level of the data stored in the memory 14, which does not require the corresponding information stored in the indicator block, which would be more difficult to read. And interpret the information (with 20

200912642 Selectively multiple bits in the entire reverse). Particular embodiments of the invention are also directed to having a patterned medium. An exemplary embodiment of the present invention can be used to load a germ stream of a hard disk drive in a magnetic zone. It is seen that the disk drive stores 5 1 2 bytes in a magnetic region, and the magnetic region is substantially rewritten in blocks. Its disk drive media is projected and patterned in a manner that is each of the individual discrete portions of the patterned media, and can be individually reduced by a number of transitions from 1 to 0 or vice versa. low. In a very long data stream, the basic area of the data storage area can be applied to a hard disk drive. The "magnetic area" is derived from mathematical terminology, which is called a circular pie pattern. The sides are bounded by a radius, and the third side is limited by the circumference of the circle. A hard disk contains a group forming a circular predetermined magnetic zone, and a given circle is defined as a single magnetic bar. A concentric group defines a single surface of a disc. Each of the early hard disk drives has the same number of magnetic regions* and is substantially standard between different models in each magnetic track. When a hard disk drive is pre-timed, each magnetic zone can store 5 1 2 bytes of data. Current advances in hard have allowed the number of magnetic regions ("SPT" p e r t r a c k '') of each track to vary significantly. An advantage of an exemplary embodiment of the present invention is that a hard disk drive having a fixed number of magnetic tracks and a hard disk drive having each magnetic track can be simultaneously adapted. Exemplary embodiments of the present invention can also be applied to a hard disk of a body in which a long memory is stored but its bits are written. Borrowing can reduce the yuan. . The term i degree section, L essentially, the predetermined magnetic zone • group (track) number of positional devices in the set value of the disc player technology, "Sector with a per-variable number improvement based on 21 200912642 patterned media hard a disc player in which individual bits can be recorded separately (which is recorded with respect to at least one entire magnetic area in each write operation). A poor bit of a magnetic region can be stored at the beginning or end of the magnetic region as needed. In addition, one or more magnetic regions of a given track may be dedicated to the indicator fields stored in all the magnetic regions of the track. Other configurations may be used with respect to the index information of the stored disk data. .

It is noted that in a data storage implementation implemented using a disk array, the array has a specific embodiment like a Redundant array of inexpensive disks ("RAID"), and as As a non-limiting example, 8 drives can be used to store the data, and a ninth disk drive can be used to store the indicator information for error detection and correction. It is also possible for some other RAID-style organizations. Exemplary embodiments of the present invention may be used in other ways to pre-process data to be written to memory. For example, in some applications, data can be rewritten frequently. A non-limiting example is an application in which transaction information for a plurality of clients can be archived within one day. Referring to FIG. 5, a data buffer 30, such as a first in first out (FIFO) buffer, can be provided for transmitting information to the memory at the client. It was stored before. By reading and pre-processing the information stored in the data buffer 30, the number of conversions can be reduced in the material actually written to the memory 14. For example, recognizing that the previous data byte #2 matches the current data, the conversions need not be reversed, which will be written to the memory 3 2 first, then the data bit, when the data byte #2 is first written. Group #1, then the current data byte occurs. 22 200912642 Current Data 000Oil 11 Data Bits # 1 1 111 1 1 1 1 Data Bits # 2 Ο Ο Ο Ο 1111 In this example, and when the current data match is detected, 'only the current data needs to be Write, and #1 (or only the data byte #2 is transmitted to the quotation voxel #1 and the current data byte can be erased). Please note that when the buffer 30 is described as storing the same location in the memory 3 2, the other 30 can be stored in the processor 12 to be applied to the processor 12, and the different logic "A rithmetic 1 〇gicunit" The indicia refers to a data processor as shown in Fig. 6 as a data processor, such as a microprocessor 60, which includes an ALU 70, a temporary sing and a C68, an instruction decoder 62, an instruction register 66, and a Address latch 78. Counter 76 and address latch 78 are connected 80. Microprocessor 60 can execute a set of instructions, a typical indication being as follows. .LOAD A - Loaded by a memory address - number • LOAD B _ is loaded by a memory address • CONA - load a certain value into the scratchpad a • CON B - load a certain value into the scratchpad b • CON C - Load a certain value into the scratchpad匸

Data byte #2 + byte #2 and 14, and the data written by the data bit to the i example, the buffer unit (ALU, simplified view, F A72, B74 hex 7 6 and Bit-to-address bus set set sub-set value to register A value to register B 23 200912642 • SAVE B - store the value in register B to a memory address • SAVE C - store register C Value in a memory address

• ADD - adds the value in register A to the value in register B and stores the result in scratchpad C

• SUB - Subtracts the value in register B from the value in register A and stores the result in register C.

• MUL - Multiplies the value in register A by the value in register B and stores the result in scratchpad C

• DIV - divides the value in register A by the value in register B and stores the result in register C as a set of serialized instructions. Microprocessor 60 consumes energy to change the state of the bits in the circuitry of ALU 70 or registers 68, 72, and 74. The method of reducing the number of bits that are changed can reduce the overall energy of the operation. One method that can accomplish this is included in a power adapter 64 in the microprocessor 60 that can inspect the command and data bus 82 to minimize the number of transitions and thus the power required. In a non-limiting example, adding 1 and 2 5 5 causes a change of 0 0 0 0 0000 1111 1111 to 0000 0001 0000 0000, which requires a conversion of 9 bits from 0 to 1 or 1 to 0. This change can be performed by the following instruction set: LOAD A 200 (in this case, the value of load scratchpad A in memory location 200-255) CON B 1 (loading the number "1" to the scratchpad B) 24 200912642 ADD (add the value in register A and the value in register B, and store it in register C) Power adapter 6 4 monitor instruction register 6 6 , data bus 8 2, and the registers 68, 72, and 74 can use a reduced energy instruction set to replace certain instruction sequence instructions, for example: CONC256 (loading the number "256" into the scratchpad C) 〇 this instruction ( CON C 25 6) Eliminate or reduce the processing that will occur in the ALU 70, and the bit changes in the registers A 72 and B 74 to save energy. Figure 7 is a description of the method of operating the power adapter 64 in accordance with an exemplary embodiment of the present invention. The method includes: reading, in block 10, a first instruction set; in block 1 1 , reading a data bus; and in block 120, reading and storing at least one data temporary storage The scratchpad Q value in the device. The method further provides that in block 130 power configurator 64 analyzes the first set of instructions, data bus and register values for energy usage purposes. In block 140, if a second set of instructions is determined to provide the same result as the first set of instructions with lower energy usage, it is used to replace the first set of instructions. The resulting set of instructions can then be applied to the ALU 70. The method of operating the power adapter 64 can be implemented only on a hard body, or in a soft body, including a firmware, or a combination of hardware and software, including a tough body. 25 200912642 Exemplary embodiments of the present invention can also be implemented using a power class. In some aspects related to the prior embodiments, the power consumption can be reduced and further reduced by using the memory buffer 30, which preferably consumes less than each conversion of the memory 14. Power to maintain the data to be stored. The skilled artisan can clearly see a variety of corrections and adjustments when reading the previous descriptions and reading them in conjunction with the accompanying drawings and the scope of the patent application. For example, other similar or equivalent memory devices, circuit and system architectures, data widths, and the like may be used by those skilled in the art. However, all of these and similar modifications of the teachings of the present invention will still fall within the scope of the present invention. In another example, it is possible to use more than two levels of logic in a system/memory architecture (eg, it is possible to use three levels of logic levels), and the indicator bits can be placed directly in the data stream. And decoding the image is the material read from the memory device. In this example, for example, the data is stored using two logical levels, and the indicator bits are stored using a third logical level. In this case, the indicator block can be considered to be scattered throughout the entire data that is stored and read back. Moreover, the use of certain features of the examples of the present invention may be advantageous without the use of other features. Accordingly, the descriptions of the present invention are to be construed as merely illustrative, 26 200912642 [Simultaneous Description of the Drawings] The foregoing and other aspects of the techniques are more apparent in the following detailed description of the preferred embodiments and the accompanying drawings, wherein: Figure 1 is applicable to the practice of the invention. A simplified block diagram of a data processing system. Figure 2 is a simplified block diagram of a portion of a memory control unit of Figure 1 in accordance with an exemplary embodiment of the present invention.

Figure 3A is a logic flow diagram of a non-limiting example of a method of operating the memory control unit of Figure 1. Figure 3B is a table of various examples of input data for current data having the same value, which reflects the operation of the method of Figure 3A. Figure 4 is a logic flow diagram of a non-limiting example of a method in accordance with the present invention. Figure 5 is a data buffer managed in accordance with an exemplary embodiment of the present invention. Figure 6 is a simplified block diagram of a portion (e.g., a microprocessor) suitable for use in implementing the data processor of the present invention. Figure 7 is a logic flow diagram of a non-limiting example of a method in accordance with the present invention. [Main component symbol description] 1 0 data processing system 1 6 memory control unit 1 2 processor 1 6 A comparison unit 1 4 memory 1 6 B inverter 27 200912642

1 6 C inverter control signal line 66 means 1 6D reading unit 68 temporary 1 8 A bus bar 70 count 1 8B bus bar 72 temporary 1 8 C bus bar 74 temporary 20 register 76 meter 30 data buffer 78 Bit 60 Microprocessor 80 Bit 62 Instruction Decoder 82 6.4 64 Power Configurator Scratchpad Memory C Logic Logic A Cache B Number Address Locator Bus Queue Bus 1., 28

Claims (1)

200912642 X. Patent Application Range: 1. A method for operating a memory device, comprising the steps of: determining a phase before overwriting a first unit of data at a location in the memory device using data of a second unit; Whether or not writing data of the second unit requires more energy than writing data of the second unit by using at least one unit having a reverse bit; If it is decided that the data written to the second unit by using at least one unit having the reverse bit requires less energy, then the at least one unit having the reversed bit is used to overwrite the data by correcting the data of the second unit. A unit of data, coupled with at least one bit, to indicate a location in the data of the correction unit of the secondary unit having the reversed bit. 2. The method of claim 1, further comprising reading the data of the correction unit and the at least one bit, and causing the bit in any sub-unit indicated as having the inverted bit Reverse to provide output data. 3. The method of claim 1, wherein the information of the unit comprises iV bits, wherein 7V is an integer, and wherein the subunit comprises one bit to 7V bits. 4. The method of claim 1, wherein the at least one bit comprises a plurality of bits encoded as a group to indicate a value. 5. The method of claim 1, wherein the at least one bit comprises a plurality of bits, wherein the individual bits of the plurality of bits specify an individual subunit corresponding to one of the plurality of subunits . The method of claim 1, wherein the memory device comprises a semiconductor memory device. 7. The method of claim 1, wherein the memory device comprises a disc or a tape type memory device. 8. The method of claim 1, wherein the at least one bit is written to the same memory device as the memory device to which the data of the correction unit is written. 9. The method of claim 1, wherein the at least one C, element is written to a memory device different from the memory device to which the data of the correction unit is written. 10. The method of claim 1, further comprising: prior to writing the data of the second unit to the memory device, buffering the data of the second unit, and comparing the data of the second unit with The data of one of the third units in the buffer is successively stored to determine whether the data of the second unit or the data of the third unit is to be written to the memory device. 11. An apparatus for operating a memory device, comprising: a memory control unit configured to determine, prior to overwriting a first unit of data at a location in the memory device, using data from a second unit Whether or not writing data of the second unit requires less energy than writing data of the second unit with at least one unit having an inverted bit; the memory control unit is further configured to respond in response to Compared to the data written to the second unit by using at least one unit having the reverse bit, the data written to the second unit requires less than 30 200912642 energy determination, in conjunction with an indicator field, the memory device Transmitting, by the at least one unit having the reverse bit, a data of the modified second unit, wherein the indicator field includes at least one bit to indicate the data of the secondary unit having the reversed bit Correct a location of the unit's data. 12. The device of claim 1, wherein the memory control device further comprises: configured to respond to the reading of the correction unit and the corresponding indicator field, wherein the indication is After the bit of any sub-unit having the inverted bit is inverted, the output data is provided. The device of claim 11, wherein the information of the unit comprises # bits, where W is an integer, and wherein the unit contains one bit to iV bits. 14. The device of claim 11, wherein the indicator field comprises a plurality of bits that are encoded into a group to indicate a value. 15. The device of claim 11, wherein the indicator block comprises a plurality of bits, wherein the individual bits of the plurality of bits specify an individual subunit corresponding to one of the plurality of subunits . 16. The device of claim 11, wherein the memory device comprises a semiconductor memory device. 17. The device of claim 11, wherein the memory device comprises a disc or a tape type memory device. 18. The apparatus of claim 11, wherein the indicator field is written to the same memory device as the memory device to which the data of the correction unit is written. The apparatus of claim 11, wherein the indicator is written to a memory device that is loaded with the memory to which the correction unit is written. 2 0. The device according to claim 1 of the patent application, which implements an integrated circuit. 21. The apparatus of claim 11, wherein the integrated circuit has a data processor and has the memory. 2 2. The device of claim 21, wherein the memory device comprises a portion of the data processor. 2 3. The device of claim 11, further comprising a device for listing data of the second unit before writing the data of the second unit to the memory, wherein the memory The volume control is further configured to determine whether: after the data of the second unit is stored in the buffer, the data of the second unit or a third unit stored in the buffer is written to the memory The device has less energy. 24. A memory medium storing computer program instructions, the job caused by the execution comprising: before using a second unit of data to overwrite a first unit of data in a memory device, determining a comparison to utilization Writing at least one unit of the reverse bit to the data of the second unit requires more energy to write the data of the second unit; if it is decided to use at least one unit with the reversed bit, the position of the block is not integrated into the body. The buffered unit can be located at the time of the capital requirement, and is written to 32 200912642. The second unit of data requires less energy, and then the at least one unit having the reversed bit is used to correct the second unit. The data overwrites the data of the first unit and cooperates with writing at least one bit to indicate a position in the data of the correction unit of the secondary unit having the reversed bit. The memory medium of claim 24, further comprising an operation responsive to successively reading the data of the correction unit and the at least one bit, so as to be indicated as having a reversed bit The bits of any subunit of the element are reversed to provide output data. 2. The memory medium of claim 24, wherein the information of the unit comprises # bits, where W is an integer, and wherein the unit comprises one bit to # bits. 27. The memory medium of claim 24, wherein the at least one bit comprises a plurality of bits that are encoded into a group to indicate a value. 28. The memory medium of claim 24, wherein the at least one bit comprises a plurality of bits, wherein the individual bits of the plurality of bits specify an individual corresponding to one of the plurality of sub-units Subunit. 29. The memory medium of claim 24, wherein the memory device comprises a semiconductor memory device. 30. The memory medium of claim 24, wherein the memory device comprises a disc or a tape type memory device. 3. The memory medium of claim 24, wherein the at least one bit is written to the same memory device as the memory 33 200912642 device to which the data of the correction unit is written. 3. The memory medium of claim 24, wherein the at least one bit is written to a memory device different from the memory device to which the data of the correction unit is written. 3. The memory medium of claim 24, further comprising: buffering the data of the second unit before writing the data of the second unit to the memory device, and comparing the data of the second unit The data is stored with data of a third unit stored in the buffer to determine whether the data of the second unit or the data of the third unit is to be written to the memory device. 34. A method of operating a memory control unit, comprising the steps of: reading current data stored in a memory location; comparing input data to be written with the current data, and calculating if by performing the current A "exclusive OR" between the data and the input data, and the total number of "1_" in the result of the mutual exclusion or the number of bit conversions that occurred when the new data was overwritten by the current data , wherein the summation result sum 1 represents the number of bit conversions that will occur if the input data overwrites the current data; compares suml with a predetermined threshold, and if suml equals or exceeds the threshold, denies the input data All or part of the current data is mutually exclusive or calculated, and a second sum2 is calculated, wherein if the value of the sum2+l of the negative input data is less than suml, the number of bit conversions will be if the negation When the input data is written into the memory location, it is lowered; and 34 200912642 In a corresponding indicator field, at least one indicator bit is set to indicate whether the input resource is The material is stored, or whether all or a part of the negative version of the input material is stored in the memory location. 35. The method of claim 34, further comprising successive readings stored in the memory The memory location and the data in the corresponding indicator field, and the bit of the read data is selectively inverted or not inverted according to the bit set in the corresponding indicator field. A method for operating a power adapter, comprising the steps of: reading a first instruction set; reading a data bus; reading a register value stored in at least one data register; analyzing the first instruction a set, a data bus, and a register value; and replacing the first set of instructions with a second set of instructions, wherein the second set of instructions provides the same result as the first set of instructions having a lower energy usage. 37. The method of claim 36, wherein the lower energy usage is measured by the overall energy of the operation. 38. The method of claim 36, wherein the lower Energy use The method of claim 36, wherein the instruction set includes at least one instruction from the instruction set, comprising: loading a temporary memory from a memory location Loading a constant to a temporary register; 35 200912642 storing a temporary register to a memory location; adding a first temporary register value to a second temporary register value, and storing the result to a third In the register; subtracting a first register value from a second register value and storing the result in a third register; multiplying a first register value by a second temporary value The value is stored, and the result is stored in a third register; and a second register value is divided by a first register value, and the result is stored in a third register. The method of claim 36, wherein the second set of instructions is executed by an arithmetic logic unit. The method of claim 36, wherein the first instruction set is read by an instruction register. 42. The method of claim 36, wherein the first set of instructions is read prior to being placed into an instruction register, and the second set of instructions is placed into an instruction register The first instruction register was previously replaced. 4 - Apparatus 1 coupled to an instruction register, a data bus, and at least one data register comprising: an input configured to read a first set of instructions stored in the instruction register One configured to read the data bus input; an input configured to read the value of the register stored in the data register; 36 200912642 a processor configured to analyze the first An instruction set, a data bus, and a register value; and an output configured to replace the first instruction set with a second instruction set, wherein the second instruction set is provided with a lower energy usage The first instruction set has the same result. 44. 45. 46. The apparatus of claim 4, wherein the lower energy usage is measured by the overall energy of the operation. The apparatus of claim 4, wherein the lower energy usage is measured by a reduced bit transition. The device of claim 4, wherein the instruction set includes at least one instruction from the instruction set, comprising: loading a temporary register from a memory location; loading a constant into a temporary register Storing a temporary register to a memory location; adding a first temporary register value to a second temporary register value, and storing the result in a third temporary register; from a second temporary register value Subtracting a first register value and storing the result in a third register; multiplying a first register value by a second register value, and storing the result to a third temporary And storing a second register value by a first register value and storing the result in a third register. The device of claim 4, wherein the first instruction set is read by an instruction register. 37 47. 200912642 4 8 The device of claim 4, wherein the first set is read before being placed in an instruction register, and the set is placed in an instruction temporary storage. The first register is replaced before the device. 49. A memory medium storing computer program instructions, wherein: causing: reading a first instruction set; reading a data bus; reading a temporary memory stored in at least one data register The first set of instructions, the data bus, and the register are analyzed and a first set of instructions is replaced with a second set of instructions, wherein the set of commands provides a result of the first instruction with a lower energy usage. 50. The memory medium of claim 49, wherein the low energy usage is measured by the overall energy of the operation. 51. The memory medium of claim 49, wherein the low energy usage is measured by a reduced bit transition. 5 2. The memory medium of claim 49, wherein an instruction set is replaced by a second instruction set before being placed in an instruction register before being placed in an instruction register. Instruction register. 5 3. A device for operating a power adapter, comprising: a component for reading a first instruction set; an index of a second finger command temporarily; a value; a second finger set of the same And the first 38 200912642 is configured to read a data bus; the component for reading the register value stored in the at least one data register; for analyzing the first a component of an instruction set, a data bus, and a register value; and means for replacing the first instruction set with a second set of instructions, wherein the second set of instructions provides the same with a lower energy usage The same result of an instruction set. 54. The apparatus of claim 5, wherein the lower energy usage is measured by the overall energy of the operation. 5 5. The apparatus of claim 5, wherein the lower energy usage is measured by a reduced bit transition. 39 39