TWI416711B - Memory structure and operating method thereof - Google Patents

Abstract

A memory structure including a substrate, a charge trapping layer, a block layer, a conducting layer and two doped regions is provided in the present invention. The charge trapping layer is disposed on the substrate. The block layer is disposed on the charge trapping layer. The conducting layer is disposed on the block layer. The doped regions are disposed respectively in the substrate on the two sides of the conducting layer.

Description

Memory structure and its operation method

The present invention relates to a memory structure, and more particularly to a charge trapping random access memory structure and method of operation thereof.

Due to the development of communication technology and the rise of the Internet, people have accelerated the demand for information exchange and processing, especially the demand for large-capacity audio and video data transmission and fast transmission speed. On the other hand, in the face of global competition, the working environment has surpassed the office environment, and may need to go to a certain place in the world at any time. At this time, a large amount of information is needed to support its actions and decisions. Therefore, portable digital devices, such as: digital notebook / NB, personal digital assistant / PDA, e-book / e-Book, mobile / Mobile Phone, digital camera / DSC and other "mobile platform", this The demand for portable digital devices has grown dramatically. The storage device for accessing the above digital products will also substantially increase the demand.

Since 1990, memory developed based on "semiconductor storage" has become an emerging technology for today's storage media. In order to cope with the increasing demand for memory, it will increase with the storage or transmission of a large amount of data, so it is of great significance and value to develop a new type of memory element.

In view of this, the object of the present invention is to provide a memory structure which can effectively reduce the volume of a memory cell and the complexity of a process.

Another object of the present invention is to provide a three-dimensional memory structure that can greatly increase the degree of integration of memory elements.

It is yet another object of the present invention to provide a method of operating a memory structure that has a faster staging and erasing speed.

It is still another object of the present invention to provide a method of operating a memory structure that has better retention time and reduces power consumption.

The invention provides a memory structure comprising a substrate, a charge trapping layer, a barrier layer, a conductor layer and two doped regions. The charge trapping layer is disposed on the substrate. The barrier layer is disposed on the charge trap layer. The conductor layer is disposed on the barrier layer. The doped regions are respectively disposed in the substrates on both sides of the conductor layer.

According to an embodiment of the invention, in the above memory structure, the substrate comprises a germanium substrate.

According to an embodiment of the invention, in the above memory structure, the germanium substrate comprises a single crystal germanium substrate or a polycrystalline germanium substrate.

According to an embodiment of the invention, in the memory structure described above, the material of the charge trap layer comprises a high dielectric constant capture material.

According to an embodiment of the invention, in the above memory structure, the material of the charge trap layer comprises tantalum nitride, aluminum oxide or hafnium oxide.

According to an embodiment of the invention, in the memory structure described above, the material of the barrier layer comprises a high dielectric constant barrier material.

According to an embodiment of the invention, in the above memory structure, the material of the barrier layer comprises ruthenium oxide, tantalum nitride, aluminum oxide or ruthenium oxide.

According to an embodiment of the invention, in the above memory structure, the material of the conductor layer comprises doped polysilicon or metal.

According to an embodiment of the present invention, in the memory structure, the memory structure is a dynamic random access memory (DRAM) or a static random access memory (SRAM). ).

The invention provides a three-dimensional memory structure comprising a substrate, a first isolation layer and a first memory structure. The first isolation layer is disposed on the substrate. The first memory structure includes a polysilicon substrate, a charge trapping layer, a barrier layer, a conductor layer, and two doped regions. The polysilicon substrate is disposed on the first isolation layer. The charge trapping layer is disposed on the polycrystalline germanium substrate. The barrier layer is disposed on the charge trap layer. The conductor layer is disposed on the barrier layer. The doped regions are respectively disposed in the polycrystalline germanium substrate on both sides of the conductor layer.

According to an embodiment of the present invention, in the above three-dimensional memory structure, a second isolation layer and a second memory structure are further included. The second isolation layer is disposed on the first memory structure. The second memory structure is disposed on the second isolation layer and has the same structure as the first memory structure.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the material of the second isolation layer comprises ruthenium oxide.

According to an embodiment of the present invention, in the above stereo memory structure, the second memory structure is a dynamic random access memory or a static random access memory.

According to an embodiment of the invention, in the above three-dimensional memory structure, the substrate comprises a germanium substrate.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the substrate has a semiconductor element.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the semiconductor element comprises a memory or a MOS transistor.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the material of the charge trap layer comprises a high dielectric constant capturing material.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the material of the charge trap layer includes tantalum nitride, aluminum oxide or tantalum oxide.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the material of the barrier layer comprises a high dielectric constant barrier material.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the material of the barrier layer comprises hafnium oxide, tantalum nitride, aluminum oxide or hafnium oxide.

According to an embodiment of the invention, in the above three-dimensional memory structure, the material of the conductor layer comprises doped polysilicon or metal.

According to an embodiment of the present invention, in the above three-dimensional memory structure, the material of the first isolation layer comprises ruthenium oxide.

According to an embodiment of the present invention, in the stereo memory structure, the first memory structure is a dynamic random access memory or a static random access memory.

The invention provides a method for operating a memory structure, wherein the memory structure comprises a substrate, a charge trapping layer, a barrier layer, a conductor layer and two doped regions, the charge trapping layer is disposed on the substrate, and the barrier layer is disposed on the charge trapping layer The conductor layer is disposed on the barrier layer, and the doped regions are respectively disposed in the substrate on both sides of the conductor layer. The method includes first applying a first voltage across the conductor layer. Next, a second voltage is applied to the substrate. Wherein, the voltage difference between the first voltage and the second voltage is sufficient to induce a Fowler-Nordheim tunneling effect such that the charge enters or is discharged from the charge trapping layer.

According to an embodiment of the invention, in the method of operating the memory structure, the first voltage is 8 volts to 20 volts and the second voltage is 0 volts.

According to an embodiment of the invention, in the method of operating the memory structure, the first voltage is -8 volts to -20 volts, and the second voltage is 0 volts.

According to an embodiment of the invention, in the method of operating the memory structure, the charge injection charge trapping layer is a stylized operation, and the discharging of the charge from the charge trapping layer is an erase operation.

The invention provides another method for operating a memory structure, wherein the memory structure comprises a substrate, a charge trapping layer, a barrier layer, a conductor layer and two doped regions, the charge trapping layer is disposed on the substrate, and the barrier layer is disposed on the charge trapping layer The conductor layer is disposed on the barrier layer, and the doped regions are respectively disposed in the substrate on both sides of the conductor layer. The method includes first performing a first stylization operation on the memory structure to cause charge to enter the charge trapping layer. Then, when the charge in the charge trap layer is lost, the memory structure is subjected to a reforming operation.

According to another embodiment of the present invention, in the above method of operating the memory structure, the reforming operation includes performing an erase operation on the memory structure. Next, a second stylization operation is performed on the memory structure.

According to another embodiment of the present invention, in the operating method of the memory structure, after performing the erasing operation, the reforming operation further includes performing a third collating step on the memory structure to confirm whether the erasing operation is performed. carry out. When the result of the third collation step is that the erase operation has been completed, a second stylization operation is performed. When the result of the third collation step is that the erase operation is not completed, the erase operation is continued.

According to another embodiment of the present invention, in the above method of operating the memory structure, the reforming operation includes performing a second stylized operation on the memory structure.

According to another embodiment of the present invention, in the operating method of the memory structure, after performing the first stylization operation, the method further includes performing a first verification step on the memory structure to confirm the first stylized operation. Whether it is completed. When the result of the first collation step is that the first stylized operation has been completed, the first stylized operation is ended. When the result of the first collation step is that the first stylization operation is not completed, the first stylization operation is continued.

According to another embodiment of the present invention, in the operating method of the memory structure, after the end of the first stylization operation, the method further includes performing a second collating step on the memory structure to confirm the Whether the charge is lost. When the result of the second collation step is that the charge in the charge trap layer has been lost, then a reforming operation is performed. When the result of the second collation step is that the charge in the charge trap layer is not lost, then the second collation step is continued.

Based on the above, since the memory structure proposed by the present invention is a MOS-like structure and does not require a capacitor, the volume of the memory cell, the complexity of the process, and the manufacturing cost can be reduced.

On the other hand, since the charge is stored in the charge trap layer of the memory structure, it has a better retention time, which can reduce the number of refresh operations, thereby reducing power consumption.

In addition, the three-dimensional memory structure proposed by the present invention can be formed on a substrate having other semiconductor elements, so that the degree of accumulation of the memory can be effectively improved.

In addition, the method of operating the memory structure proposed by the present invention has a faster stylization and erasing speed because no other film layer exists between the charge trapping layer of the memory structure and the substrate.

Furthermore, since the reforming operation is included in the operation method of the memory structure proposed by the present invention, data loss can be prevented, and if the checking step is added when the memory structure is operated, the stylization can be accurately grasped. The timing of the operation and erasing operations.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 is a cross-sectional view showing the structure of a memory according to an embodiment of the present invention.

Referring to FIG. 1 , the memory structure 100 includes a substrate 102 , a charge trap layer 104 , a barrier layer 106 , a conductor layer 108 , and a doped region 110 . The substrate 102 is, for example, a single crystal germanium substrate or a germanium substrate such as a polycrystalline germanium substrate. In addition, the substrate 102 is doped with the design of a visible memory by a person of ordinary skill in the art.

The charge trapping layer 104 is disposed on the substrate 102 to capture charges therein and is, for example, characterized by a low barrier height. The material of the charge trapping layer 104 is, for example, tantalum nitride, aluminum oxide or hafnium oxide or other high dielectric constant capturing material. Here, the definition of the high dielectric constant is higher than the dielectric constant of yttrium oxide (about 3.9). The method of forming the charge trap layer 104 is, for example, a chemical vapor deposition method.

The barrier layer 106 is disposed on the charge trap layer 104 to block the passage of charges. Barrier layer 106 is, for example, hafnium oxide, tantalum nitride, aluminum oxide, hafnium oxide or other high dielectric constant barrier material. The formation method of the barrier layer 106 is, for example, a chemical vapor deposition method.

The conductor layer 108 is disposed on the barrier layer 106 for use as a gate. The material of the conductor layer 108 is, for example, doped polysilicon or metal. The method of forming the conductor layer 108 is, for example, a chemical vapor deposition method or a physical vapor deposition method, and the method used depends on the material to be formed.

The doped regions 110 are disposed in the substrate 102 on both sides of the conductor layer 108 for use as a source/drain region. The method of forming the doping region 110 is, for example, an ion implantation method. The doping of the doped region 110 may be an n-type dopant such as phosphorus or a p-type dopant such as boron, which is adjusted by the general knowledge of the design of the visible memory. In general, the doped region 110 and the substrate 102 are of different doping types.

Since there is no other film layer between the charge trapping layer 104 of the memory structure 100 and the substrate 102, the speed of the staging operation and the erasing operation is relatively fast, up to 30 nanoseconds (ns) or less. However, the charge trapping layer 104 is slowly lost, so a reforming operation is required to prevent data loss. In this way, the memory structure 100 is made to have the characteristics of random access memory, and can be applied to a dynamic random access memory or a static random access memory. In addition, the memory structure 100 stores the electric charge in the charge trapping layer 104 and belongs to the charge trapping type memory. Therefore, the data storage time is long, and the number of reforming operations can be reduced, thereby reducing power consumption.

In the above, when the memory structure 100 of the present invention is applied to a dynamic random access memory, it is called a trapped DRAM (TDRAM); the memory structure 100 of the present invention is applied to In the case of static random access memory, it is called trapping SRAM (TSRAM).

As can be seen from the above embodiments, the structure of the memory structure 100 is relatively simple and has a structure similar to a MOS-like transistor. When the memory structure 100 is a TDRAM, the memory structure 100 does not require a capacitor compared to the conventional DRAM structure, and thus can reduce the volume of the memory cell, the complexity of the process, and the manufacturing cost.

2 is a cross-sectional view showing the structure of a three-dimensional memory according to an embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 simultaneously, the three-dimensional memory structure includes a substrate 200, a first isolation layer 202, and a first memory structure 204. The substrate 200 is, for example, a single crystal germanium substrate. A semiconductor component 206 is present in the dielectric layer 226 on the substrate 200. The semiconductor element 206 is, for example, a memory such as a DRAM, an SRAM or a TDRAM, or a MOS semi-electrode such as a CMOS, an NMOS or a CMOS.

In the present embodiment, the semiconductor device 206 illustrated in FIG. 2 is, for example, a TDRAM having the same structure as the memory structure 100 of FIG. 1 and is, for example, by a contact window 208 and dielectric in the dielectric layer 226. Conductor 210 on layer 226 operates to operate semiconductor component 206.

The first isolation layer 202 is disposed on the substrate 200 for isolating two semiconductor elements adjacent to each other. The material of the first isolation layer 202 is, for example, ruthenium oxide. The formation method of the first isolation layer 202 is, for example, a chemical vapor deposition method.

The first memory structure 204 is disposed on the first isolation layer 202, including the polysilicon substrate 212, the charge trapping layer 214, the barrier layer 216, the conductor layer 218, and the doping region 220, and is, for example, by contact in the dielectric layer 228. The wires 230 on the window 230 and the dielectric layer 228 operate the first memory structure 204. The first memory structure 204 can be TDRAM or TSRAM.

The polysilicon substrate 212 is disposed on the first isolation layer 202. The method of forming the polysilicon substrate 212 is, for example, a chemical vapor deposition method. In addition, the polycrystalline germanium substrate 212 is doped in the art by a person of ordinary skill in the art. In the first memory structure 204, except for defining the substrate as the polysilicon substrate 212, the remaining components are similar to the memory structure 100 of FIG. 1, and will not be described again.

In addition, the three-dimensional memory structure further includes a second isolation layer 222 and a second memory structure 224. The second isolation layer 222 is disposed on the first memory structure 204 for isolating two semiconductor elements adjacent to each other. The material of the second isolation layer 222 is, for example, ruthenium oxide. The method of forming the second isolation layer 222 is, for example, a chemical vapor deposition method.

The second memory structure 224 is disposed on the second isolation layer 222 and has the same structure as the first memory structure 204. The polysilicon substrate is also used as the substrate, and is, for example, the contact window 236 in the dielectric layer 234. A wire 238 on the dielectric layer 234 operates the second memory structure 224. The second memory structure 224 can be TDRAM or TSRAM.

As can be seen from the above embodiments, the three-dimensional memory structure is a memory structure (such as the first memory structure 204 and the second memory structure 224) using a polycrystalline germanium substrate as a substrate, and is stacked on the substrate 200, and utilizes, for example, a first isolation layer. The isolation layer of the second isolation layer 222 isolates the two adjacent semiconductor elements to form a three-dimensional memory structure, which can effectively improve the memory accumulation.

Although in this embodiment, two memory structures (such as the first memory structure 204 and the second memory structure 224) using a polycrystalline germanium substrate as a substrate are stacked on the substrate 200, the technical field has Generally, the knowledgeer can adjust the number of stacked memory structures using the polycrystalline substrate as a substrate.

Hereinafter, the operation method of the memory structure of the present invention will be described by taking the memory structure 100 of FIG. 1 as an example.

FIG. 3 is a flow chart showing a method of operating a memory structure according to an embodiment of the invention.

First, referring to FIG. 1 and FIG. 3 simultaneously, step S100 is performed to apply a first voltage to the conductor layer 108. Next, in step S102, a second voltage is applied to the substrate 102. Wherein, the voltage difference between the first voltage and the second voltage is sufficient to induce an F-N tunneling effect such that the charge enters or is discharged from the charge trap layer 104. The charge is, for example, an electron or a hole.

Here, the electron injection charge trap layer 104 is defined as a stylization operation, and the electrons are discharged from the charge trap layer 104 as an erase operation to explain the present embodiment, but the above definitions of the program operation and the erase operation are not used. In order to limit the invention, those skilled in the art can define it according to requirements.

In the above, when the memory structure 100 is programmed, the first voltage applied to the conductor layer 108 is, for example, 8 volts to 20 volts, and the second voltage applied to the substrate 102 is, for example, 0 volts. To induce an F-N tunneling effect, electrons enter the charge trapping layer 104. On the other hand, when erasing the memory structure 100, the first voltage applied to the conductor layer 108 is, for example, -8 volts to -20 volts, and the second voltage applied to the substrate 102 is, for example, 0 volts to induce an F-N tunneling effect such that electrons are discharged from the charge trapping layer 104.

Since there is no other film barrier between the charge trapping layer 104 of the memory structure 100 and the substrate 102, the memory structure 100 performs a program operation and an erase operation at a relatively fast speed of up to 30 nanoseconds.

However, the charge stored in the charge trapping layer of the memory structure proposed by the present invention is slowly lost, so that when the memory structure is operated, it must be continuously charged to perform the data reforming operation. Hereinafter, an operation method of performing a reforming operation on the memory structure of the present invention will be described.

FIG. 4 is a flow chart showing a reforming operation of the memory structure according to the first embodiment of the present invention.

First, referring to FIG. 4, step S200 is performed to perform a first stylization operation on the memory structure to cause charges to enter the charge trap layer. The memory structure that is operated is, for example, the memory structure 100 of FIG.

Next, step S202 is performed to perform a reforming operation on the memory structure when the charge in the charge trap layer is lost. The performing the reorganization operation includes: performing step S204 to perform an erase operation on the memory structure. Thereafter, step S206 is performed to perform a second stylization operation on the memory structure.

FIG. 5 is a flow chart showing a reforming operation of the memory structure according to the second embodiment of the present invention.

First, referring to FIG. 5, step S300 is performed to perform a first stylization operation on the memory structure to cause charges to enter the charge trapping layer. The memory structure that is operated is, for example, the memory structure 100 of FIG.

Next, step S302 is performed to perform a reforming operation on the memory structure when the charge in the charge trap layer is lost. Among them, the reforming operation performed is, for example, a second stylized operation.

FIG. 6 is a flow chart showing a reforming operation of the memory structure according to the third embodiment of the present invention.

First, referring to FIG. 6, step S400 is performed to perform a first stylization operation on the memory structure to cause charges to enter the charge trap layer. The memory structure that is operated is, for example, the memory structure 100 of FIG.

Then, step S402 is selectively performed to perform a first collating step on the memory structure to confirm whether the first stylized operation is completed. When the result of the first collating step is that the first stylized operation has been completed, the A stylized operation; when the result of the first collation step is that the first stylized operation is not completed, then returning to step S400, the first stylized operation is continued.

Then, after the end of the first stylization operation, step S404 may be selectively performed to perform a second collation step on the memory structure to confirm whether the charge in the charge trap layer is lost, and the result of the second collation step is charge trapping. When the charge in the layer has been lost, the process proceeds to step S406 to perform a reforming operation; when the result of the second collation step is that the charge in the charge trap layer is not lost, the process returns to step S404 to continue the second collation step.

Next, step S406 is performed to perform a reforming operation on the memory structure when the charge in the charge trap layer is lost. The performing the reorganization operation includes: first, performing step S408 to perform an erase operation on the memory structure.

Then, step S410 is selectively performed to perform a third collation step on the memory structure to confirm whether the erasing operation is completed. When the result of the third collating step is that the erasing operation has been completed, the process proceeds to step S412. The second stylization operation; when the result of the third collation step is an unfinished erase operation, the process returns to step S408 to continue the erase operation.

Then, in step S412, a second stylization operation is performed on the memory structure.

FIG. 7 is a flow chart showing a reforming operation of the memory structure according to the fourth embodiment of the present invention.

First, referring to FIG. 7, step S500 is performed to perform a first stylization operation on the memory structure to cause charges to enter the charge trap layer. The memory structure that is operated is, for example, the memory structure 100 of FIG.

Then, step S502 is selectively performed to perform a first verification step on the memory structure to confirm whether the first stylization operation is completed. When the result of the first verification step is that the first stylized operation has been completed, the A stylized operation; when the result of the first collation step is that the first stylized operation is not completed, then returning to step S500, the first stylized operation is continued.

Then, after the end of the first stylization operation, step S504 may be selectively performed to perform a second collation step on the memory structure to confirm whether the charge in the charge trap layer is lost, and the result of the second collation step is charge trapping. When the charge in the layer has been lost, the process proceeds to step S506 to perform a reforming operation. When the result of the second collation step is that the charge in the charge trap layer is not lost, the process returns to step S504 to continue the second collation step.

Next, step S506 is performed to perform a reforming operation on the memory structure when the charge in the charge trap layer is lost. Among them, the reforming operation performed is, for example, a second stylized operation.

It should be noted that the embodiments described in FIG. 4 and FIG. 5 are basic implementations of the reforming operation of the memory structure of the present invention, and the embodiments introduced in FIGS. 6 and 7 are respectively illustrated. 4 and the embodiment described in Figure 5 are added to the collation step, and these collation steps are selectively performed. That is, those skilled in the art can add the required verification steps according to actual needs in the basic implementations described in FIG. 4 and FIG. 5. Therefore, the memory structure of the present invention is reformed. It is not limited to the embodiment described in FIGS. 4 to 7.

Based on the above, since the reforming operation is included in the operation method of the memory structure proposed by the present invention, the loss of data from the charge trapping layer can be avoided. In addition, if the checking step is added when the memory structure is operated, the timing of the stylized operation and the erasing operation can be accurately grasped.

In summary, the present invention has at least the following advantages: 1. The memory structure proposed by the present invention can reduce the volume of the memory cell, the complexity of the process, and the manufacturing cost.

2. Since the memory structure proposed by the present invention has better data retention time, the number of reforming operations can be reduced, and power consumption can be reduced.

3. The stereo memory structure proposed by the present invention can effectively improve the memory accumulation.

4. The method of operation of the memory structure proposed by the present invention can be programmed and erased at a relatively fast speed.

5. In the method of operation of the memory structure proposed by the present invention, a reforming operation is included, thereby preventing data loss.

6. The operation method of the memory structure proposed by the present invention can accurately grasp the timing of the stylized operation and the erase operation.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Memory structure

102, 200. . . Base

104, 214. . . Charge trapping layer

106,216. . . Barrier layer

108, 218. . . Conductor layer

110, 220. . . Doped region

202. . . First isolation layer

204. . . First memory structure

206. . . Semiconductor component

208, 230, 236. . . Contact window

210, 232, 238. . . wire

212. . . Polycrystalline germanium substrate

222. . . Second isolation layer

224. . . Second memory structure

226, 228, 234. . . Dielectric layer

S100, S102, S200, S202, S204, S206, S300, S302, S400, S402, S404, S406, S408, S410, S412, S500, S502, S504, S506. . . Step label

1 is a cross-sectional view showing the structure of a memory according to an embodiment of the present invention.

2 is a cross-sectional view showing the structure of a three-dimensional memory according to an embodiment of the present invention.

FIG. 3 is a flow chart showing a method of operating a memory structure according to an embodiment of the invention.

FIG. 4 is a flow chart showing a reforming operation of the memory structure according to the first embodiment of the present invention.

FIG. 5 is a flow chart showing a reforming operation of the memory structure according to the second embodiment of the present invention.

FIG. 6 is a flow chart showing a reforming operation of the memory structure according to the third embodiment of the present invention.

FIG. 7 is a flow chart showing a reforming operation of the memory structure according to the fourth embodiment of the present invention.

100. . . Memory structure

102. . . Base

104. . . Charge trapping layer

106. . . Barrier layer

108. . . Conductor layer

110. . . Doped region

Claims (43)

A memory structure comprising: a substrate; a charge trapping layer disposed directly on the substrate; a barrier layer disposed on the charge trapping layer; a conductor layer disposed on the barrier layer; and a doped region , respectively disposed in the substrate on both sides of the conductor layer. The memory structure of claim 1, wherein the substrate comprises a substrate. The memory structure of claim 1, wherein the germanium substrate comprises a single crystal germanium substrate or a polycrystalline germanium substrate. The memory structure of claim 1, wherein the material of the charge trap layer comprises a high dielectric constant capture material. The memory structure of claim 1, wherein the material of the charge trap layer comprises tantalum nitride, aluminum oxide or cerium oxide. The memory structure of claim 1, wherein the material of the barrier layer comprises a high dielectric constant barrier material. The memory structure of claim 1, wherein the material of the barrier layer comprises cerium oxide, cerium nitride, aluminum oxide or cerium oxide. The memory structure of claim 1, wherein the material of the conductor layer comprises doped polysilicon or metal. The memory structure of claim 1, wherein the memory structure is a dynamic random access memory or a static random access memory. A three-dimensional memory structure includes: a substrate; a first isolation layer disposed on the substrate; and a first memory structure including: a polysilicon substrate disposed on the first isolation layer; a charge trapping layer Directly disposed on the polysilicon substrate; a barrier layer disposed on the charge trap layer; a conductor layer disposed on the barrier layer; and two doped regions respectively disposed on the polysilicon substrate on both sides of the conductor layer in. The three-dimensional memory structure of claim 10, further comprising: a second isolation layer disposed on the first memory structure; and a second memory structure disposed on the second isolation layer And having the same structure as the first memory structure. The three-dimensional memory structure of claim 11, wherein the material of the second isolation layer comprises ruthenium oxide. The three-dimensional memory structure of claim 11, wherein the second memory structure is a dynamic random access memory or a static random access memory. The three-dimensional memory structure of claim 10, wherein the substrate comprises a germanium substrate. The three-dimensional memory structure of claim 10, wherein the substrate has a semiconductor component thereon. The three-dimensional memory structure of claim 15, wherein the semiconductor component comprises a memory or a MOS transistor. The three-dimensional memory structure of claim 10, wherein the material of the charge trapping layer comprises a high dielectric constant capturing material. The three-dimensional memory structure of claim 10, wherein the material of the charge trapping layer comprises tantalum nitride, aluminum oxide or cerium oxide. The three-dimensional memory structure of claim 10, wherein the material of the barrier layer comprises a high dielectric constant barrier material. The three-dimensional memory structure of claim 10, wherein the material of the barrier layer comprises ruthenium oxide, tantalum nitride, aluminum oxide or ruthenium oxide. The three-dimensional memory structure of claim 10, wherein the material of the conductor layer comprises doped polysilicon or metal. The three-dimensional memory structure of claim 10, wherein the material of the first isolation layer comprises ruthenium oxide. The three-dimensional memory structure of claim 10, wherein the first memory structure is a dynamic random access memory or a static random access memory. A method of operating a memory structure, wherein the memory structure comprises a substrate, a charge trapping layer, a barrier layer, a conductor layer and two doped regions, the charge trapping layer being directly disposed on the substrate, the barrier layer configuration On the charge trapping layer, the conductive layer is disposed on the barrier layer, and the doped regions are respectively disposed in the substrate on both sides of the conductive layer, the method comprising: applying a first voltage on the conductive layer; as well as A second voltage is applied to the substrate, wherein a voltage difference between the first voltage and the second voltage is sufficient to induce an F-N tunneling effect such that charge enters or is discharged from the charge trapping layer. The method of operating a memory structure according to claim 24, wherein the first voltage is 8 volts to 20 volts and the second voltage is 0 volts. The method of operating a memory structure according to claim 24, wherein the first voltage is -8 volts to -20 volts and the second voltage is 0 volts. The method of operating a memory structure according to claim 24, wherein the charge injection into the charge trap layer is a stylization operation, and discharging the charge from the charge trap layer is an erase operation. A method of operating a memory structure, wherein the memory structure comprises a substrate, a charge trapping layer, a barrier layer, a conductor layer and two doped regions, the charge trapping layer being directly disposed on the substrate, the barrier layer configuration On the charge trapping layer, the conductor layer is disposed on the barrier layer, and the doped regions are respectively disposed in the substrate on both sides of the conductor layer, the method comprising: performing a first stylization on the memory structure Operating to cause charge to enter the charge trapping layer; and performing a reforming operation on the memory structure when the charge in the charge trapping layer is lost. The method of operating a memory structure according to claim 28, wherein the reforming operation comprises: performing an erase operation on the memory structure; and performing a second stylization operation on the memory structure. The method of operating a memory structure according to claim 29, wherein after performing the erasing operation, the reforming operation further comprises performing a third collating step on the memory structure to confirm the erasing operation. Whether it is completed, when the result of the third verification step is that the erasing operation is completed, the second stylization operation is performed, and when the result of the third verification step is that the erasing operation is not completed, the Erase operation. The method of operating a memory structure according to claim 28, wherein the reforming operation comprises performing a second stylization operation on the memory structure. The method for operating a memory structure according to claim 28, wherein after performing the first stylization operation, further comprising performing a first verification step on the memory structure to confirm the first stylized operation Is it completed, when the result of the first collating step is that the first stylized operation has been completed, the first stylized operation is ended, when the result of the first collating step is that the first stylized operation is not completed, Then continue the first stylization operation. The method for operating a memory structure according to claim 32, wherein after the end of the first stylization operation, further comprising performing a second collating step on the memory structure to confirm the charge trapping layer Whether the charge is lost. When the result of the second collation step is that the charge in the charge trap layer has been lost, the reforming operation is performed, when the result of the second collation step is that the charge in the charge trap layer is not lost. Then proceed to the second verification step. The method of operating a memory structure according to claim 33, wherein the reforming operation comprises: performing an erase operation on the memory structure; and performing a second stylization operation on the memory structure. The method of operating a memory structure according to claim 34, wherein after performing the erasing operation, the reforming operation further comprises performing a third collating step on the memory structure to confirm the erasing operation. Whether it is completed, when the result of the third verification step is that the erasing operation is completed, the second stylization operation is performed, and when the result of the third verification step is that the erasing operation is not completed, the Erase operation. The method of operating a memory structure according to claim 33, wherein the reforming operation comprises performing a second stylization operation on the memory structure. The method of operating a memory structure as described in claim 32, wherein the reforming operation comprises: performing an erase operation on the memory structure; and performing a second stylization operation on the memory structure. The method for operating a memory structure according to claim 37, wherein after performing the erasing operation, the reforming operation further comprises performing a third collating step on the memory structure to confirm the erasing operation. Whether it is completed, when the result of the third verification step is that the erasing operation is completed, the second stylization operation is performed, and when the result of the third verification step is that the erasing operation is not completed, the Erase operation. The method of operating a memory structure according to claim 32, wherein the reforming operation comprises performing a second stylization operation on the memory structure. The method for operating a memory structure according to claim 28, wherein after the end of the first stylization operation, further comprising performing a second collating step on the memory structure to confirm the charge trapping layer Whether the charge is lost. When the result of the second collation step is that the charge in the charge trap layer has been lost, the reforming operation is performed, when the result of the second collation step is that the charge in the charge trap layer is not lost. Then proceed to the second verification step. The method of operating a memory structure according to claim 40, wherein the reforming operation comprises: performing an erase operation on the memory structure; and performing a second stylization operation on the memory structure. The method for operating a memory structure according to claim 41, wherein after performing the erasing operation, the reforming operation further comprises performing a third collating step on the memory structure to confirm the erasing operation. Whether it is completed, when the result of the third verification step is that the erasing operation is completed, the second stylization operation is performed, and when the result of the third verification step is that the erasing operation is not completed, the Erase operation. The method of operating a memory structure according to claim 40, wherein the reforming operation comprises performing a second stylizing operation on the memory structure.