KR20100059543A - Non-nolatile memory device, method of fabrication the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to reduce the amount of etching during the process such as forming spacer or contact area by removing a lower structure such as tunneling layer in advance. CONSTITUTION: A memory cell and selection transistors are formed on a substrate(1200). A peripheral transistor is formed(1210). A blocking layer, a electron storing layer, and a tunneling layer between the selection transistors are etched respectively(1220). Accordingly, a spacer is installed(1230).

Description

Non-volatile memory device and method of manufacturing the non-volatile memory device {Non-nolatile memory device, method of fabrication the same}

The present invention relates to a nonvolatile memory device and a method of manufacturing the nonvolatile memory device.

Semiconductor memory devices that store data may be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Representative examples of volatile memory devices include DRAM (Dynamic Random Access Memory) and SRAM (Static RAM). Examples of nonvolatile memory devices include EEPROM, flash memory, and PRAM.

The flash memory device includes a memory cell transistor for storing and erasing data, and a peripheral circuit for driving the memory cell transistor. The source and drain of the memory cell transistor are connected to a common source line (CSL) contact and a direct contact (DC) contact, respectively.

SUMMARY OF THE INVENTION Problems to be Solved by the Invention The present invention provides a nonvolatile memory device and a nonvolatile memory capable of reducing substrate loss in source and drain regions of transistors in a peripheral circuit region during formation of a spacer and etching of a contact region. It is to provide a method for manufacturing a device.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, wherein a plurality of memory cells having a stacked structure of a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a metal layer are respectively selected from a cell region of a substrate. Forming transistors; Forming a plurality of peripheral transistors having a stacked structure of a gate oxide film, polysilicon, and a metal layer in the peripheral circuit region of the substrate; Etching the blocking insulating layer between two adjacent ones of the selection transistors; And depositing a spacer on top of the memory cells, the selection transistors, and the peripheral transistors.

The method may further include etching a spacer deposited between the two adjacent selection transistors and a portion of the spacer deposited in the source region and the drain region of the peripheral transistors. And depositing a capping layer over the memory cells, the select transistors and the peripheral transistors, and etching the blocking insulating layer comprises: the capping layer and the blocking insulation between two adjacent select transistors. The layer can be etched.

The method may further include forming contact regions by etching the predetermined region between the two adjacent selection transistors and the source region and the drain region of the peripheral transistors. The contact region formed in a predetermined region between the two adjacent selection transistors may be a direct contact (DC) contact, and the contact regions formed in the source region and the drain region of the peripheral transistors may be metal contacts.

Etching the blocking insulating layer may further include etching the charge storage layer between the two adjacent selection transistors. Etching the blocking insulating layer may further include etching the tunneling insulating layer between the two adjacent selection transistors.

In addition, the nonvolatile memory device according to the present invention is formed in the cell region on the substrate, each of the memory cells and the selection transistor having a stacked structure of a tunneling insulating layer, a charge storage layer, a blocking insulating layer and a metal layer; And peripheral transistors formed in the peripheral circuit region on the substrate, the peripheral transistors having a stacked structure of a gate insulating layer, a polysilicon layer, and a metal layer, wherein a region between two adjacent selection transistors of the selection transistors is formed by the blocking insulating layer. It can be etched.

The charge storage layer may be further etched in an area between two adjacent selection transistors among the selection transistors. The tunnel insulating layer may be further etched in an area between two adjacent selection transistors among the selection transistors.

According to the present invention, the formation of a spacer is performed by removing, in advance, the underlying structure such as a blocking insulating layer, a charge storage layer and a tunneling insulating layer between two adjacent selection transistors of the selection transistors of the nonvolatile memory device before deposition of the spacer. The etching amount can be reduced in subsequent processes, such as the formation of contact regions. Therefore, since the substrate loss of the source region and the drain region of the peripheral circuit region can be reduced, the performance of the transistors of the peripheral circuit region can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity of description.

Throughout the specification, when referring to one component, such as a film, region, or substrate, being located on, “connected”, or “coupled” to another component, the one component is directly It may be interpreted that there may be other components "on", "connected", or "coupled" in contact with, or interposed therebetween. On the other hand, when one component is said to be located on another component "directly on", "directly connected", or "directly coupled", it is interpreted that there are no other components intervening therebetween. do. Like numbers refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers, and / or parts, these members, parts, regions, layers, and / or parts are defined by these terms. It is obvious that not. These terms are only used to distinguish one member, part, region, layer or portion from another region, layer or portion. Thus, the first member, part, region, layer or portion, which will be discussed below, may refer to the second member, component, region, layer or portion without departing from the teachings of the present invention.

Also, relative terms such as "top" or "above" and "bottom" or "bottom" may be used herein to describe the relationship of certain elements to other elements as illustrated in the figures. It may be understood that relative terms are intended to include other directions of the device in addition to the direction depicted in the figures. For example, if the device is turned over in the figures, elements depicted as present on the face of the top of the other elements are oriented on the face of the bottom of the other elements. Thus, the exemplary term "top" may include both "bottom" and "top" directions depending on the particular direction of the figure. If the device faces in the other direction (rotated 90 degrees relative to the other direction), the relative descriptions used herein can be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. Also, as used herein, "comprise" and / or "comprising" specifies the presence of the mentioned shapes, numbers, steps, actions, members, elements and / or groups of these. It is not intended to exclude the presence or the addition of one or more other shapes, numbers, acts, members, elements and / or groups.

1 to 4 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, the substrate 100 is divided into a cell region A and a peripheral circuit region by an isolation layer. In the cell region A, memory cells MC and selection transistors ST are formed, and the peripheral region is formed. In the circuit region, peripheral circuits for driving the memory cells MC are formed. The peripheral circuit region is divided into a region B in which a low voltage element is formed and a region C in which a high voltage element is formed.

The tunneling insulating layer 110, the charge storage layer 120, and the blocking insulating layer 130 are sequentially deposited in the cell region A of the substrate 100. Subsequently, a metal layer 140 for forming gates of the memory cells MC and the selection transistors ST is stacked in the cell region A. As a result, the gates of the memory cells MC and the selection transistors ST have a stacked structure of the tunneling insulating layer 110, the charge storage layer 120, the blocking insulating layer 130, and the metal layer 140. In addition, the source and drain regions of the memory cells MC and the selection transistors ST may include a tunneling insulating layer 110, a charge storage layer 120, and a blocking insulating layer 130. In this case, the gate may be formed by a general photo process and a dry etching process, and thus a detailed description thereof will be omitted.

The tunneling insulating layer 110 may be formed of, for example, a silicon oxide film, and may be formed to a thickness of about 20 to about 70 microseconds. The charge storage layer 120 may be formed of a silicon nitride film or a high dielectric film having a higher dielectric constant. For example, the charge storage layer 120 may be formed of a Si 3 N 4 film, a metal oxide film, a metal nitride film, or a combination thereof, and may be formed to a thickness of about 40 to about 120 μs. Here, the charge storage layer 120 includes a trap site for storing charge passing through the tunneling insulating layer 110. Here, the charge storage layer 120 may be referred to as a floating gate.

The blocking insulating layer 130 blocks electrons from escaping to the metal layer 140 while being trapped at the trap site of the charge storage layer 120, and the charge of the metal layer 140 is injected into the charge storage layer 120. It blocks the work. When the charge storage layer 120 is nitride, the tunneling insulation layer 110, the charge storage layer 120, and the blocking insulation layer 130 may have an oxide-nitride-oxide (ONO) structure. The metal layer 140 may be made of at least one material selected from the group consisting of TaN, TiN, W, WN, HfN, and tungsten silicide. The metal layer 140 is connected to the corresponding word line to apply a program voltage, and the drain is connected to the corresponding bit line.

Meanwhile, a gate oxide film 150 is deposited in the peripheral circuit regions B and C of the substrate 100, and then a polysilicon layer 160 and a metal layer 170 are formed to form gates of the peripheral transistors. At this time, the thickness of the gate oxide film in the region C in which the high voltage element is formed is thicker than the thickness of the gate oxide film in the region B in which the low voltage element is formed. Thus, the gates of the peripheral transistors have a stacked structure of the gate oxide film 150, the polysilicon layer 160, and the metal layer 170, and the source and drain regions of the peripheral transistors include the gate oxide film 150. In this case, the gate may be formed by a general photo process and a dry etching process, and thus a detailed description thereof will be omitted.

Referring to FIG. 2, a photoresist 180 is applied to open only a region between two adjacent selection transistors.

Referring to FIG. 3, an etching process (for example, a dry etching process) is performed on the semiconductor device 10, so that a blocking insulating layer 130 formed in an area between two adjacent selection transistors ST and charge storage The layer 120 and the tunneling insulating layer 110 are removed. In another embodiment of the present invention, only the blocking insulating layer 130 and the charge storage layer 120 formed in the region between two adjacent select transistors ST may be removed. In another exemplary embodiment, only the blocking insulating layer 130 formed in the region between two adjacent selection transistors ST may be removed.

Referring to FIG. 4, a spacer 190 is deposited on the semiconductor device 10. Subsequently, an etching process is performed on the spacer 190 deposited on the source region and the drain region of the peripheral transistors of the peripheral circuit regions B and C and the region between two adjacent selection transistors ST.

In a conventional semiconductor device, a region between two adjacent selection transistors has a stacking structure of a blocking insulating layer, a charge storage layer, and a tunneling insulating layer. An etching process is performed between forming two spacers to form a spacer structure. The blocking insulating layer, the charge storage layer, and the tunneling insulating layer of the drain contact region and the common source line region of are removed. In this case, since the source region and the drain region of the peripheral transistors include only the gate oxide layer, the thickness is thinner than the region between two adjacent selection transistors. However, since the same etching process is performed on the cell region and the peripheral circuit region during the formation of the spacer, the substrate and the source region and the drain region of the peripheral transistors are lost. In particular, since the source oxide and the drain region of the transistor of the low voltage device region have a thinner thickness of the gate oxide film, the loss of the substrate may increase, resulting in a problem of deterioration of the short channel effect.

However, according to the present exemplary embodiment, since the blocking insulating layer 130, the charge storage layer 120, and the tunneling insulating layer 110 are already removed, the area between the two adjacent selection transistors ST is removed. In the process of forming 190, the amount of etching is reduced compared to the prior art. This also reduces the loss of the substrate in the source and drain regions of the peripheral transistors. In other words, the center portion of the region between two adjacent selection transistors ST is removed so that the spacer 190 is exposed so that the substrate 100 is exposed, but the source region of the transistors of the low voltage region B and the high voltage region C. And the drain region is reduced the loss of the substrate 100.

5 to 8 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 5, the substrate 200 is divided into a cell region A ′ and a peripheral circuit region by an isolation layer. In the cell region A ′, memory cells MC and selection transistors ST are formed. In the peripheral circuit region, a peripheral circuit for driving the memory cells MC is formed. The peripheral circuit region is divided into a region B 'on which a low voltage element is formed and a region C' on which a high voltage element is formed.

The tunneling insulating layer 210, the charge storage layer 220, and the blocking insulating layer 230 are sequentially deposited in the cell region A ′ of the substrate 200. Subsequently, a metal layer 240 for forming gates of the memory cells MC and the selection transistors ST is stacked in the cell region A '. Meanwhile, a gate oxide film 250 is deposited in the peripheral circuit regions B ′ and C ′ of the substrate 200, and then a polysilicon layer 260 and a metal layer 270 for forming gates of the peripheral transistors are stacked. do. At this time, the thickness of the gate oxide film in the region C 'in which the high voltage element is formed is thicker than the thickness of the gate oxide film in the region B' in which the low voltage element is formed. Subsequently, a capping film 275 is deposited on the semiconductor device 20. Each element included in the semiconductor device 20 corresponds to the contents described above with reference to FIG. 1, and thus a detailed description thereof will be omitted.

Referring to FIG. 6, a photoresist 280 is applied to open only a region between two adjacent select transistors.

Referring to FIG. 7, an etching process is performed on the semiconductor device 20 to form a capping layer 275, a blocking insulating layer 230, and a charge storage layer 220 formed in a region between two adjacent selection transistors ST. ) And the tunneling insulating layer 210 is removed. In another exemplary embodiment, only the capping layer 275, the blocking insulating layer 230, and the charge storage layer 220 formed in a region between two adjacent selection transistors ST may be removed. In another embodiment, only the capping layer 275 and the blocking insulating layer 230 formed in the region between two adjacent selection transistors ST may be removed. In another embodiment of the present invention, only the capping layer 275 formed in the region between two adjacent select transistors ST may be removed.

Referring to FIG. 8, a spacer 290 is deposited on the semiconductor device 20. Subsequently, an etching process is performed on the spacer 190 deposited on the source region and the drain region of the peripheral transistors in the region between two adjacent selection transistors ST and the peripheral circuit regions B 'and C'. .

According to the present exemplary embodiment, a region between two adjacent selection transistors ST is already removed from the capping layer 275, the blocking insulating layer 230, the charge storage layer 220, and the tunneling insulating layer 210. Therefore, the etching amount in the process of forming the spacer 290 is reduced compared to the conventional. This also reduces the loss of the substrate in the source and drain regions of the peripheral transistors. In other words, the center portion of the region between two adjacent selection transistors ST is removed so that the spacer 290 is exposed to expose the substrate 200, but the transistors of the low voltage region B 'and the high voltage region C' are removed. The source region and the drain region reduce the loss of the substrate 200.

9 to 11 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

Referring to FIG. 9, the semiconductor device 30 is a subsequent process performed on the semiconductor device illustrated in FIG. 4 or 8, and the first and second insulating layers are performed on the semiconductor device illustrated in FIG. 4 or 8. (383, 386) are laminated.

In more detail, the substrate 300 is divided into a cell region A ″ and a peripheral circuit region by an isolation layer. In the cell region A ″, memory cells MC and selection transistors ST are formed. A peripheral circuit for driving the memory cells MC is formed in the peripheral circuit area. The peripheral circuit region is divided into a region B ″ in which a low voltage element is formed and a region C ″ in which a high voltage element is formed.

The tunneling insulating layer 310, the charge storage layer 320, and the blocking insulating layer 330 are sequentially deposited in the cell region A ″ of the substrate 300. Then, the memory cell (A ″) is deposited in the cell region A ″. Metal layers 340 for forming gates of the MCs and the selection transistors ST are stacked. Meanwhile, a gate oxide film 350 is deposited in the peripheral circuit regions B ″ and C ″ of the substrate 300, and then a polysilicon layer 360 and a metal layer 370 for forming gates of the peripheral transistors are stacked. do. At this time, the thickness of the gate oxide film in the region C ″ in which the high voltage element is formed is thicker than the thickness of the gate oxide film in the region B ″ in which the low voltage element is formed. Subsequently, a spacer 380 is formed in the semiconductor device 30, and the first and second insulating layers 383 and 386 are sequentially stacked on the semiconductor device 30. The region between two adjacent selection transistors may include only the substrate 300 by removing the tunneling insulating layer 310, the charge storage layer 320, and the blocking insulating layer 330. Each element included in the semiconductor device 30 corresponds to the contents described above with reference to FIG. 1, and thus a detailed description thereof will be omitted.

Referring to FIG. 10, a region between two adjacent select transistors of a cell region A ″, a source region and a drain region of the low voltage element region B ″, a source region and a drain region of the high voltage element region C ″. The photoresist 390 is applied to open only the bay, wherein the region between two adjacent select transistors of the cell region A ″ is the region where the DC contact is to be formed, and the low voltage element region B ″. The source region and the drain region, the source region and the drain region of the high voltage device region C ″ are regions in which a metal contact (MC) contact is to be formed.

The region where the DC contact is to be formed in the cell region A ″ has a stacked structure of a substrate 300, first and second insulating layers 383 and 386, and both ends of the substrate 300 and a spacer. 380 and the first and second insulating layers 383 and 386. In the low voltage device region B ″, the region where the MC contact is to be formed is formed of the substrate 300, the spacer 380, The stacked structure of the first and second insulating layers 383 and 386, and the region where the MC contact is to be formed in the high voltage device region C ″ is formed of the substrate 300, the gate oxide film 350, the spacer 380, and the first region. And a stacked structure of the second insulating layers 383 and 386. In other words, the stacked structure of the region where the DC contact is to be formed in the cell region A ″ and the MC contact in the peripheral circuit region B ″ and C ″ are formed. The stacked structure of the regions to be formed is the same.

Referring to FIG. 11, a dry etching process is performed on the semiconductor device 30 to form the DC contact 391 and the MC contacts 392, 393, 394, and 395.

According to the present exemplary embodiment, since the blocking insulating layer 230, the charge storage layer 220, and the tunneling insulating layer 210 are already removed, the dry etching amount is known in the process of forming the DC contact. Is reduced compared to. This also reduces the loss of the substrate 300 in the region where the MC contact in the peripheral circuit region is to be formed.

12 is a flowchart illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 12, in operation 1200, a plurality of memory cells and a plurality of select transistors having a stacked structure of a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a metal layer are respectively formed in a cell region of a substrate.

In operation 1210, a plurality of peripheral transistors having a stacked structure of a gate oxide film, polysilicon, and a metal layer are formed in the peripheral circuit region of the substrate.

In operation 1220, the blocking insulating layer between two adjacent select transistors of the select transistors is etched.

In operation 1230, a spacer is deposited on the memory cells, the selection transistors, and the peripheral transistors.

An embodiment of the present invention further includes etching a spacer deposited between the two adjacent selection transistors and a portion of the spacer deposited in the source region and the drain region of the peripheral transistors.

13 is a schematic diagram showing a card according to an embodiment of the present invention.

Referring to FIG. 13, the card 1300 may be arranged to exchange electrical signals with the controller 1310 and the memory 1320. For example, when a command is issued from the controller 1310, the memory 1320 may transmit data. The memory 1320 may include the nonvolatile memory device of FIG. 4, 8, or 11. The card 1300 may be a variety of cards, for example a memory stick card (memory stick card), smart media card (SM), secure digital (SD), mini secure digital card (mini) memory device such as a secure digital card (mini SD) or a multi media card (MMC).

14 is a schematic diagram illustrating a system according to an embodiment of the present invention.

Referring to FIG. 14, the processor 1410, the input / output device 1420, and the memory 1430 included in the system 1400 may perform data communication with each other using a bus 1440. The processor 1410 may execute a program and control the system 1400. The input / output device 1420 may be used to input or output data of the system 1400. The system 1400 may be connected to an external device, such as a personal computer or a network, using the input / output device 1420 to exchange data with the external device. The memory 1440 may include the nonvolatile memory device of FIG. 4, 8, or 11. For example, the memory 1430 may store code and data for the operation of the processor 1410. For example, such a system 1400 may be a mobile phone, MP3 player, navigation, portable multimedia player (PMP), solid state disk (SSD) or consumer electronics ( household appliances).

The invention described above can also be embodied as computer readable code on a computer readable storage medium. Computer-readable storage media includes all types of storage devices on which data readable by a computer system is stored. Examples of computer-readable storage media include ROM, RAM, CD-ROM, DVD, magnetic tape, floppy disks, optical data storage, flash memory, and the like, and also in the form of carrier waves (for example, transmission over the Internet). It also includes implementations. The computer readable storage medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. Here, the program or code stored in the storage medium means that a computer or the like is expressed as a series of instruction commands used directly or indirectly in an apparatus having an information processing capability to obtain a specific result. Thus, the term computer is used to mean all devices having an information processing capability for performing a specific function by a program including a memory, an input / output device, and an arithmetic device, despite the name actually used.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope not departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 to 4 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

5 to 8 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention.

9 to 11 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

12 is a flowchart illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

13 is a schematic diagram showing a card according to an embodiment of the present invention.

14 is a schematic diagram illustrating a system according to an embodiment of the present invention.

Claims (10)

Forming a plurality of memory cells and a plurality of select transistors each having a stacked structure of a tunneling insulating layer, a charge storage layer, a blocking insulating layer and a metal layer in a cell region of the substrate; Forming a plurality of peripheral transistors having a stacked structure of a gate oxide film, polysilicon, and a metal layer in the peripheral circuit region of the substrate; Etching the blocking insulating layer between two adjacent ones of the selection transistors; And Depositing a spacer over the memory cells, the select transistors and the peripheral transistors. The method of claim 1, And etching a portion of the spacer deposited between the two adjacent selection transistors and a portion of the spacer deposited in the source region and the drain region of the peripheral transistors. The method of claim 2, Depositing a capping layer over the memory cells, the select transistors and the peripheral transistors, The etching of the blocking insulation layer may include etching the capping layer and the blocking insulation layer between the two adjacent selection transistors. The method according to claim 2 or 3, And etching the predetermined region between the two adjacent selection transistors and the source region and the drain region of the peripheral transistors to form contact regions. The method of claim 4, wherein The contact region formed in the predetermined region between the two adjacent selection transistors is a direct contact (DC) contact, and the contact regions formed in the source region and the drain region of the peripheral transistors are metal contacts. Method of manufacturing volatile memory device. The method of claim 4, wherein Etching the blocking insulating layer, And etching the charge storage layer between the two adjacent select transistors. The method of claim 6, Etching the blocking insulating layer, And etching the tunneling insulating layer between the two adjacent selection transistors. Memory cells and select transistors formed in a cell region on the substrate, each having a stacked structure of a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a metal layer; And A peripheral transistor formed in the peripheral circuit region on the substrate, the peripheral transistor having a laminated structure of a gate insulating layer, a polysilicon, and a metal layer; And the blocking insulating layer is etched in an area between two adjacent selection transistors among the selection transistors. The method of claim 8, And wherein the charge storage layer is further etched in a region between two adjacent select transistors of the select transistors. 10. The method of claim 9, And wherein the tunnel insulation layer is further etched in an area between two adjacent selection transistors among the selection transistors.

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