TWI401664B - Driving circuit for display panel - Google Patents

Description

Display panel driving circuit

The present invention relates to a driving circuit, and more particularly to a driving circuit for a display panel.

According to the current development of technology, the variety of information products has been updated to meet the different needs of many people. Most of the early displays were cathode ray tube (CRT) displays. Due to their large size and power consumption, and the radiation generated, they are harmful to users who use the display for a long time. Today's displays on the market will gradually replace the old CRT monitors with liquid crystal displays (LCDs). Liquid crystal displays have the advantages of being thin and light, low in radiation and low in power consumption, and thus have become the mainstream in the current market.

As described above, the liquid crystal display controls the light transmittance of the liquid crystal unit according to the data signal to display an image. Since the active matrix type liquid crystal display adopts an active control switching device, such a liquid crystal display has an advantage in displaying animation, and a thin film transistor (TFT) is a closing device mainly used for an active matrix type liquid crystal display.

Please refer to the first figure, which is a schematic diagram of a driving system of a liquid crystal display of the prior art. As shown, the drive system includes a display panel 10', a scan drive circuit 12', a data drive circuit 14', a timing control circuit 16' and a reference voltage generating circuit 18'. The display panel 10' is configured to display images, and the scan driving circuit 12' is configured to generate and transmit a scan signal to the display panel 10' to drive a thin film transistor of the display panel 10', and the data driving circuit 14' is used to generate and transmit A data signal is sent to the display panel 10' to display the image according to the data signal. The timing control circuit 16' generates a timing control signal and respectively transmits the timing control signal to the scan driving circuit 12' and the data driving circuit 14' to control the scanning. The driving circuit 12' and the data driving circuit 14 respectively transmit the scanning signal and the data signal to the display panel 10' to display the image. In addition, the reference voltage generating circuit 18' generates a reference voltage and transmits the reference voltage to the data driving circuit 14', so that the data driving circuit 14' generates a data signal according to the timing control signal and the reference voltage.

Please refer to the second figure, which is a schematic diagram of a reference voltage generating circuit of the prior art. As shown in the figure, when the digital display data corresponding to RGB is composed of, for example, 6 bits, the reference voltage generating circuit 18' can output 64 kinds of specific voltages V0 to V63 corresponding to 2 ⁶ = 64 gray scale levels, respectively. . The reference voltage generating circuit 18' is constituted by a resistor dividing circuit in which resistors R0 to R7 are connected in series. Each of the resistors R0 to R7 is connected in series to eight resistors. That is, as shown in the third figure, eight resistors R01, R02, ..., and R08 are connected in series to form a resistor R0, and the remaining resistors R1 to R7 also have the same configuration as the resistor R0. Therefore, the reference voltage generating circuit 18' is composed of 64 resistors, and voltages V0 to V63 are generated.

However, since the reference voltage generating circuit 18' must use about 64 resistors in order to generate 64 different voltage levels, the area of the reference voltage generating circuit 18' will be increased, thereby increasing the area of the display device. Further, in order to reduce the area of the reference voltage generating circuit 18', it is necessary to use a resistor having a large resistance value, but increasing the resistance of the resistor affects the driving ability of the data driving circuit 14'. Further, when the data driving circuit 14' drives the display panel 10' through the resistors, it is necessary to consume a large amount of energy on the resistor, thereby wasting power of the display device.

Therefore, how to solve the above problem is to provide a novel display panel driving circuit, which can reduce the number of used resistors and reduce the area of the display device without affecting the driving capability of the data driving circuit 14', thereby solving the above problem. problem.

One of the objects of the present invention is to provide a driving circuit for a display panel that uses a precharge source to charge a capacitor of a display device to shorten a driving time.

One of the objectives of the present invention is to provide a driving circuit for a display panel that first charges a capacitor of a display device by using a precharge source to avoid energy consumption on the resistor, thereby saving power of the display device.

The driving circuit of the display panel of the present invention comprises a precharge source, a precharge switch, a buffer circuit and a plurality of impedance elements. The precharge switch is coupled between the precharge source and one of the capacitors of the display panel; the buffer circuit is configured to buffer a data signal to generate a buffer signal; the plurality of impedance components are connected in series and coupled to the buffer circuit, and according to the buffer signal And generating a plurality of driving signals between the impedance components; wherein the driving circuit turns on the pre-charge switch, so that the pre-charging source charges the capacitor, and then charges the capacitor with one of the driving signals to shorten the driving time, and Energy consumption can be avoided on the resistor, thereby saving power of the display device.

In order to provide a better understanding and understanding of the structural features and the efficacies of the present invention, please refer to the preferred embodiment and the detailed description as follows: please refer to the fourth figure, which is A schematic diagram of a drive system for a liquid crystal display of the invention. As shown, the drive system includes a display panel 10, a scan drive circuit 12, a data drive circuit 14, a timing control circuit 16, and a gamma circuit 18. The display panel 10 is configured to display images. The scan driving circuit 12 is configured to generate and transmit a scan signal to the display panel 10 to drive a thin film transistor of the display panel 10. The data driving circuit 14 is configured to generate and transmit a data signal to the display. The panel 10 displays the image according to the data signal, and the timing control circuit 16 generates a timing control signal, and respectively transmits the timing control signal to the scan driving circuit 12 and the data driving circuit 14 to control the scan driving circuit 12 and the data driving circuit 14 respectively. The scan signal and the data signal are transmitted to the display panel 10 to display the image. In addition, the gamma circuit 18 generates a reference voltage and transmits a reference voltage to the data driving circuit 14, so that the data driving circuit 14 generates a data signal according to the timing control signal and the reference voltage.

Please refer to the fifth figure, which is a block diagram of a preferred embodiment of the present invention. As shown, the driving circuit of the display panel of the present invention is applied to the data driving circuit 14 to receive 64 voltage levels generated by the gamma circuit 18. The driving circuit of the present invention can receive 8-bit signals. Therefore, the data driving circuit 14 needs to use eight driving circuits to receive and process 64 voltage levels, and the present embodiment is described by only one driving circuit. The driving circuit of the present invention comprises a first pre-charge source AVDD, a first pre-charge switch 140, a buffer circuit 142 and a plurality of impedance elements 143, 144, 146, 148. The first pre-charge switch 140 is coupled between the pre-charge source AVDD and the capacitor 100 of the display panel 10. The buffer circuit 142 is configured to buffer a data signal to generate a buffer signal, and the plurality of impedance elements 143, 144, 146. The 148 are connected in series and coupled to the buffer circuit 142. The impedance elements 143, 144, 146, 148 generate a plurality of driving signals between the impedance elements 143, 144, 146, and 148 according to the buffering signal, and the driving circuit is first turned on. The first pre-charge switch 140 charges the capacitor 100 after the first pre-charge source AVDD charges the capacitor 100, and then charges the capacitor 100 with one of the driving signals. That is, please refer to the sixth figure, which is the driving timing diagram of the driving circuit. As shown in the figure, the dotted line represents the driving circuit charging the capacitor 100 without pre-charging. The solid line is the driving circuit of the invention pre-charging the capacitor 100 charging, as can be seen from the figure, the driving circuit of the present invention first charges the capacitor 100 with the first pre-charging source AVDD during T1 to T2, and charges the capacitor 100 with the driving signal during the period from T2 to T3. In this way, the driving circuit of the present invention has completed driving the display panel 10 at T3, thereby shortening the time for the driving circuit to charge the capacitor 100, and shortening the driving time of the data driving circuit 14 to the display panel 10, thereby increasing the display device. effectiveness. Moreover, since the time during which the driving circuit charges the capacitor 100 is shortened, the time spent on the impedance elements 143, 144, 146, 148 can be reduced, thereby saving power. The impedance elements 143, 144, 146, 148 are a resistor.

In addition, the driving circuit of the display panel of the present invention further includes an analog-to-digital conversion circuit 15 for converting an input signal to generate a data signal. The analog digital conversion circuit 15 is coupled to the gamma circuit 18 to receive the correction data generated by the gamma circuit 18 as an input signal, and the gamma circuit 18 generates the correction data according to a gamma curve. Furthermore, the analog-to-digital conversion circuit 15 is further coupled to a memory unit 20 for storing complex pixel data, and the analog digital conversion circuit 15 receives the pixel data and the correction data as input signals to generate data signals. . The memory unit 20 is a random access memory (RAM).

Referring to the fifth figure, a first switch 150, a second switch 152 and a third switch 154 are respectively disposed between the impedance elements 143, 144, 146, and 148. The analog digital conversion circuit 15 can generate a control signal to turn on/off the first switch 150, the second switch 152 or the third switch 154 according to the pixel data stored in the memory unit 20. Furthermore, the analog digital conversion circuit 15 first controls the first pre-charge switch 140 or the second pre-charge switch 141 to be turned on to charge the capacitor 100 first. When a period of time passes, the first pre-charge switch 140 is controlled. The second pre-charge switch 141 is turned off, and turns on one of the first switch 150, the second switch 152 or the third switch 154 to continuously charge the capacitor 100.

Moreover, the buffer circuit 142 includes a first buffer 1420 and a second buffer 1421. The first buffer 1420 is for buffering the data signal to generate a first buffer signal, and the second buffer is for buffering the data signal to generate a second buffer signal, the impedance elements 143, 144, 146, 148. The driving signal is generated by the voltage difference between the first buffer signal and the second buffer signal generated by the first buffer 1420 and the second buffer 1421. The first buffer 1420 and the second buffer 1421 are an operational amplifier.

In addition, since the liquid crystal of the display panel 10 needs to be reversed in polarity to avoid accumulating charges and affect display quality, the driving circuit of the present invention further includes a second pre-charge source VSS and a second pre-charge switch 141 for driving. The circuit passes through the first pre-charge switch 140 and the second pre-charge switch 141 according to the polarity of the liquid crystal of the display panel 10 to provide the first pre-charge source AVDD or the second pre-charge source VSS to the capacitor 100. The first pre-charge source AVDD and the second pre-charge source VSS can be coupled to any power terminal in the display device.

Please refer to the seventh figure, which is a block diagram of another preferred embodiment of the present invention. As shown in the figure, the embodiment is different from the embodiment of the fifth embodiment in that the first pre-charge source AVDD and the second pre-charge source VSS are coupled to the first buffer 1420 respectively. The output end and the output end of the second buffer 1421, so that the driving circuit is not pre-charged in the process of pre-charging with the first pre-charge source AVDD or the second pre-charge source VSS Overcharge phenomenon and simplify control of switching time.

In summary, the driving circuit of the display panel of the present invention charges a capacitor of a display panel with a precharge source through a precharge switch, and then generates between the impedance components according to the buffer signal. One of the complex drive signals charges the capacitor to reduce the drive time and avoid energy consumption on the resistor, thereby saving power of the display device.

The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the shapes, structures, features, and spirits described in the claims are equivalently changed. Modifications are intended to be included in the scope of the patent application of the present invention.

Conventional technology:

10’. . . Display panel

12’. . . Scan drive circuit

14’. . . Data drive circuit

16’. . . Timing control circuit

18’. . . Reference voltage generating circuit

this invention:

10. . . Display panel

100. . . capacitance

12. . . Scan drive circuit

14. . . Data drive circuit

140. . . First pre-charge switch

141. . . Second precharge switch

142. . . Buffer circuit

1420. . . First buffer

1421. . . Second buffer

143. . . Impedance component

144. . . Impedance component

146. . . Impedance component

148. . . Impedance component

15. . . Analog digital conversion circuit

150. . . First switch

152. . . Second switch

154. . . Third switch

16. . . Timing control circuit

18. . . Karma circuit

20. . . Memory unit

The first figure is a schematic diagram of a driving system of a liquid crystal display of the prior art;

The second figure is a schematic diagram of a reference voltage generating circuit of the prior art;

The third figure is a schematic diagram of a detailed reference voltage generating circuit of the prior art;

The fourth figure is a schematic diagram of a driving system of the liquid crystal display of the present invention;

Figure 5 is a block diagram of a preferred embodiment of the present invention;

Figure 6 is a driving timing diagram of a preferred embodiment of the fifth figure;

Figure 7 is a block diagram of another preferred embodiment of the present invention.

100. . . capacitance

140. . . First pre-charge switch

141. . . Second precharge switch

142. . . Buffer circuit

1420. . . First buffer

1421. . . Second buffer

143. . . Impedance component

144. . . Impedance component

146. . . Impedance component

148. . . Impedance component

15. . . Analog digital conversion circuit

150. . . First switch

152. . . Second switch

154. . . Third switch

18. . . Karma circuit

20. . . Memory unit

Claims (11)

A driving circuit for a display panel, comprising: a precharge source; a precharge switch coupled between the precharge source and a capacitance of the display panel; and a buffer circuit for buffering a data signal to generate And a plurality of impedance elements, wherein the impedance elements are connected in series with each other and coupled to the buffer circuit, and generate a plurality of driving signals between the impedance elements according to the buffering signal; wherein the driving circuit turns on the pre-charging The switch causes the pre-charging source to charge the capacitor, and then charges the capacitor with one of the driving signals. A driving circuit for a display panel according to claim 1, which is applied to a data driving circuit of the display panel. The driving circuit of the display panel of claim 1, further comprising: an analog-to-digital conversion circuit for converting an input signal to generate the data signal. The driving circuit of the display panel of claim 1, further comprising: a gamma circuit that generates and transmits the input signal to the analog-to-digital conversion circuit according to a gamma curve. The driving circuit of the display panel of claim 1, wherein the driving circuit provides a positive voltage signal or a zero voltage signal of the pre-charging source to the capacitor according to the polarity of the liquid crystal of the display panel. The driving circuit of the display panel of claim 1, further comprising: a plurality of switches, one end of which is coupled between each of the impedance elements of the impedance element, and the other end of which is coupled to the display panel, A control signal turns on one of the switches to generate and transmit the drive signal to the capacitor. The driving circuit of the display panel of claim 6, further comprising: an analog-to-digital conversion circuit that generates the control signal according to an input signal to turn on one of the switches. The driving circuit of the display panel of claim 1, wherein the buffer circuit comprises: a first buffer for buffering the data signal to generate a first buffer signal; and a second buffer. The buffer signal is buffered to generate a second buffer signal. The driving circuit of the display panel according to claim 1, wherein the impedance elements are a resistor. The driving circuit of the display panel according to claim 1, wherein the second buffer is an operational amplifier. The driving circuit of the display panel according to claim 1, wherein the first buffer is an operational amplifier.