TWI391945B - Memory system with in stream data encryption/decryption and error correction and method for correcting data in the memory system - Google Patents

Abstract

The throughput of the memory system is improved where error correction of data in a data stream is cryptographically processed with minimal involvement of any controller. To perform error correction when data from the memory cells are read, the bit errors in the data in the data stream passing between the cells and the cryptographic circuit are corrected prior to any cryptographic process performed by the circuit. Preferably the error correction occurs in one or more buffers employed to buffer the data between the cryptographic circuit and the memory where latency is reduced by using multiple buffers.

Description

Memory system with internal stream data encryption and decryption and error correction and method for correcting data in the memory system

The present invention relates generally to memory systems and, more particularly, to memory systems having internal stream data encryption and decryption and error correction.

The mobile device market is including content storage to grow in the direction of increasing average revenue by generating more data exchanges. This means that content must be protected when it is stored on a mobile device.

Portable storage devices have been commercially available for many years. It transfers data from one computing device to another computing device or to store backup data. More sophisticated portable storage devices, such as portable hard drive, portable flash memory and flash memory cards, include a microprocessor for controlling storage management.

In order to protect the content stored in the portable storage device, the stored data is typically encrypted and only authorized users are allowed to decrypt the data.

Since bit errors can exist in the data stored in the portable storage device, error correction is required. Current solutions for error correction may be incompatible with cryptographically capable portable storage devices. There is therefore a need to provide an improved local storage device in which these difficulties are alleviated.

The data stored in the memory unit can contain errors due to several reasons. It is therefore common to perform error correction when reading data from such memory cells. Error correction can also detect the location of such errors in the data stream. The cryptographic processing performed by a circuit can change the position of the bits in the data stream such that if the bit errors in the data stream are not corrected when performing such processing, then The information of the position of the bit error after processing will no longer be correct, so that error correction is no longer possible after performing the cryptographic processing. Thus, one aspect of the present invention is based on the consensus that the bit error in the data in the data stream between the elements and the cryptographic circuit is preferably corrected prior to any encryption processing performed by the circuit. Preferably, at least one buffer is used to store data in the data stream passing between the units and the circuit and the correction is stored in the buffer and derived from the data cryptographic processing of the circuit. Any error or multiple errors in the data of these units.

An exemplary memory system is illustrated by the block diagram of FIG. 1, in which various aspects of the present invention can be implemented. As shown in FIG. 1, the memory system 10 includes a central processing unit (CPU) 12, a buffer management unit (BMU) 14, a host interface module (HIM) 16, and a flash interface module (FIM). 18. A flash memory 20 and a peripheral channel module (PAM) 22. The memory system 10 communicates with a host device 24 via a host interface bus 26 and port 26a. The NAND (reverse) type flash memory 20 can be used to provide data storage for the host device 24. The software code for the CPU 12 can also be stored in the flash memory 20. The FIM 18 is coupled to the flash memory 20 via a flash interface bus 28 and port 28a. The HIM 16 is suitable for connection to a host system such as a digital camera, personal computer, personal digital assistant (PDA), digital media player, MP3 player, and cellular telephone or other digital device. The peripheral channel module 22 selects suitable control modules such as FIM, HIM, and BMU for communication with the CPU 12. In one embodiment, all of the components of system 10 within the dashed box can be enclosed into a single unit (such as a memory card or memory stick) 10' and preferably sealed into a card or wand.

The buffer management unit 14 includes a host direct memory access (HDMA) 32, a flash direct memory access (FDMA) controller 34, an arbiter 36, a buffer random access memory (BRAM) 38, and a Password engine 40. The arbiter 36 is a shared bus arbiter such that only one master or initiator (which may be HDMA 32, FDMA 34 or CPU 12) may be active at any time, and the slave or target is BRAM 38 . The arbiter is responsible for directing the appropriate initiator request to the BRAM 38. HDMA 32 and FDMA 34 are responsible for transferring data between HIM 16, FIM 18 and BRAM 38 or CPU random access memory (CPU RAM) 12a. The operation of HDMA 32 and FDMA 34 is conventional and need not be described in detail herein. The BRAM 38 is used to buffer data passing between the host device 24, the flash memory 20, and the CPU RAM 12a. The HDMA 32 and FDMA 34 are responsible for transferring data between the HIM 16/FIM 18 and the BRAM 38 or the CPU RAM 12a and are responsible for indicating the completion of the sector transfer. As described below, the FIM 18 also has the ability to detect errors in the data read from the flash memory 20 and to notify the CPU 12 when an error is found.

First, when the data from the flash memory 20 is read by the host device 24, the encrypted data in the memory 20 is retrieved via the bus bar 28, the FIM 18, the FDMA 34, and the cryptographic engine 40, wherein the decrypted data is decrypted. The data is encrypted and stored in BRAM 38. The decrypted data is then sent from the BRAM 38 to the host device 24 via the HDMA 32, the HIM 16, and the bus 26 . The data taken from the BRAM 38 can be re-encrypted via the encryption engine 40 before being passed to the HDMA 32, so that the data sent to the host device 24 is encrypted again, but the encryption is stored in the memory by a decryption with them. The key/or algorithm of the data of the volume 20 is compared to a different key and/or algorithm. Preferably, and in an alternate embodiment, the decrypted material is not stored in the BRAM 38 in the process described above, wherein the data may become susceptible to unauthorized access attacks, but may be borrowed prior to being sent to the BRAM 38. The data from the memory 20 is decrypted and encrypted again by the cryptographic engine 40. The encrypted data in BRAM 38 is then sent to host device 24 as before. This illustrates the data stream during a read process.

When the data is written to the memory 20 by the host device 24, the direction of the data stream is reversed. For example, if the unencrypted material is sent by the host device via the bus 26, the HIM 16, and the HDMA 32 to the cryptographic engine 40, the data can be encrypted by the engine 40 before the data is stored in the BRAM 38. Alternatively, unencrypted material can be stored in BRAM 38. The data is then encrypted on the way to the memory 20 before being sent to the FDMA 34. The data written therein is subjected to multi-level cryptographic processing. Preferably, engine 40 performs this processing before storing the processed data in BRAM 38.

When the memory system 10 of FIG. 1 contains a flash memory, the system can be replaced by another type of non-volatile memory, such as a magnetic disk, an optical CD, and a rewritable non-volatile memory system. All other types, and the various advantages described above, will apply equally to this alternative embodiment. In this alternative embodiment, the memory is also preferably sealed to the same entity (such as a memory card or stick) along with the remaining components of the memory system.

Error correction

Data stored in a non-volatile (eg, flash) memory can be subject to damage and contain errors. To this end, the FIM 18 can include an error correction (ECC) circuit 102 that detects which bit or bits of the data stream from the memory 20 contain errors, including in the bit stream. The location of the error. This will be illustrated in Figure 2, which is a block diagram of a memory system 100 for illustrating another aspect of the present invention. The FIM 18 sends an interrupt signal to the CPU 12 when an error is detected in the bit stream, and the circuit 102 transmits information regarding the position of the bit in the error to the CPU 12. In conventional memory systems without cryptographic features, the errors are corrected in the BRAM 38 by the CPU. However, if the data from the data stream is first cryptographically processed prior to the correction, the cryptographic processing may result in a change in the location and/or value of the data bits in the processed data stream, such that after the cryptographic processing The position and/or value of the bit error may be different from the position and/or value of the bit error of the data transmitted by the circuit 102 to the CPU 12. This makes it impossible to correct the errors when the data processed in the cryptographic manner reaches the BRAM 38. One aspect of the present invention stems from the consensus that correcting the detected errors prior to processing the data in a cryptographic manner may avoid this problem.

An error buffer unit (EBU) 104 is used to store data from the data stream passing between the BMU 14 and the FIM 18 such that when the CPU 12 receives an interrupt from the FIM 18 indicating that there is an error in the data stream. The CPU corrects the error in the EBU 104 instead of correcting the error at the BRAM 38. The error bits are simply "exchanged" at the position of the error detected by the circuit 102 (ie, "1" is changed to "0" and "0" is changed to "1") to correct the digital data. .

To reduce the number of interrupts in the data stream when an error is detected, two or more buffers can be used in the EBU 104, such as shown in FIG. As shown in FIG. 3, two buffers 104a and 104b are used, wherein one of the two buffers will receive material from memory 20 via FIM 18 and the other will pass FDMA 34 in BMU 14. Send the data to the cryptographic engine 40. In Figure 3, two switches 106a and 106b are used. When the two switches are in the solid line position as shown in Figure 3, the buffer 104a will supply the data to the BMU 14 and the buffer 104b will receive the data from the FIM 18. When the two switches are in the dashed position as shown in Figure 3, the buffer 104b will supply the data to the BMU 14 and the buffer 104a will receive the data from the FIM 18. Each of the buffers may first be populated with data before the data stored therein is sent to the BMU. The CPU corrects errors in the buffers 104a and 104b as the data is transmitted or received by the buffers 104a and 104b. In this way, the only latency when the data stream begins is the time required to fill one of the two buffers. Thereafter, if the time taken by the CPU to correct the error is less than the time required to fill each buffer, then there will be no interruption in the data stream even when the error is detected by circuit 102.

If the calibration data takes longer than filling a buffer, the data stream will be interrupted only when an error is detected and the data stream will flow without interruption if no error is detected. A buffer-empty signal (not shown) connected between the EBU 104 and the FDMA 34 signals the latter that the data stream is interrupted and no more information is available. FDMA 34 and cryptographic engine 40 will then pause and wait for the data stream to resume.

When the data is written to the memory 20 by the host device 24, no correction error is required so that it will need to skip the EBU. This can be done by switch 108. When the switch 108 is turned off, the data from the HIM 16 (not fully shown in Figure 2) completely skips the two buffers 104a and 104b. The switch 108 can also be turned off in a bypass mode in which no cryptographic processing is required when reading data from the memory 20 or writing data to the memory 20. In this mode, HDMA and FDMA are directly connected to the arbiter 36 as if the cryptographic engine 40 was removed from the system 10, and the data stream skips the EBU 104 and the cryptographic engine 40. This can also be done by using a switch. Thus, in the bypass mode, one of the logic circuits (not shown) in system 100 causes the data stream to skip block 40 and cause switch 108 to turn off under the control of CPU 12.

This error correction process will be explained by the flowchart of FIG. The CPU 12 starts a read operation (ellipse 150) after receiving a read command from one of the host devices 24. The cryptographic engine 40 is then configured with the appropriate security configuration information or records to the scratchpad 52, and the BMU 14 and other parameters for a read operation are configured, such as the memory space for the operation in the BRAM 38. Assignment (blocks 152, 154). The FIM 18 is also configured, such as by specifying the location of the data to be read in the memory 20 (block 156). The HDMA engine 32 and the FDMA engine 34 are then started (see block 158). When the CPU receives an interrupt, it checks to see if it is a FIM interrupt (diamond 160). When receiving a FIM interrupt, the CPU checks to see if the interrupt is an interrupt indicating that one or more errors are present in the data stream (162). If an error is indicated, it begins to correct the error in buffers 104a and/or 104b (block 164) and returns to configure FIM 18 to change the location in memory 20 where the data is then to be read (block 156). When the FIM interrupt is not indicative of an error in the data stream, it means that the FIM has completed its operation and the CPU also returns to block 156 to reconfigure and restart the FIM. If the interrupt detected by the CPU is not a FIM interrupt, it checks to see if it is a data end interrupt (diamond 166). If so, the read operation ends (ellipse 168). If not, the interrupt is independent of the cryptographic processing of the data (i.e., the clock is interrupted) and the CPU 12 is servicing it (not shown) and it returns to diamond 160 to check for the interrupt.

Only a slight modification of Figure 4 is required for a write operation. Since there is no ECC error processing in the data to be written to the memory 20, the CPU 12 can skip the processing in the diamond 162 and block 164 in a write operation. If a FIM interrupt is received by the CPU 12 during a write operation, this means that the FIM completes its operation and the CPU also returns to block 156 to reconfigure the FIM. In addition to this distinction, the write operation is substantially similar to the read operation.

While the invention has been described hereinabove with reference to the various embodiments thereof, it is understood that modifications and modifications may be made without departing from the scope of the invention. All references cited herein are hereby incorporated by reference.

10. . . Memory system

10'. . . Single unit

12. . . Central processing unit / CPU

12a. . . CPU random access memory / CPU RAM

14. . . Buffer Management Unit / BMU

16. . . Host Interface Module / HIM

18. . . Flash interface module / FIM

20. . . Flash memory

twenty two. . . Peripheral channel module / PAM

twenty four. . . Host device

26. . . Host interface bus

26a. . . port

28. . . Flash interface bus

28a. . . port

32. . . Host direct memory access / HDMA

34. . . Flash Direct Memory Access Controller / FDMA

36. . . Arbitrator

38. . . Buffer random access memory/BRAM

40. . . Password engine

100. . . Memory system

102. . . Error Correction Circuit / ECC CKT

104. . . Error buffer unit / EBU

104a. . . buffer

104b. . . buffer

106a. . . switch

106b. . . switch

108. . . switch

1 is a block diagram of a memory system in communication with a host device to illustrate the present invention.

Figure 2 is a block diagram of certain blocks of the memory system of Figure 1.

3 is a circuit diagram illustrating a preferred configuration of the error correction buffer unit of FIG. 2 in more detail.

Figure 4 is a flow diagram illustrating the operation of the system of Figure 2 to illustrate a preferred embodiment of one aspect of the present invention.

For ease of description, the same components are labeled with the same numerals in the present application.

12. . . Central processing unit / CPU

14. . . Buffer Management Unit / BMU

16. . . Host Interface Module / HIM

18. . . Flash interface module / FIM

32. . . Host direct memory access / HDMA

34. . . Flash Direct Memory Access Controller / FDMA

36. . . Arbitrator

38. . . Buffer random access memory/BRAM

40. . . Password engine

100. . . Memory system

102. . . Error Correction Circuit / ECC CKT

104. . . Error buffer unit / EBU

Claims (12)

A memory system comprising: a non-volatile memory; a circuit operative to detect the presence of one or more errors in data read from the non-volatile memory and further operable to generate an indication One of the one or more errors in the data; a cryptographic circuit operable to perform cryptographic processing on the data; at least one buffer operative to transmit the data to the cryptographic circuit The data previously stored from the non-volatile memory; and a processor operative to receive the signal indicative of the presence of the one or more errors in the data and in response to receiving the signal Correcting the one or more errors in the data stored in the at least one buffer before the data is sent from the at least one buffer to the cryptographic circuit; wherein the data from the non-volatile memory to the cryptographic circuit One of the streams is first detected by error and then cryptographically processed, and wherein one of the streams is cryptographically processed when the portion of the stream is error-detected Minute. The memory system of claim 1, wherein when detecting the presence of the one or more errors and correcting the one or more errors, it takes longer to store the data in the at least one buffer, interrupting from the non- A stream of volatile memory to one of the cryptographic circuits. The memory system of claim 1, wherein the at least one buffer comprises two buffers, and wherein the processor is further operable to alternately use the two buffers to store and transmit from the non-volatile memory to the password Electricity Road information. The memory system of claim 3, wherein the processor is further operative to store from the non-volatile memory when data stored in one of the two buffers is sent to the cryptographic circuit The read data is in one of the two buffers. The memory system of claim 1, wherein the processor is further operative to skip the at least one buffer when the memory system is operating in a bypass mode. The memory system of claim 3, wherein only one or more errors in the data stored in the first buffer of the two buffers are corrected than data read from the non-volatile memory To fill one of the two buffers, the second buffer takes longer to interrupt the data stream from the non-volatile memory to the cryptographic circuit. A method for correcting data in a memory system, the method comprising: a circuit comprising a non-volatile memory, operable to detect the presence of one or more errors in the data, a cryptographic circuit, Performing the following steps in at least one buffer and one processor memory system: storing data between the non-volatile memory and the cryptographic circuit in the at least one buffer; before providing the data to the cryptographic circuit Correcting one or more errors in the data stored in the at least one buffer, wherein the processor corrects the data in response to receiving a signal from the circuit indicating the presence of the one or more errors The one or more errors; and Providing the data to the cryptographic circuit after the one or more errors in the data stored in the at least one buffer are corrected; wherein a portion of the data stream from the non-volatile memory to the cryptographic circuit First, the error is detected and then processed in a cryptographic manner, and wherein one portion of the data stream is cryptographically processed when another portion of the data stream is error detected. The method of claim 7, wherein when the presence of the one or more errors is detected and the one or more error corrections are longer than the stored data in the at least one buffer, the non-volatile is interrupted A stream of data from the memory to the cryptographic circuit. The method of claim 7, wherein the at least one buffer comprises two buffers, and wherein the method further comprises alternately using the two buffers to store and transmit data from the non-volatile memory to the cryptographic circuit. The method of claim 9, wherein when the data stored in the second buffer of the two buffers is sent to the cryptographic circuit, the data read from the non-volatile memory is stored in the two buffers. One of the first buffers in the device. The method of claim 7, further comprising skipping the at least one buffer when the memory system is operating in a bypass mode. The method of claim 9, wherein only one or more errors in correcting data stored in one of the two buffers are filled with data read from the non-volatile memory. When one of the two buffers takes longer, the data stream from the non-volatile memory to the cryptographic circuit is interrupted.