JPS642136A - System for controlling fifo buffer - Google Patents
System for controlling fifo bufferInfo
- Publication number
- JPS642136A JPS642136A JP62158307A JP15830787A JPS642136A JP S642136 A JPS642136 A JP S642136A JP 62158307 A JP62158307 A JP 62158307A JP 15830787 A JP15830787 A JP 15830787A JP S642136 A JPS642136 A JP S642136A
- Authority
- JP
- Japan
- Prior art keywords
- pointer
- output
- data
- effective
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Communication Control (AREA)
Abstract
PURPOSE: To realize the output interruption of error data and the absorption of a speed difference with a simple constitution by executing the output control in accordance with an output pointer and an effective pointer to show the final position of the outputtable data.
CONSTITUTION: An error detecting part 2 executes the error detection of input data, a control part 3 has an input pointer IP and an output pointer OPP to show the input position and output position of a buffer memory 1 respectively, in addition, an effective pointer VP to show the final position of the outputtable data of a buffer 1 is provided, the output control is executed in accordance with the output pointer OP and the effective pointer VP, and in accordance with the output of the error detecting device 2, the updating control of the effective pointer VP is executed. Thus, the judgement whether or not the buffer 1 is empty is executed by the comparison between the output pointer OP and the effective pointer VP, and only by changing the updating of the effective pointer VP to be executed when it is confirmed that the error is not present at the data of a processing unit, the function of the output interruption of error data can be given to the FIFO buffer having high speed absorption.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-158307A JPH012136A (en) | 1987-06-25 | FIFO buffer control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-158307A JPH012136A (en) | 1987-06-25 | FIFO buffer control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS642136A true JPS642136A (en) | 1989-01-06 |
JPH012136A JPH012136A (en) | 1989-01-06 |
Family
ID=
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008524754A (en) * | 2004-12-21 | 2008-07-10 | サンディスク コーポレーション | Memory system having in-stream data encryption / decryption and error correction functions |
US8396208B2 (en) | 2004-12-21 | 2013-03-12 | Sandisk Technologies Inc. | Memory system with in stream data encryption/decryption and error correction |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008524754A (en) * | 2004-12-21 | 2008-07-10 | サンディスク コーポレーション | Memory system having in-stream data encryption / decryption and error correction functions |
US8396208B2 (en) | 2004-12-21 | 2013-03-12 | Sandisk Technologies Inc. | Memory system with in stream data encryption/decryption and error correction |
TWI391945B (en) * | 2004-12-21 | 2013-04-01 | Sandisk Technologies Inc | Memory system with in stream data encryption/decryption and error correction and method for correcting data in the memory system |
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