TW546933B - Circuit structure and signal encoding method capable of reducing signal number of serial ATA separating physical layer interface - Google Patents

Abstract

The invention relates to a circuit structure with ATA interface, in particular a circuit structure capable of reducing signal number of serial ATA separating physical layer interface. Its separating physical layer chip primarily comprises at least a parallel to serial converter, at least a serial to parallel converter, at least a phase lock loop (PLL), at least a transmitter, at least a receiver and at least a 00B signal detector and utilizes digital and analog separating structure to fabricate high frequency analog circuit in separating physical layer chip, while digital circuit part can be integrated in media access controller, further ensuring production yield rate of digital control chip. Using characteristics of interface signal itself and characteristics of decimal data encoding to transmit and encode control signal and status signal with a multi-level signal to data signal so as to lower interface signal number required to link with separating physical layer chip and master control chip.

Description

546933 V. Description of the invention (i) ffa is about the circuit structure of an ΑτA interface, especially the circuit structure of the main Sunchatian * knife-off physical layer interface signal number. Ten-bit data: ΐ and use The characteristics of the interface signal itself and the 'in the data signal' can effectively reduce the communication properties required for the connection. It is good: it is highly developed in the information-related industry and people are investing in: the need for two people to lose speed. "As a result, the industry continues to develop the transmission interface specifications. As far as the storage interface is concerned, the earliest # ^^ 16MBps ^ ATA (Advanced Technology Attaint) " surface has been continuously improved to generate a transmission rate M ·" (Μ " per second ) 'S ATA33 interface and transmission rate "-" people use "Interface tricks: As for the interface specifications such as ATA100 and ATA133, but because the above interface ^ is transmitted in parallel (parallel) data transmission method, not only ^ required signals The number of lines is large, the noise interference is large, the length of the transmission line is limited, and the increase of the transmission rate is also difficult. Recently, due to the continuous attempts of developers from all walks of life, a serial ATA interface specification has finally appeared, which not only increases the transmission rate to 1.5 Gbps (giga bit per second) in the first generation, but also the second generation in the future. 3.0Gbps and 6.0Gbps of the third generation are also expected in the future, and its data transmission requires only four signal lines, and the length of its signal lines can also be large & lengthened, which is a major breakthrough. However, the products of the tandem ATA interface interface specification are still in the development stage 546933 V. Description of the invention (2) --- The parallel ATA products are still the mainstream on the 4 '. Considering the scalability: t ϊ ί' Industry in Computer systems are still designed to support both interface specifications. The solution adopted by some operators is shown in Figure 2, which is mainly based on the storage media controller of the chip i 2 (such as the South Bridge chip), and a serial ATA physical layer (physical iayer) ρΗγ) 1 2 3, through which the serial ATAA physical layer 123 can connect a string of jΑΤΑ devices 16 (such as a serial ATAA hard disk), and the storage media controller 1 2 1 is converged through an ide Row 4 is connected to a parallel ατα device 1 8 (such as a parallel ΑΑΑ hard disk). Although this architecture can support both tandem ΑΑΑ devices and parallel ΑΑΑ devices, the tandem < ατα physical layer 1 2 3 is mainly based on the same frequency analog circuit, which requires a large area. The integration into the main control chip 1 2 + will cause the area of the main control chip worker 2 to be too large, and the yield of its production is difficult to control. Therefore, how to propose a novel solution to the shortcomings of the conventional circuit architecture and the problems that occur during use, and design a simple and effective circuit structure that can not only reduce the pins required for connection, but also ensure the main control chip The yield rate and effective cost reduction have long been the difficult points for users to look forward to and the inventor wants to solve. The inventor is based on the practice of related research, development, and sales in the information industry Experience, thoughts and ideas for improvement. After various designs, discussions, trial samples, and improvements, a circuit architecture and device with parallel and serial ατα interfaces are finally developed to solve the above problems.爰 is 546933

The main feature of the invention | The separated physical layer interface S 'is to provide a circuit structure and signal encoding method that can reduce the number of serial atas to be applied to the digital fish number. Below the main bridge, the phase separation cylinder and the ratio separation The design of the control chip 'in this design, the mounting circuit part can be produced in a separate physical layer chip' and the number is coded, which can be effectively used in the storage media controller of Poetry II through appropriate information. Subtracting the serial AT's separated physical layer interface signals requires the target signal to be decoded with a multi-level signal state signal and the physical layer signal to reduce the continuous signal of the physical layer signal. The identification number of the required number of digits is used to transmit the level information by the electric number of the number, the position of the electric control signal of the number, and the normal person who composes the information. Provide a road structure, to the physical layer number and to provide a road structure, number and status. Provide a coding method, data encoding. The sub-separable physical layer control signal of the present invention can also separate the real-world separated real device and a signal. The special data signal of the real-world separated real-coded encoding can reduce the serial ΑΓΓΑ. The main control wafer can be a wafer, and a physical layer wafer is a master control wafer. Can reduce serial ΑΤΑ Can use a signal encoding Signal encoding in data messages Can reduce serial ΑΑΑ It mainly uses the special code of the signal to replace the original

Hereby, in order to make the #examiners have a better understanding and understanding of the features, structure and effects of the present invention, I would like to accompany the detailed description with the preferred embodiments and the detailed explanations as follows: The main structure of the separation of the preferred embodiment includes First, please refer to FIG. 2, which is a block diagram of a solid-layer chip circuit according to the present invention. As shown in the figure, 546933 V. Description of the invention (4) There are a serializer / deseriaiizer (Ser Des), a phase locked loop (PLL), and at least one transmitter 4 0 5. At least one receiver 4 0 7 and at least one 00B signal detector 4 6 1. The components required for the tandem ATAA physical layer under the framework of the present invention are designed in two chips according to the circuit characteristics. The discrete physical layer chip 4 includes all high-frequency analog circuits. The other physical layer circuits are The digital circuit is mainly integrated in the storage media controller, such as an encoder (8B10B encode r) that converts the 8-bit signal and control signal of the parallel ATP to a 10-bit signal and 10 bits from the serial ATP signal. The signal is converted into an 8-bit signal and a control signal decoder (10B8B decoder) and a word aligner (word alignment). In this way, the main control chip will not increase the chip area due to the integration of high-frequency analog circuits, and can maintain its production yield, and the main control chip needs the pins required for the connection between the serial ATA and the serial ATA separated physical layer 40. Can also be greatly reduced. In this embodiment, the parallel-to-serial converter includes a parallel-to-serializer (PIS〇) 4 2 3 and a serial-to-parallel converter (deserializer; SIP0) 4 4 3, and the phase-locked loop It also includes a transmitting phase-locked loop 4 2 1 and a receiving phase-locked loop 4 4 1, wherein the transmitting phase-locked loop 4 2 1 can generate a serial ATA discrete real-time & layer 40 when required to send signals. The pulse signal is sent to the parallel-to-serial converter 4 2 3 and the storage media controller as its reference clock signal (Re fC 1 k). The parallel-to-serial converter 4 2 3 is based on the effective signal (TxVal id) and sampling clock signal from the storage media controller.

546933 V. Invention Description (5) (strobe differential clock; TxStrobe, TxStrobe) converts the data signal to be sent from a set of parallel signal transmission lines (TxDat a [4: 0]) into a serial ΑΑΑ data signal (TxData), which is transmitted to the serial ΑΑΑ device by the transmitter 405 in a set of serial signal transmission lines (TXP1, TXN1 or TXP2, TXN2). In the receiving part, the receiver 408 receives the signal from the serial ΑΑΑ device through a serial signal receiving line (RXP1, RXN1 or RXP2, RXN2) and sends it to the serial-to-parallel converter 4 4 3, and the serial-to-parallel converter 4 4 3 converts the serial signal into a parallel signal according to the clock signal generated by the phase-locked loop 4 4 1 and passes a parallel signal receiving line (RXD ata [ 4: 0]) and two sampling clock signal lines (r χ s trob, RxStrob—) send the data signal and sampling clock signal to the storage media controller. In addition, at least one 00B signal detector (out 0f ba nd signal detector) 4 6 1 is connected to each serial signal receiving line to detect the status of signal transmission, and will receive squashed signals (Squelch), The initialization signal (Cominit) and the wake-up signal (commWake) are transmitted to the storage media controller. Furthermore, in this embodiment, since two sets of transmitters and receivers are included, an active tandem ATHA hard disk and a slave tandem ATHA hard disk can be connected at the same time. Therefore, an active slave selector is also provided in the device. (Fflaster / slaVe selec tor) 4 2 5 and 4 4 5 can receive the control signal (Master) from the storage media controller and choose the active or slave transmission line. Among them, the active slave selector 4 2 5 is connected to each transmitter 450, and can be activated after receiving the transmission enable signal (TxEnable) of the parallel to serial converter 4 2 3

Page 8 546933 V. Description of the invention (6) Enable corresponding transmitter 40 5. The other active slave selector 4 4 5 can transmit the data signal (RxData) corresponding to the receiver 4 07 to the serial-to-parallel converter 4 4 3. In order to reduce the number of pins connected to the serial ATA separate physical layer 40 and the storage media controller, a selector 403 can be added to the device, or it can be selected from the corresponding 00B according to the control signal (Master). The received stationary signal (S i gQu iet) of the signal detector 4 6 1 is transmitted to the storage media controller. In addition, another selector 409 can be added to the device. The input end is connected to the active slave selector 4 4 5 and the parallel-to-serial converter 4 2 3 ′, and the output end is connected to the serial-to-parallel converter 4. 4 3, according to a control signal (Loopback), a normal sending and receiving path can be selected or the serial signal converted by the parallel-to-serial converter 4 2 3 is transmitted to the serial-to-parallel converter 4 4 3 to form a Loop back to test whether the encoding and decoding operations between parallel and serial signals in the system are correct. In addition, the serial ATA separate physical layer 40 of the present invention is further provided with a power controller 4 01, which can respectively receive a physical layer reset signal (PhyReset) and a multi-level signal from the storage media controller. The power control signals P art S 1 um 1 and P art S 1 um 2 are used for integrated power saving control of the power supply. PartSluml and PartSlum2 can obtain the real power control signal parti ali through the level detector 4 1 1. Slumber 1, Par ia 12 and S1 umber2 〇 The appearance of the corpuscle chip can also be based on the send-ready signal (TxReady) from the send phase-locked loop 4 2 i and the receive-ready signal (RxLocked) from the receive phase-locked loop 4 4 1 ) Respond to the storage media controller by the above

Page 9 546933

= The signal is composed of multi-level multi-level (PhyReady) signals through the level converter 4 i 2. Secondly, please refer to No. 3 ', which is a circuit block diagram of another embodiment of the present invention. The main structure shown in the figure is roughly the same as the embodiment shown in Figure 2. However, it can also be added-a control signal decoder 4 8 and a state signal encoder 4 8 3 °, where the control signal decoder 4 8 i is connected In this group of parallel signal transmission lines (TxData [4: 0]), it is used to receive a data signal containing a valid transmission signal. The data signal can be decoded to obtain a valid transmission signal (TxVal id), and then sent to the parallel transmission. In a serial-to-serial converter, the number of pins required for a connection can be reduced. The status signal encoder 4 8 3 is connected to the serial-to-parallel converter 4 4 3, which can encode the received still signal (SigQuiet) from the selector 4 03 into the data signal, and then receive it through the parallel flood Line (RxDa ta [4: 0]) to the storage media controller 'can reduce one connection pin. In addition, the phase-locked loop of the present invention may be provided with a plurality of transmission rate switching options. The ability to use a signal line (not shown) to connect to the storage media controller to receive control signals from the storage media controller for different purposes. The switching action of the transmission rate can meet the transmission rate of all generations of serial ATA specifications. In addition, the circuit structure of the present invention can be integrated into a separate physical layer chip, which can facilitate production and save costs. Please refer to FIG. 4 and FIG. 5, which are timing diagrams of the multi-level power control signal and the multi-level physical layer ready status signal of the present invention, respectively. As shown in Figure 4, the storage media controller converts the power control signal through multiple levels, and the PartSlum signal represents the Partial or Slumber signals at the level.

546933 V. Description of Invention (8). Low level sadness (V-low) represents no action for Partial and Slumber; V-mid status represents Partial; high level status (v — high) represents S 1 umber. The physical layer chip obtains the true power control signal through level detection. As shown in FIG. 5, the physical layer ready signal (PhyReady) of the present invention is a multi-level status signal which is a combination of a send ready signal (TxReady) and a receive ready signal (RxLocked), that is, when sending a phase lock When the loop is not ready, the physical layer ready signal is in the low level state (v—10w); only when the transmission phase-locked loop is ready, it is in the mid-level state (v-mid); and the sending and receiving phase-locking When the loops are ready, it is in the high level state (V-high). > Please refer to FIG. 6 and FIG. 7 respectively, which are timing diagrams of the decoding of a valid signal transmitted and the encoding of a stationary signal according to the present invention, respectively. Among them, Data [4: 0] and RxData [4: 0] are data signals before decoding and before encoding, respectively, and TxData — de [4: 0] and RxData_en [4: 〇] are after decoding respectively. And the encoded data signal, TxVaUd — de is the effective signal sent after decoding. Since 8-bit data is converted into 10-bit signals, normal encoding cannot generate all data signals that are all 0 or 1. Therefore, we can use this feature to store a control signal on the storage media controller side. In the interval in which the effective signal is transmitted at a low level, the data signal to be transmitted in this interval is replaced by all the same as 0 or the same as that of Wang Xi, while the physical chip ^ control signal decoder is decoded to obtain the effective signal. . Stationary II; $, aspect 'The state signal encoder in the physical chip receives the same number 0 or all the same i in the interval of receiving the static direction to replace the received data number of product B, and is controlled in the storage medium. Device-side signal decoding 546933 V. Description of the invention (9) The device is based on receiving stationary signals. Using the circuit structure and signal coding method described above, the design can be simplified and the power of the separated physical layer can be brought into full play, and the number of connection pins required for the storage media controller can be greatly reduced. For the first- and second-generation serial ATA specifications, it can even be reduced to less than 27 pins (the LoopBack pin is used for testing without connecting the control module), and the original storage media bus can be directly connected. Not having to add a pin for the control chip not only greatly reduces the production cost, but the system designer can also decide whether to add a separate physical layer chip without considering modifying the motherboard design. / 'In summary, when the present invention is related to a circuit structure of an ATAA interface, especially a circuit structure that can reduce the serial ATAA discrete physical layer interface signal ^, it mainly uses digital and analog separation. Structure, the high-frequency analog circuit is made in a separate physical layer chip, and the part of the control and status is transmitted or encoded in a multi-level signal by using the characteristics of the interface signal itself and the characteristics of the ten-bit data encoding In the signal, it can effectively connect the required interface signals. Therefore, the present invention is truly novel, progressive, and available for industrial use. It should meet the requirements of the patent application, and submit an application for an invention patent in accordance with the law. I would like to invite your reviewer to grant the invention patent earlier. Poop. However, the above is only a preferred embodiment of the present invention, and is used to limit the scope of the present invention, that is, where the shape, structure, characteristics and spirit described in the patent application according to the present invention are All equal changes and modifications should be included in the scope of patent application of the present invention.

546933

V. Description of the invention (ίο) Brief description of drawing number 1 2 Main control chip 1 2 1 Storage media controller 1 2 3 Serial ATA physical layer 1 4 IDE bus 1 6 丨 Serial SATA device 18 Parallel ATP device 4 0 Tandem ΑΤΑ separated real body layer 4 0 1 Power controller 4 0 3 Selector 4 0 5 Transmitter 4 0 7 Receiver 4 0 8 Receiver 4 0 9 Selector 4 1 1 Level detector 4 1 2 Level converter 4 2 1 Send phase-locked loop 4 2 3 Parallel-to-serial converter 4 2 5 Active slave selector 4 4 1 Receive phase-locked loop 4 4 3 Serial-to-parallel converter 4 4 5 Master status Slave selector 4 6 1 OOB signal detector 4 8] L control signal decoder 4 8 3 status signal encoder

Page 13 546933 Brief description of the diagram. Figure 1: A block diagram of a conventional ATAA interface structure. Figure 2: A circuit block diagram of a preferred embodiment of the present invention. Figure 3: A block diagram of another embodiment of the present invention. Circuit block diagram; Figure 4: timing diagram of the multi-level power control signal of the present invention; Figure 5: timing diagram of the ready state signal of the physical layer of the present invention; and Figures 6 and 7: respectively Invented the timing diagram of sending effective signal decoding and receiving stationary signal coding.

Page 14

Claims (1)

546933 VI. Scope of patent application 1. A circuit structure capable of reducing the number of signals in a serial ATA separated physical layer interface. The main structure includes a parallel serial converter, which uses a set of parallel signal transmission lines and A set of parallel receiving cables is connected to a storage media controller for converting parallel signals from the storage media controller into serial signals, and converting serial signals to parallel signals and transmitting to the storage media controller; 'A phase-locked loop connected to the parallel-to-serial converter to generate a clock signal required for data signal transmission and to transmit a reference clock signal to the storage media controller; ^ A at least one transmitter, When connected to the parallel serial converter, each transmitter can convert the data signal into a serial data signal and send it to a serial ΑΑΑ device connected through a serial signal transmission line; at least one receiver, connect In the parallel serial converter, each receiver can transmit the data signal received from the connected serial ΑΑΑ device to a serial signal receiving line through a serial signal receiving line. Parallel-to-serial converter, which converts the data signal into a parallel signal and sends it to the storage media controller; and at least one 00B signal detector, which is connected to the receiving signal line of each corresponding receiver , Used to detect the operating status of the serial ATA device 'and can send the complex array signal obtained from the debt measurement to the storage media controller. '2 · The circuit structure described in item 1 of the scope of patent application, wherein the parallel-to-serial converter may include a parallel-to-serial converter and a serial Page 15 546933 Parallel to parallel converters, such as the patent application scope, may include one. The circuit structure described in item 1 sends a phase-locked loop and-creates' where the phase-locked receives the phase-locked loop. 4 · If the patent application has a power control group control signal, send a physical layer to the patent application and the actual 5 · Those who apply for a signal. 6 · If the application layer is ready, the patent signal signal system is received as soon as it is received. 7 · If the patent application is signaled, there is a control signal that includes the sender and the sender. The device can receive signals from the storage media control to control its reset and other power states to the circuit structure described in item 4 of the storage media controller. ^ The signal for somatic-ready cancer is-item number 4 The circuit structure includes a signal originating from one of the phase-locked loops. According to the circuit structure described in item 1, the decoder is connected to the parallel signal of the parallel signal transmission line to decode the parallel signal, and the divided signal and parallel data signal are transmitted to the complex number of the y-direction container, and can be passed on. The power supply position status message is still included in the entity ready to send message. It can be decoded in parallel. 8 · The circuit structure described in item 1 of the scope of patent application, in which Shang Baoren has a status signal encoder, By connecting the parallel serial converter, the parallel data signal after conversion and the reception from the 00B signal detector can be encoded and transmitted to the storage media controller via the parallel signal receiving line. ' 546933 6. Scope of patent application • The circuit structure described in item 1 of the scope of patent application, which also includes a transmission path controller, which connects each transmitter and each receiver, and can control the data signal according to the control signal of the storage media controller. Its transmission path. 10. The circuit structure as described in item 9 of the scope of the patent application, wherein the transfer path controller is an active slave selector. 11 The circuit structure as described in item 10 of the scope of patent application, wherein the active slave selector can include a sending active slave selector and a receiving active slave selector. 12 · The circuit structure described in item 1 of the scope of patent application, which still includes a selector, connected to each OOB signal detector, and can choose to detect one of the 100B signals according to the control signal of the storage media controller. The receiver receives the stationary signal and sends it to the storage media controller. 13 · The circuit structure described in item 8 of the scope of patent application, which still includes a selector, connected to each OOB signal detector, and can choose to detect one of the 100β signals according to the control signal of the storage media controller. The receiver's still signal is sent to the status signal encoder. 14 · The circuit structure described in item 1 of the scope of patent application, wherein the phase-locked = road still includes a transmission rate switching function, which can select the signal to switch the transmission rate according to the speed of the storage media controller. 15 · The circuit structure described in item 丄 of the patent application scope, wherein the phase-locked loop has a plurality of transmission rate switching selection functions, which can switch the action by receiving a control signal from the storage media controller through a signal line. Page 17 / 、、 Scope of patent application 1 6 · The circuit structure as described in item 2 of the scope of patent application, which can be integrated on a chip t. " 17 · A numbering method that can reduce the number of pins in the serial ATA discrete physical layer 'It is mainly in the data signal transmitted between the serial ATA discrete physical layer and the cast media controller' An encoder and a decoder incorporate control signals and status signals into the data signal, thereby reducing the number of connected pins. + 1 8 · The signal coding method as described in item 17 of the scope of patent application, wherein if the data signal is transmitted from the storage media controller to the serial ATA separated physical layer, it can be sent in the interval where the effective signal drops , Replace all the data with 0 or all 1. 1 9 · The signal coding method described in item 7 of the patent scope, if the data signal is transmitted from the serial ATA separated physical layer to the storage media controller, it can be raised between receiving the static signal. In the text, all data are replaced by 0 or all 1.