CN104035908A - Signal processing system and associated method - Google Patents
Signal processing system and associated method Download PDFInfo
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- CN104035908A CN104035908A CN201410078322.8A CN201410078322A CN104035908A CN 104035908 A CN104035908 A CN 104035908A CN 201410078322 A CN201410078322 A CN 201410078322A CN 104035908 A CN104035908 A CN 104035908A
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Abstract
The present invention provides a signal processing system distributed across a first chip and a second chip, and associated method. The signal processing system includes a first inter-ship connection circuit, a second inter-ship connection circuit, and a quantity of converters. Each converter includes multiple serially coupled units forming multiple frequency interfaces, and each of the units is capable of converting frequencies between two consecutive frequency interfaces. The first inter-ship connection circuit and the second inter-ship connection circuit partition each converter to a first portion and a second portion at a corresponding one of the frequency interfaces of each converter. The first portion and the second portion of each converter are respectively formed in the first chip and the second chip, and the first inter-ship connection circuit and the second first inter-ship connection circuit are arranged to relay signal between the first portion and the second portion of each converter. The signal processing system and associated method has higher flexibility.
Description
Technical field
The invention relates to a kind of signal processing system and method thereof, particularly relevant for a kind of by suitably cutting apart converter, be that the different branches that are formed in different chips optimize signal processing system and the method thereof that realizes cost.
Background technology
The broadcasting of multimedia (as audio frequency and/or video) and/or collection (as reception, seizure, record etc.) have been very popular even indispensable functions in modern electronics; These electronic installations comprise mobile phone, intelligent mobile phone, flat board/notebook computer, Wearable accessory, digital camera and camcorders (camcorder), omniselector (as satellite positioning device), monitoring (surveillance) equipment, hand-held device and pocket computer etc.For processing multimedia broadcasting and collection, existing structure is by analog-digital converter (ADC, analog-to-digital converter) with digital analog converter (DAC, digital-to-analog converter) be integrated into coding and decoding (codec, coding-decoding) chip, with master chip Collaboration; For example, this master chip can be central processing unit (CPU), application processor (application processor) or fundamental frequency (baseband) processor.Coding and decoding chip and master chip are by exchanging signal across chip connection mechanism.
For instance, for reaching broadcasting and the collection of audio frequency, coding and decoding chip is that master chip is bridged to one or more loudspeakers and one or more microphone.During audio plays, the digital audio and video signals that provides wish to play by master chip, this digital audio and video signals can be by being transferred to coding and decoding chip across chip connection mechanism, and be converted into analog output signal by coding and decoding chip, to drive loudspeaker.While collecting audio frequency, the simulated audio signal by coding and decoding chip, microphone being detected is converted to digital signal, and by being transferred to master chip across chip connection mechanism.
In the prior art, at master chip and coding and decoding chip chamber transmission (relay) digital audio and video signals, across chip connection mechanism, being with I2S(inter-IC sound) serial media bus (hereinafter to be referred as Slimbus) realizes between bus or low-power chip.For the digital audio and video signals at master chip and coding and decoding chip chamber two-way (bi-directional) exchange stereophony (2-channel stereo), three of minimum need of I2S are across chip wiring, therefore master chip need have three ball pin (ball) (or stitch (pin)), and coding and decoding chip need have other three ball pin.If support more multichannel, I2S needs more wiring, so master chip and coding and decoding chip also must arrange more ball pin.Therefore, I2S bus lock into high pin number (counting of ball pin) with complicated across chip wiring.
On the other hand, Slimbus can be at master chip and coding and decoding chip chamber supports the DAB two-way exchange of multichannel with twin wire across chip communication.Yet, Slimbus must realize complicated network layer in master chip and coding and decoding chip, comprises Physical layer (physical layer), ccf layer (frame layer) and more high-rise messaging protocol (message protocol) and host-host protocol (transport protocol).Therefore,, no matter be at master chip or coding and decoding chip, Slimbus locks into complicated hardware and larger layout area.
Summary of the invention
In view of this, the present invention proposes a kind of signal processing system and method.
According to first embodiment of the invention, provide a kind of signal processing system.This signal processing system distributes and crosses over the first chip and the second chip, and comprise: first across chip connecting circuit, be formed in this first chip, second across chip connecting circuit, be formed in this second chip, and be coupled to this first across chip connecting circuit, and a plurality of converters of changing between digital signal and simulating signal; Arbitrary converter in the plurality of converter comprises: a plurality of unit that form the serial connection of a plurality of frequency interface, different frequency interface is associated with different frequency respectively, and the inversion frequency between two continuous side frequency interfaces of the arbitrary unit in the plurality of unit; Wherein, this first second is divided into first branch and second branch at the corresponding frequency interface place of this arbitrary converter by this arbitrary converter across chip connecting circuit across chip connecting circuit with this, this of this arbitrary converter the first branch and this second branch are formed at respectively in this first chip and this second chip, and this first across chip connecting circuit and this second across chip connecting circuit signal transmission between this first branch of arbitrary converter and this second branch.
According to second embodiment of the invention, provide a kind of signal processing method.This signal processing method is realized distributing and is crossed over the signal processing system of the first chip and the second chip, this signal processing method comprises: arrange a plurality of converters, arbitrary converter in the plurality of converter receives input signal, and correspondingly provide output signal by the conversion between digital signal and simulating signal, wherein, this arbitrary converter is split into the first branch being formed in this first chip and is formed at the second branch in this second chip, and one of them of this first branch and this second branch changed the sample frequency of this input signal, so that the M signal of different sample frequency to be provided, and by be formed at first in this first chip across chip connecting circuit be formed at second in this second chip across chip connecting circuit, between this first branch of this arbitrary converter and this second branch, transmit this M signal.
Signal processing system proposed by the invention and method, have stronger dirigibility.
Accompanying drawing explanation
Fig. 1 to Fig. 8 is according to the schematic diagram of the signal processing system of embodiment of the present invention.
Fig. 9 is for optimizing the design cycle of embodiment of the present invention.
Embodiment
Please refer to Fig. 1, Fig. 1 is according to the schematic diagram of the signal processing system 100 of embodiment of the present invention.Chip 101 and chip 102 are crossed in the distribution of signal processing system 100.Signal processing system 100 comprises across chip connecting circuit 111 and across chip connecting circuit 112, and converter DA[1] to converter DA[P] and converter AD[1] to converter AD[Q] (wherein the number of converter is (P+Q)).Converter DA[p] (wherein, p=1～P) each in is digital analog converter (for example, with poor digital analog converter (sigma-delta DAC)), can be by signal Sa[p, 0] be converted to signal Sa[p, Nu+2], signal Sa[p wherein, 0] be digital input signals, signal Sa[p, Nu+2] be analog output signal.Converter AD[q] (wherein, q=1～Q) each in be analog-digital converter (for example, with poor analog-digital converter (sigma-delta ADC)), can be by signal Sb[q, 0] be converted to signal Sb[q, Nd+1], signal Sb[q wherein, 0] be analog input signal, signal Sb[q, Nd+1] be analog output signal.Across chip connecting circuit 111 and across chip connecting circuit 112, be formed at respectively in chip 101 and chip 102, by converter DA[p] (wherein, p=1～P) each in is divided into the X1[p of branch being formed at respectively in chip 101 and chip 102] and the X2[p of branch], and, also by converter AD[q] each in (wherein, q=1～Q) is divided into the Y1[q of branch that is formed at respectively chip 101 and chip 102] with the Y2[q of branch].That is, two chips (chip 101 and chip 102) are at least crossed in the distribution of signal processing system 100.
Chip 101 comprises external data ball pin (stitch) Da[1 for signal exchange] to data ball pin (stitch) Da[K] (wherein the number of data ball pin is K), and external clock signal ball pin (stitch) B1, in order to receive clock signal CK1.Accordingly, chip 102 comprises the external data ball pin Db[1 for signal exchange] to data ball pin Db[K] (wherein the number of data ball pin is K), and external clock signal ball pin B2, in order to transmit clock signal CK1.Each is to data ball pin Da[k] with data ball pin Db[k] (wherein, k=1～K) couple mutually, clock signal ball pin B1 couples mutually with clock signal ball pin B2.By data ball pin Da[1] to data ball pin Da[K] and data ball pin Db[1] to data ball pin Db[K], across chip connecting circuit 111 with across chip connecting circuit 112, mutually couple, to carry out bidirectional data transfers according to the sequential of clock signal C K1.Correspondingly, can intercom mutually across chip connecting circuit 111 with across chip connecting circuit 112, just can be each converter DA[p] (wherein, p=1～P) by signal by the X1[p of branch] transfer to the X2[p of branch], and be each converter AD[q] (wherein, q=1～Q) by signal by the Y2[q of branch] transfer to the Y1[q of branch], to make converter DA[p] in each can settling signal Sa[p, 0] to signal Sa[p, Nu+2] numeral to analog-converted (wherein, signal Sa[p, 0] be digital input signals, signal Sa[p, Nu+2] be analog output signal), and make converter AD[q] in each can settling signal Sb[q, 0] to signal Sb[q, Nd+1] simulate to digital conversion (wherein, signal Sb[q, 0] be analog input signal, signal Sb[q, Nd+1] be digital output signal).
According to the embodiment of the present invention, signal processing system 100 can be audio codec system, for changing between digital audio and video signals and simulated audio signal, chip 101 can be high-speed digital integrated circuit, with advanced, expensive small size (meter level as how) technique manufacturing; 102 of chips can be composite signal integrated circuits, with ripe, large scale (as micron order) technique manufacturing cheaply.Converter DA[1] to converter DA[P] for the stereo audio of P sound channel, play, wherein, signal Sa[1,0] to signal Sa[P, 0] be the digital tone source signal to be played of P sound channel, by digital interface circuit DI(, be formed in chip 101) provide, and by converter DA[1] to converter DA[P] be converted to respectively signal Sa[1, Nu+2] to signal Sa[P, Nu+2], make signal Sa[1, Nu+2] to signal Sa[P, Nu+2] can be in order to drive P loudspeaker (not shown) (wherein, signal Sa[1, Nu+2] to signal Sa[P, Nu+2] be analog output signal).On the other hand, converter AD[1] to converter AD[Q] for the stereo audio of Q sound channel, collect, wherein, signal Sb[1,0] to signal Sb[Q, 0] for Q the simulated audio signal that microphone (not shown) detects, understand by converter AD[1] to converter AD[Q] be converted to respectively signal Sb[1, Nd+1] to signal Sb[Q, Nd+1] (wherein, signal Sb[1, Nd+1] to signal Sb[Q, Nd+1] be digital output signal), and be sent to digital interface circuit DI and collect.According to the embodiment of the present invention, number P can equal 2 to support left and right two sound channels, and number Q also can equal 2.
As shown in Figure 1, converter DA[p] (wherein, p=1～P) each in comprises the unit U[p of serial connection, 1] to unit U[p, Nu] (wherein, the number of the unit of serial connection is Nu), be coupled to the unit U[p at end, Nu] digital and analog interface circuit I A[p], and be coupled to digital and analog interface circuit I A[p] digital simulation level (DAC stage) DAs[p].In one embodiment of the present invention, number N u can equal 3.Unit U[p, i] each in (wherein, i=1～Nu) can be to rise sampling filter, in order to increase sample frequency (sampling rate) (sampling rate).Converter DA[p] in each leading unit U[p, 1] can receive signal Sa[p, 0] (wherein, signal Sa[p, 0] be digital input signals), and the signal Sa[p that sample frequency is higher, 1 are correspondingly provided]; The unit U[p that each is follow-up, i] (wherein, i>1) can receive previous unit U[p, i-1] the signal Sa[p that provides of (not shown), i-1], and the signal Sa[p that sample frequency is higher, i are correspondingly provided].That is, signal Sa[p, 0] to signal Sa[p, Nu] respectively through the frequency interface of (Nu+1) individual different frequency, the cumulative frequency interface of sample frequency as individual in (Nu+1).Unit U[p, i] (wherein, i=1～Nu) sampling of liter can be after rising sampling signal Sa[p, i] the middle number that increases sampling, for example, can be in signal Sa[p, i-1] in two neighbouring samples between carry out interpolation, to make signal Sa[p, i] in unit interval number of samples be greater than signal Sa[p, i-1] in unit interval number of samples.Digital and analog interface circuit I A[p] can with and poor modulation carry out the unit U[p to end, Nu] the signal Sa[p that provides, Nu] modulate, to form the signal Sa[p after modulation, Nu+1] (wherein, signal Sa[p, Nu+1] be digital signal), digital simulation level DAs[p] can be by the signal Sa[p after modulation, Nu+1] be converted to signal Sa[p, Nu+2] (wherein, signal Sa[p, Nu+2] be analog output signal).
At each converter DA[p] unit U[p, 1] to unit U[p, Nu] in, across chip connecting circuit 111 with across chip connecting circuit 112 at signal Sa[p, ix] corresponding frequency interface is converter DA[p] be divided into the X1[p of branch] and with the X2[p of branch], wherein, sign (index) ix is a definite value of selecting in 1 to Nu.According to an embodiment of the invention, signal Sa[p, ix] sample frequency be signal Sa[p, 0] to signal Sa[p, ix-1] 4 to 16 times of sample frequency.Another embodiment according to the present invention, if the sign ix selecting is less than number N u, be formed at the X1[p of branch of chip 101] comprise unit U[p, 1] to unit U[p, ix], be formed at the X2[p of branch of chip 102] comprise unit U[p, ix+1] to unit U[p, Nu], digital and analog interface circuit I A[p], and digital simulation level DAs[p].If make it equal number N u during selection marker ix, the X1[p of branch] can comprise unit U[p, 1] to unit U[p, Nu], the X2[p of branch] comprise digital and analog interface circuit I A[p] with digital simulation level DAs[p].
As shown in Figure 1, converter AD[q] (wherein, q=1～Q) each in comprises the cells D [q of serial connection, 1] to cells D [q, Nd] (wherein, the number of the unit of serial connection is Nd), be coupled to leading cells D [q, 1] A/D interface circuit I D[q], and be coupled to A/D interface circuit I D[q] analog digital level (ADC stage) ADs[q].In one embodiment of the present invention, number N d can be set to number N u, and for example 3.Can integrate A/D interface circuit I D[q] with analog digital level ADs[q] with by coming modulation signal Sb[q, 0 with poor modulation], and signal Sb[q after modulation, 1 are correspondingly provided] (wherein, signal Sb[q, 1] be digital signal).Each in cells D [q, j] (wherein, j=1～Nd) can be changed different frequencies between two side frequency interfaces; For instance, each cells D [q, j] can be desampling fir filter, in order to reduce sample frequency (sampling rate).Converter AD[q] leading cells D [q, 1] can receive signal Sb[q, 1] and the signal Sb[q that sample frequency is lower, 2 are correspondingly provided], cells D [the q that each is follow-up, j] (wherein, j>1 and j<Nd) can receive the signal Sb[q that previous cells D [q, j-1] (not shown) provides, j], and correspondingly to follow-up cells D [q, j+1] (not shown), provide the signal Sb[q that sample frequency is lower, j+1].The cells D at end [q, Nd] can receive the signal Sb[q of previous cells D [q, Nd-1] (not shown), Nd], and the signal Sb[q that sample frequency is lower, Nd+1 are correspondingly provided].That is, signal Sb[q, 1] to signal Sb[q, Nd+1] respectively through the frequency interface of (Nd+1) individual different frequency, sample frequency as individual in (Nd+1) frequency interface decrescence.Cells D [q, j] (wherein, j=1～Nd) down-sampled can be at the signal Sb[q after down-sampled, j+1] the middle number that reduces sampling, for example, discardable signal Sb[q, j] in some samplings, make signal Sb[q, j+1] unit interval number of samples be less than signal Sb[q, j] unit interval number of samples.
At each converter AD[q] cells D [q, 1] to cells D [q, Nd] in, across chip connecting circuit 111 with across chip connecting circuit 112 at signal Sb[q, jx] corresponding frequency interface is converter AD[q] be divided into the Y1[q of branch] and with the Y2[q of branch], wherein, sign jx is a definite value of selecting in 1 to Nd.Correspondingly, if sign jx is greater than 1, be formed at the Y2[q of branch of chip 102] comprise analog digital level ADs[q], A/D interface circuit I D[q] with cells D [q, 1], to cells D [q, jx-1], be formed at the Y1[q of branch of chip 101] comprise cells D [q, jx] to cells D [q, Nd].If sign jx is chosen to be 1, be formed at the Y2[q of branch of chip 102] comprise analog digital level ADs[q] with A/D interface circuit I D[q], be formed at the Y1[q of branch of chip 101] comprise that cells D [q, 1] is to cells D [q, Nd].
Because each converter DA[p] at unit U[p, ix] with unit U[p, ix+1] between divided, signal Sa[p, ix] (can be considered across cell signal) Xu You X1[p of branch] unit U[p, ix] transfer to the X2[p of branch] unit U[p, ix+1].For reaching this signal, pass on, across chip connecting circuit 111, can arrange (arrange) X1[1 of branch] to the X1[P of branch] signal Sa[1, ix] to signal Sa[P, ix] in sampling, to form crossfire sf1[1] to crossfire sf1[K] (wherein, the number of crossfire is K), and pass through across the data ball pin Da[1 in chip connecting circuit 111] to data ball pin Da[K] difference transmission stream sf1[1] to crossfire sf1[K].According to the sequential of clock signal C K1, across chip connecting circuit 112, can pass through the data ball pin Db[1 across chip connecting circuit 112] to data ball pin Db[K] reception crossfire sf1[1] to crossfire sf1[K], and rearrange crossfire sf1[1] to crossfire sf1[K] in sampling, and correspondingly obtain converter DA[1] to converter DA[P] the X2[1 of branch] to the X2[P of branch] and signal Sa[1, ix] to signal Sa[P, ix].
Selectively, further can be according to the X1[1 of branch across chip connecting circuit 111] to the X1[P of branch] signal Sa[1, ix] to signal Sa[P, ix] and checking information (as error correction code (error correction code)) is attached to crossfire sf1[1] to crossfire sf1[K].When obtaining the X2[1 of branch across chip connecting circuit 112] to the X2[P of branch] signal Sa[1, ix] to signal Sa[P, ix] time, across chip connecting circuit 112 can be further by checking checking information, and the crossfire sf1[1 that detecting receives] to crossfire sf1[K] error; And if necessary and likely, according to checking information, proofread and correct crossfire sf1[1] to crossfire sf1[K].
In like manner, due to each converter AD[q] at cells D [q, jx-1] and D[q, jx] between divided, signal Sb[q, jx] (can be considered across cell signal) Xu You Y2[q of branch] cells D [q, jx-1] transfer to the Y1[q of branch] cells D [q, jx].For reaching this signal, pass on, across chip connecting circuit 112, can arrange the Y2[1 of branch] to the Y2[Q of branch] signal Sb[1, jx] to signal Sb[Q, jx] in sampling, to form crossfire se1[1] to crossfire se1[K] (wherein, the number of crossfire is K), and by the data ball pin Db[1 of chip 102] to data ball pin Db[K] difference transmission stream se1[1] to crossfire se1[K].By the data ball pin Da[1 of chip 101] to data ball pin Da[K], across chip connecting circuit 111, further can receive crossfire se1[1] to crossfire se1[K], and rearrange crossfire se1[1] to crossfire se1[K] in sampling, and correspondingly obtain converter AD[1] to converter AD[Q] the Y1[1 of branch] to the Y1[Q of branch] and signal Sb[1, jx] to signal Sb[Q, jx].
Selectively, further can be according to the Y2[1 of branch across chip connecting circuit 112] to the Y2[Q of branch] signal Sb[1, jx] to signal Sb[Q, jx] and checking information is attached to crossfire se1[1] to crossfire se1[K].When obtaining the Y1[1 of branch across chip connecting circuit 111] to the Y1[Q of branch] signal Sb[1, jx] to signal Sb[Q, jx] time, across chip connecting circuit 111 can be further by checking checking information, and the crossfire se1[1 that detecting receives] to crossfire se1[K] error; And if necessary and likely, according to checking information, proofread and correct crossfire se1[1] to crossfire se1[K].
In one embodiment, number K is less than number N u or number N d, therefore realizes the required pin number (being number K) of (P+Q) individual sound channel and can reduce.For instance, number K can be set to 1; That is, at the X1[1 of branch] to the X1[P of branch], the Y1[1 of branch] to the Y1[Q of branch] and the X2[1 of branch] to X2[P], the Y2[1 of branch] to the Y2[Q of branch] between required across the available single a pair of data ball pin Da[1 of chip signal transmission] with data ball pin Db[1] be achieved with a pair of clock signal ball pin B1 and clock signal ball pin B2.At number K, equal under 1 situation, can be by parallel signal Sa[1 across chip connecting circuit 111, ix] to signal Sa[P, ix] in sampling (checking information additional with selectivity) serialization (serialize) be single crossfire sf1[1], and by configuration to the single data ball pin Da[1 of signal processing system 100] transmit single crossfire sf1[1].For instance, across chip connecting circuit 111 signal transmission Sa[1 sequentially, ix] in each bit of a certain sampling (if adopt optionally error correcting function, by signal transmission Sa[1, ix] in a certain sampling transmit together with error correction code), be signal transmission Sa[2 sequentially again, ix] in each bit (and error correction code) of sampling of same sampling time point, by that analogy.Accordingly, can be by single data ball pin Db[1 across chip connecting circuit 112] receive single crossfire sf1[1], to crossfire sf1[1] in sampling carry out de-serialization (de-serialize), so that for converter DA[1] to converter DA[P] the X2[1 of branch] to the X2[P of branch] recover parallel signal Sa[1, ix] to signal Sa[P, ix].For instance, for example, across chip connecting circuit 112 available buffers (using flip-flop) at crossfire sf1[1] in the bit sequentially received, and whether the bit that counting is received is enough combined into a sampling (and error correction code), the bit that correspondingly group receives, so that for rebuilding parallel signal Sa[1, ix] to signal Sa[P, ix] the sampling (and error correction code, and each sampling is carried out error detecting and proofreaied and correct) of same sampling time point; So, signal Sa[1, ix] to signal Sa[P, ix] just can be transferred to the X2[1 of branch] to the X2[P of branch].
Vice versa, at number K, equal under 1 situation, can be by parallel signal Sb[1 across chip connecting circuit 112, jx] to signal Sb[Q, jx] in sampling (checking information additional with selectivity) be serialized as single crossfire se1[1], and by single data ball pin Db[1] transmission stream se1[1].As response, can be by single data ball pin Da[1 across chip connecting circuit 111] receive single crossfire se1[1], to crossfire se1[1] in sampling carry out de-serialization, so that for converter AD[1] to converter AD[Q] the Y1[1 of branch] to the Y1[Q of branch] recover parallel signal Sb[1, jx] to signal Sb[Q, jx].
(for example support complicated communication layers and agreement with needs, Slimbus) complicated circuit is compared, owing to needing to carry out simple function across chip connecting circuit 111 and across 112 of chip connecting circuit, for example data ordering with rearrange (and optionally error correction), therefore across chip connecting circuit 111 with across chip connecting circuit 112, can realize with quite simple circuit.Although signal Sa[1,0] to signal Sa[P, 0] can be the digital signal of pulse code modulation (PCM) (PCM, pulse-code modulation), signal Sa[1, ix] to signal Sa[P, ix] need not be the digital signal of pulse code modulation (PCM).
In an embodiment of the invention, clock signal C K1 is by being supplied to across chip connecting circuit 111 across chip connecting circuit 112; Clock signal C K1 is aligned in the chip 102Zhong X2[1 of branch] to the X2[P of branch] with the Y2[1 of branch] to the Y2[Q of branch] and sequential, therefore across the synchronous crossfire sf1[. of chip connecting circuit 112] with crossfire se1[.] with the X2[. of branch that aligns] and the Y2[. of branch] sequential.For meeting the X1[. of branch], the X2[. of branch], the Y1[. of branch] with the Y2[. of branch] time sequential routine, the clock rate of clock signal C K1, and crossfire sf1[1] to crossfire sf1[K] with crossfire se1[1] to crossfire se1[K] and handling capacity, can decide according at least one following factor: the value of number P and number Q, the value of number K, signal Sa[p, ix] and signal Sb[q, jx] in each sampling (with checking information) bit number, and signal Sa[p, ix] with signal Sb[q, jx] sample frequency.For instance, if if if the value of the larger number K of numerical value of number P and/or number Q is less and/or signal Sa[., ix] with signal Sb[., jx] sample frequency higher, the clock rate of clock signal C K1 also should arrange higher.Under the situation of number P=number Q=2, it should be technical suitably feasible that number K is set as to 1.Consider clock rate, if number P or number Q are greater than 2, number K can be configured to 2,3 or larger.That is,, while only adopting a pair of clock signal ball pin, number K can be (scalable) of changeable.
According to the liter sampling shown in Fig. 1 and down-sampled structure, signal Sa[p, i] frequency higher than signal Sa[p, i-1] frequency (wherein, i=1～Nu); On the other hand, signal Sb[q, j] frequency higher than signal Sb[q, j+1] frequency (wherein, j=1～Nd).The frequency interface of cutting apart by change (for example, selection marker ix from 1 to Nu, and/or from 1 to Nd selection marker jx) and/or pin number (number K), the present invention just can provide the elasticity of design, with what optimize signal processing system 100, always realizes cost.
Under the situation remaining unchanged in the value of number K, if the value of sign ix more approaches the value of number N u and/or sign jx, more approach 1, the circuit that will be realized by chip 101 (for example, more unit U[p, .] and D[q .]) more, the circuit that be realized by chip 102 is fewer; In addition, because the frequency interface of cutting apart is corresponding to the higher signal of sample frequency, data ball pin Da[1] to Da[K] and Db[1] to Db[K] handling capacity, together with the clock rate of clock signal C K1, also all needing increases.In chip 101, realize more multicircuit, cost and layout area all will increase, and connecting across chip at a high speed also can increase cost; Yet, because 102 of chips need be realized less circuit with less layout, can reduce costs again.The manufacturing technologies of manufacturing chip 101 and 102 employings also can affect the balance of cost, if chip 101 with the manufacturing of advanced small size technique, is realized more multicircuit extra layout area, not necessarily can significantly increase; On the other hand, if chip 102 with the manufacturing of ripe large scale technique, its effect reducing costs also can be influenced.In addition, the value of number K also can affect cost; Number K is increased, and the handling capacity and the clock rate that across chip, connect can reduce, and make cost, but larger number K also can increase pin number and across the complexity of chip wiring, this can reduce the impact of cost again.
Although the implementation cost with intuition estimating signal disposal system 100 is quite difficult, for the different choice of dividing frequency interface and number K, still can use the cost under computing machine accurate Calculation different choice.Cost under more various selections, just can adopt the selection that cost is minimum to carry out the actual signal processing system 100 that realizes.
Please refer to Fig. 2, Fig. 2 is according to the schematic diagram of the signal processing system 200 of embodiment of the present invention.Follow the structure shown in Fig. 1, chip 201 and chip 202 are crossed in the distribution of the signal processing system 200 in Fig. 2, and adopt three grades rise sampling for numeral to analog-converted, and three grades down-sampled for simulating to digital conversion, so number N u=number N d=3.Signal processing system 200 comprises converter DA[1] to converter DA[P] and converter AD[1] to converter AD[Q].Wherein, converter DA[1] to converter DA[P] be that digital analog converter and number are P; Converter AD[1] to converter AD[Q] be that analog-digital converter and number are Q.Each converter DA[p] (wherein, p=1～P) comprise for rising the unit U[p of sampling, 1] to unit U[p, 3], digital and analog interface circuit I A[p] with digital simulation level DAs[p].Each converter AD[q] (wherein, q=1～Q) comprise analog digital level ADs[q], A/D interface circuit I D[q], and for down-sampled cells D [q, 1] to cells D [q, 3].
Have digital interface circuit DI in chip 201, it is the signal Sa[1 of fs that frequency can be provided, 0] to signal Sa[P, 0], signal Sa[1 wherein, 0] to signal Sa[P, 0] be digital input signals.Signal Sa[p, 0] (wherein, p=1～P) is by unit U[p, 1] rise sampling, take the signal Sa[p that frequency is L*fs, 1 are provided]; That is, unit U[p, 1] the sampling operation that rises can be by signal Sa[p, 0] frequency f s be multiplied by factor L frequently.Similarly, unit U[p, 2] with unit U[p, 3] by rise sampling can provide respectively take advantage of factor M frequently and take advantage of factor N frequently, the signal Sa[p that therefore output frequency is L*M*fs respectively, 2] with frequency be L*M*N*fs signal Sa[p, 3].
At each converter AD[q] in, analog digital level ADs[q] with A/D interface circuit I D[q] can co-operating, receive signal Sb[q, 0] (wherein, signal Sb[q, 0] be analog input signal), and correspondingly provide the signal that a frequency is L*M*N*fs Sb[q, 1] (wherein, signal Sb[q, 1] be digital signal).Signal Sb[q, 1] can be down-sampled by cells D [q, 1], take the signal that a frequency is L*M*fs Sb[q, 2 are provided]; That is, the down-sampled operation of cells D [q, 1] is by signal Sb[q, 0] frequency L*M*N*fs divided by frequency elimination factor N.Similarly, cells D [q, 2] and D[q, 3] by down-sampled, can provide respectively frequency elimination factor M and frequency elimination factor L, the signal Sb[q that therefore output frequency is L*fs respectively, 3] with frequency be fs signal Sb[q, 4].
By selection marker ix, all equal 2 with sign jx and carry out splitting signal disposal system 200, and connect by selecting number K to equal 1 and set up across chip.Correspondingly, each converter DA[p] be segmented into the X1[p of branch] with the X2[p of branch], the X1[p of branch] with the X2[p of branch] by chip 201 and chip 202, realized respectively; Unit U[p, 1] with unit U[p, 2] be included in the X1[p of branch] in, unit U[p, 3] belong to the X2[p of branch].The X1[1 of branch] to the X1[P of branch] provide, signal Sa[1 that frequency is L*M*fs, 2] to signal Sa[P, 2], by across chip connecting circuit 211 and single a pair of data ball pin Da[1 across chip connecting circuit 212] with data ball pin Db[1] on single crossfire sf2, transfer to the X2[1 of branch] to the X2[P of branch].
Similarly, each converter AD[q] be segmented into the Y1[q of branch] with the Y2[q of branch], the Y1[q of branch] with the Y2[q of branch] by chip 201 and chip 202, realized respectively; Cells D [q, 2] is included in the Y1[q of branch with cells D [q, 3]] in, cells D [q, 1] belongs to the Y2[q of branch].The Y2[1 of branch] to the Y2[Q of branch] provide, signal Sb[1 that frequency is L*M*fs, 2] to signal Sb[Q, 2], by across chip connecting circuit 212 and single a pair of data ball pin Db[1 across chip connecting circuit 211] with data ball pin Da[1] on single crossfire se2, transfer to the Y1[1 of branch] to the Y1[Q of branch].Clock signal C K2 is transferred to the clock signal ball pin B1 of chip 201 by the clock signal ball pin B2 of chip 202, think that crossfire sf2 and crossfire se2 provide sequential.The handling capacity of the clock rate of clock signal C K2 and crossfire sf2 and crossfire se2 decides according to frequency L*M*fs, to meet bidirectional linked list, transmits signal Sa[1,2] to signal Sa[P, 2] and signal Sb[1,2] to signal Sb[Q, 2] desired sequential.
Please refer to Fig. 3, Fig. 3 is according to the schematic diagram of the signal processing system 300 of embodiment of the present invention.Similar with Fig. 2, the signal processing system 300 shown in Fig. 3 is crossed over chip 301 and chip 302, and comprises converter DA[1] to converter DA[P] and converter AD[1] to converter AD[Q].Wherein, converter DA[1] to converter DA[P] and be digital analog converter, converter AD[1] to converter AD[Q] be analog-digital converter.Each converter DA[p] (wherein, p=1～P) receive the signal Sa[p that sample frequency is fs, 0 by digital interface circuit DI], and comprise the unit U[p that rises sampling, 1] to unit U[p, 3], so the frequency signal Sa[p that is fs, 0] can be converted into the signal Sa[p that frequency is L*fs, 1], the signal Sa[p that frequency is L*M*fs, 2], and frequency be L*M*N*fs signal Sa[p, 3].Each converter AD[q] (wherein, q=1～Q) to signal Sb[q, 0] carry out intending to digital conversion with differential mode, and sample frequency is correspondingly provided is the signal Sb[q of L*M*N*fs, 1] (wherein, signal Sb[q, 1] be digital signal), and comprise that down-sampled cells D [q, 1] is to cells D [q, 3], thus frequency be L*M*N*fs signal Sb[q, 1] can be converted into the signal Sb[q that frequency is L*M*fs, 2], the signal Sb[q that frequency is L*fs, 3], and frequency be fs signal Sb[q, 4].
At number K, be all under 1 situation, one of difference of two embodiments shown in Fig. 2 and Fig. 3 is: the signal processing system 300 shown in Fig. 3 is segmented in signal Sa[p, 1] with signal Sb[q, 3] the associated frequency frequency interface that is L*fs.Correspondingly, each converter DA[p] be segmented into the X1[p of branch] with the X2[p of branch], the X1[p of branch] with the X2[p of branch] by chip 301 and chip 302, realized respectively; The X1[p of branch] comprise unit U[p, 1], the X2[p of branch] comprise unit U[p, 2] with unit U[p, 3].By across chip connecting circuit 311 and single a pair of data ball pin Da[1 across chip connecting circuit 312] with data ball pin Db[1] on single crossfire sf3, the X1[1 of branch] to the X1[P of branch] the signal Sa[1 that provides respectively, 1] to signal Sa[P, 1] (frequency is L*fs) can be transferred to the X2[1 of branch] to the X2[P of branch].
Similarly, each converter AD[q] be segmented into the Y1[q of branch] with the Y2[q of branch], the Y1[q of branch] with the Y2[q of branch] by chip 301Yu branch 302, realized respectively; The Y1[q of branch] comprise cells D [q, 3], the Y2[q of branch] comprise cells D [q, 2] and cells D [q, 1].By at single a pair of data ball pin Db[1] with data ball pin Da[1] on single crossfire se3, the Y2[1 of branch] to the Y2[Q of branch] the signal Sb[1 that provides respectively, 3] to signal Sb[Q, 3] (frequency is L*fs) can be transferred to the Y1[1 of branch] to the Y1[Q of branch].Clock signal C K3 is transferred to the clock signal ball pin B1 of chip 301 by the clock signal ball pin B2 of chip 302, think that crossfire sf3 and crossfire se3 provide sequential.
Two embodiments of comparison diagram 2 and Fig. 3, because signal processing system 200(is as shown in Figure 2) cut apart in the frequency interface of higher frequency L*M*fs, signal processing system 300(is as shown in Figure 3) cut apart in the frequency interface of lower frequency L*fs, clock signal C K2(is as shown in Figure 2) clock rate need be higher than clock signal C K3(as shown in Figure 3) clock rate.Crossfire sf2 and crossfire se2(are as shown in Figure 2) handling capacity also need be higher than crossfire sf3 and crossfire se3(as shown in Figure 3) handling capacity.Yet chip 302(is as shown in Figure 3) than chip 202(as shown in Figure 2) need more multicircuit to realize.
Please refer to Fig. 4, Fig. 4 is according to the schematic diagram of the signal processing system 400 of embodiment of the present invention.Similar with Fig. 2 and Fig. 3, chip 401 and chip 402 are crossed in the distribution of the signal processing system 400 shown in Fig. 4, and comprise converter DA[1] to converter DA[P] and converter AD[1] to converter AD[Q].Wherein, converter DA[1] to converter DA[P] and be digital analog converter, converter AD[1] to converter AD[Q] be analog-digital converter.Each converter DA[p] (wherein, p=1～P) receive the signal Sa[p that sample frequency is fs, 0 by digital interface circuit DI], and comprise the unit U[p that rises sampling, 1] to U[p, 3], so the frequency signal Sa[p that is fs, 0] can be converted into the signal Sa[p that frequency is L*fs, 1], the signal Sa[p that frequency is L*M*fs, 2], and frequency be L*M*N*fs signal Sa[p, 3].Each converter AD[q] (wherein, q=1～Q) to signal Sb[q, 0] carry out intending to digital conversion with differential mode, and sample frequency is correspondingly provided is the signal Sb[q of L*M*N*fs, 1], and comprise down-sampled cells D [q, 1] to cells D [q, 3], so the frequency signal Sb[q that is L*M*N*fs, 1] can be converted into the signal Sb[q that frequency is L*M*fs, 2], the signal Sb[q that frequency is L*fs, 3], and frequency be fs signal Sb[q, 4].
At number K, be all under 1 situation, one of difference of two embodiments shown in Fig. 2 to Fig. 4 is: Fig. 4 signal processing system 400 is segmented in signal Sa[p, 3] with signal Sb[q, 1] associated frequency is L*M*N*fs frequency interface.Correspondingly, each converter DA[p] be segmented into the X1[p of branch] with the X2[p of branch], the X1[p of branch] with the X2[p of branch] by chip 301 and chip 302, realized respectively; The X1[p of branch] comprise unit U[p, 1], unit U[p, 2] with unit U[p, 3], the X2[p of branch] comprise converter DA[p] remaining circuit, as digital simulation interface circuit IA[p] with digital simulation level DAs[p].By across chip connecting circuit 411 and single a pair of data ball pin Da[1 across chip connecting circuit 412] with data ball pin Db[1] on single crossfire sf4, the X1[1 of branch] to the X1[P of branch] the signal Sa[1 that provides respectively, 3] to signal Sa[P, 3] (frequency is L*M*N*fs) can be transferred to the X2[1 of branch] to the X2[P of branch].
Similarly, each converter AD[q] be segmented into the Y1[q of branch] with the Y2[q of branch], the Y1[q of branch] with the Y2[q of branch] respectively by chip 401 and 402 realizations; The Y1[q of branch] comprise that cells D [q, 1] is to cells D [q, 3], the Y2[q of branch] converter AD[q] and remaining circuit, as analog digital level ADs[q] with A/D interface circuit I D[q].By at single a pair of data ball pin Db[1] with data ball pin Da[1] on single crossfire se4, the Y2[1 of branch] to the Y2[Q of branch] the signal Sb[1 that provides respectively, 1] to signal Sb[Q, 1] (frequency is L*M*N*fs) can be transferred to the Y1[1 of branch] to the Y1[Q of branch].Clock signal C K4 is transferred to the clock signal ball pin B1 of chip 401 by the clock signal ball pin B2 of chip 402, think that crossfire sf4 and crossfire se4 provide sequential.
A plurality of embodiments of comparison diagram 2 to Fig. 4, because signal processing system 400(is as shown in Figure 4) cut apart in the frequency interface of higher frequency L*M*N*fs, signal processing system 300(is as shown in Figure 3) with signal processing system 200(as shown in Figure 2) divided in the frequency interface of lower frequency L*fs and frequency L*M*fs respectively, clock signal C K4(is as shown in Figure 4) clock rate need be higher than clock signal C K3(as shown in Figure 3) and clock signal C K2(as shown in Figure 2) clock rate.Crossfire sf4 and crossfire se4(are as shown in Figure 4) handling capacity also need be higher than crossfire sf3 and crossfire se3(as shown in Figure 3) handling capacity and crossfire sf2 and crossfire se2(as shown in Figure 2) handling capacity.Although chip 402(is as shown in Figure 4) circuit that need to realize is minimum, utilize across chip connecting circuit 411 with across chip connecting circuit 412, realize high speeds and be connected and may increase cost across chip.
In each embodiment of Fig. 2 to Fig. 4, converter DA[.] and converter AD[.] divided in the frequency interface of same frequency.In Fig. 2, each converter DA[p] and each converter AD[q] the divided frequency interface that is L*M*fs in frequency.In Fig. 3, each converter DA[p] and each converter AD[q] the divided frequency interface that is L*fs in frequency.In Fig. 4, each converter DA[p] and each converter AD[q] the divided frequency interface that is L*M*N*fs in frequency.Yet, converter DA[p] and converter AD[q] also can be divided in the frequency interface of different frequency.Please refer to Fig. 5 and Fig. 6, Fig. 5 is according to the schematic diagram of the signal processing system 500 of embodiment of the present invention; Fig. 6 is according to the schematic diagram of the signal processing system 600 of embodiment of the present invention.
Similar with Fig. 2 to Fig. 4, chip 501 and chip 502 are crossed in the distribution of the signal processing system 500 shown in Fig. 5, and comprise converter DA[1] to converter DA[P] and converter AD[1] to converter AD[Q].Wherein, converter DA[1] to converter DA[P] and be digital analog converter, converter AD[1] to converter AD[Q] be analog-digital converter.Each converter of each converter DA[p] (wherein, p=1～P) receive the signal Sa[p that sample frequency is fs, 0 by digital interface circuit DI], and comprise the unit U[p that rises sampling, 1] to unit U[p, 3], so the frequency signal Sa[p that is fs, 0] can be converted into the signal Sa[p that frequency is L*fs, 1], the signal Sa[p that frequency is L*M*fs, 2], and frequency be L*M*N*fs signal Sa[p, 3].Each converter AD[q] (wherein, q=1～Q) to signal Sb[q, 0] carry out intending to digital conversion with differential mode, and sample frequency is correspondingly provided is the signal Sb[q of L*M*N*fs, 1], and comprise down-sampled cells D [q, 1] to cells D [q, 3], so the frequency signal Sb[q that is L*M*N*fs, 1] can be converted into the signal Sb[q that frequency is L*M*fs, 2], the signal Sb[q that frequency is L*fs, 3], and frequency be fs signal Sb[q, 4].
At number K, be all under 1 situation, one of difference of each embodiment shown in Fig. 2 to Fig. 5 is: digital analog converter and the analog-digital converter of the signal processing system 500 shown in Fig. 5 are cut apart the frequency interface in different frequency.Each converter DA[p] cut apart in signal Sa[p, 1] the associated frequency frequency interface that is L*fs; Each converter AD[q] cut apart in signal Sb[p, 2] frequency interface of the associated frequency L*M*fs that is upper frequency.Correspondingly, each converter DA[p] be segmented into the X1[p of branch] with the X2[p of branch], the X1[p of branch] with the X2[p of branch] by chip 501 and chip 502, realized respectively; The X1[p of branch] comprise unit U[p, 1], the X2[p of branch] comprise unit U[p, 2] with unit U[p, 3].By across chip connecting circuit 511 and single a pair of data ball pin Da[1 across chip connecting circuit 512] with data ball pin Db[1] on single crossfire sf5, the X1[1 of branch] to the X1[P of branch] the signal Sa[1 that provides respectively, 1] to signal Sa[P, 1] (frequency is L*fs) can be transferred to the X2[1 of branch] to the X2[P of branch].
Similarly, each converter AD[q] be segmented into the Y1[q of branch] with the Y2[q of branch], the Y1[q of branch] with the Y2[q of branch] by chip 501 and chip 502, realized respectively; The Y1[q of branch] comprise cells D [q, 3] and cells D [q, 2], the Y2[q of branch] comprise cells D [q, 1].By at single a pair of data ball pin Db[1] with data ball pin Da[1] on single crossfire se5, the Y2[1 of branch] to the Y2[Q of branch] the signal Sb[1 that provides respectively, 2] to signal Sb[Q, 2] (frequency is L*M*fs) can be transferred to the Y1[1 of branch] to the Y1[Q of branch].Clock signal C K5 is transferred to the clock signal ball pin B1 of chip 501 by the clock signal ball pin B2 of chip 502, think that crossfire sf5 and crossfire se5 provide sequential.Sf5 compares with crossfire, because crossfire se5 needs the signal Sb[1 of the higher frequency of serial (frequency L*M*fs), 2] to signal Sb[Q, 2], therefore the frequency speed of clock signal C K5 can decide according to higher frequency L*M*fs, to meet the sequential demand of crossfire se5, its medium frequency L*M*fs is dividing frequency.On the other hand, crossfire sf5 only needs the signal Sa[1 of the lower frequency of serial (frequency L*fs), 1] to signal Sa[P, 1], so the sequential of crossfire sf5 can decide according to the frequency elimination result of clock signal C K5.
Similar with Fig. 2 to Fig. 5, the signal processing system 600 of Fig. 6 is integrated and is realized with chip 602 by chip 601, and comprises converter DA[1] to converter DA[P] and converter AD[1] to converter AD[Q].Wherein, converter DA[1] to converter DA[P] and be digital analog converter, converter AD[1] to converter AD[Q] be analog-digital converter.Each converter DA[p] (wherein, p=1～P) receive the signal Sa[p that sample frequency is fs, 0 by digital interface circuit DI], and comprise the unit U[p that rises sampling, 1] to unit U[p, 3], so the frequency signal Sa[p that is fs, 0] can be converted into the signal Sa[p that frequency is L*fs, 1], the signal Sa[p that frequency is L*M*fs, 2], and frequency be L*M*N*fs signal Sa[p, 3].Each converter AD[q] (wherein, q=1～Q) to signal Sb[q, 0] carry out intending to digital conversion with differential mode, and sample frequency is correspondingly provided is the signal Sb[q of L*M*N*fs, 1], and comprise down-sampled cells D [q, 1] to cells D [q, 3], so the frequency signal Sb[q that is L*M*N*fs, 1] can be converted into the signal Sb[q that frequency is L*M*fs, 2], the signal Sb[q that frequency is L*fs, 3], and frequency be fs signal Sb[q, 4].
At number K, be made as under 1 situation, one of difference of each embodiment shown in Fig. 2 to Fig. 6 is: the digital analog converter of the signal processing system 600 shown in Fig. 6 and analog-digital converter are cut apart respectively in higher and frequency interface lower frequency.Each converter DA[p] cut apart in signal Sa[p, 2] associated frequency is L*M*fs frequency interface; Each converter AD[q] cut apart in signal Sb[p, 3] the associated frequency L*fs frequency interface that is lower frequency.Correspondingly, each converter DA[p] be segmented into the X1[p of branch] with the X2[p of branch], the X1[p of branch] with the X2[p of branch] by chip 601 and chip 602, realized respectively; The X1[p of branch] comprise unit U[p, 1] with unit U[p, 2], the X2[p of branch] comprise unit and U[p, 3].By across chip connecting circuit 611 and single a pair of data ball pin Da[1 across chip connecting circuit 612] with data ball pin Db[1] on single crossfire sf6, the X1[1 of branch] to the X1[P of branch] the signal Sa[1 that provides respectively, 2] to signal Sa[P, 2] (frequency is L*fs) can be transferred to the X2[1 of branch] to the X2[P of branch].
Similarly, each converter AD[q] be segmented into the Y1[q of branch] with the Y2[q of branch], the Y1[q of branch] with the Y2[q of branch] by chip 601 and chip 602, realized respectively; The Y1[q of branch] comprise cells D [q, 3], the Y2[q of branch] comprise cells D [q, 1] and cells D [q, 2].By at single a pair of data ball pin Db[1] with data ball pin Da[1] on single crossfire se6, the Y2[1 of branch] to the Y2[Q of branch] the signal Sb[1 that provides respectively, 3] to signal Sb[Q, 3] (frequency is L*fs) can be transferred to the Y1[1 of branch] to the Y1[Q of branch].Clock signal C K6 is transferred to the clock signal ball pin B1 of chip 601 by the clock signal ball pin B2 of chip 602, think that crossfire sf6 and crossfire se6 provide sequential.Because crossfire sf6 needs the signal Sa[1 of the higher frequency of serial (frequency L*M*fs), 2] to signal Sa[P, 2], so the clock frequency of clock signal C K6 can decide according to higher frequency L*M*fs, to meet the sequential demand of crossfire sf6, its medium frequency L*M*fs is dividing frequency.On the other hand, crossfire se6 only needs the signal Sb[1 of the lower frequency of serial (frequency L*fs), 3] to signal Sb[Q, 3], so the sequential of crossfire se6 can decide according to the frequency elimination result of clock signal C K6.
From Fig. 2 to Fig. 4 and Fig. 5 to Fig. 6, by converter DA[p] be segmented into the frequency of the frequency interface of two branches, and by converter AD[q] being segmented into the frequency of the frequency interface of two branches, these two frequencies can equate or be different.That is, because of each converter DA[p] divided in signal Sa[p, ix] frequency interface, each converter AD[q] divided in signal Sb[q, jx] frequency interface, so signal Sa[p, ix] with signal Sb[q, jx] frequency can be identical or different.In the embodiment of Fig. 2 to Fig. 4, signal Sa[p, ix] with signal Sb[q, jx] frequency identical; And in the embodiment of Fig. 5 and Fig. 6, signal Sa[p, ix] with signal Sb[q, jx] frequency different.As Fig. 5 and Fig. 6 discuss, if signal Sa[p, ix] with signal Sb[q, jx] be selected as the signal of different frequency, across the clock rate of the clock signal of chip crossfire, can be depending on higher frequency in two frequencies.
Please refer to Fig. 7, Fig. 7 is according to the schematic diagram of the signal processing system 700 of embodiment of the present invention.Similar to the embodiment shown in Fig. 1, signal processing system 700 distributes and crosses over chip 701 and chip 702, and comprise converter DAe[1] to converter DAe[P], converter ADe[1] to converter ADe[Q], and be formed at respectively in chip 701 and chip 702 across chip connecting circuit 711 with across chip connecting circuit 712.Wherein, converter DAe[1] to converter DAe[P] be that digital analog converter and number are P; Converter ADe[1] to converter ADe[Q] be that analog-digital converter and number are Q.Chip 701 has the data ball pin Da[1 that number is K] to data ball pin Da[K] and clock signal ball pin B1, data ball pin Da[1] to data ball pin Da[K] be respectively coupled to chip 702 data ball pin Db[1 with clock signal ball pin B1] to data ball pin Db[K] and clock signal ball pin B2, the number of the data ball pin of its chips 702 is identical with the number of the data ball pin of chip 701.
In signal processing system 700, each converter DAe[p] (wherein, p=1～P) can be and differ from digital analog converter, this and poor digital analog converter can be by signal Sa[p, 0] be converted to signal Sa[p, Nu+2] (wherein, signal Sa[p, 0] be digital input signals, signal Sa[p, Nu+2] be analog output signal), and comprise that number is the unit U[p of frequency inverted of the serial connection of Nu, 1] to unit U[p, Nu], digital and analog interface circuit I A[p], digital simulation level DAs[p], code level Ea[p] with decode stage Ga[p].Unit U[p, 1] can the digital interface circuit DI in chip 701 receive signal Sa[p, 0], and be follow-up unit U[p, 2] (not shown) provide the signal rising after sampling Sa[p, 1]; Similarly, the unit U[p that each is follow-up, i] (wherein, i>1) can receive previous unit U[p, i-1] the signal Sa[p that provides of (not shown), i-1] (not shown), and provide frequency higher rise sampled signal Sa[p, i] (not shown).Digital and analog interface circuit I A[p] can with and poor modulation carry out the unit U[p to end, Nu] the signal Sa[p that provides, Nu] modulate, to form the signal Sa[p after modulation, Nu+1] (wherein, signal Sa[p, Nu+1] be digital signal), digital simulation level DAs[p] can be by the signal Sa[p after modulation, Nu+1] be converted to signal Sa[p, Nu+2] (wherein, signal Sa[p, Nu+2] be analog output signal).
Each converter DAe[p] be split into the X1e[p of branch] with the X2e[p of branch], the X1e[p of branch] with the X2e[p of branch] be formed at respectively in chip 701 and chip 702.The sign ix that utilization is selected from 1 to Nu, the X1e[p of branch] comprise unit U[p, 1] to unit U[p, ix] and with code level Ea[p], wherein, code level Ea[p] be coupled to unit U[p, ix] and across between chip connecting circuit 711.The X2e[p of branch] comprise unit U[p, ix+1] to unit U[p, Nu], digital and analog interface circuit I A[p], digital simulation level DAs[p] with decode stage Ga[p]; Wherein, decode stage Ga[p] be coupled to across chip connecting circuit 712 and unit U[p, ix+1] between.
For reaching converter DA[p] translation function, by the X1e[p of branch] unit U[p, ix] the signal Sa[p that provides, ix] need across chip transfer to the X2e[p of branch] unit U[p, ix+1].For passing on signal Sa[p, ix], each converter DAe[p] code level Ea[p] can be to signal Sa[p, ix] encode, so that coded signal sc1[p to be provided].For instance, code level Ea[p] can be by signal Sa[p, ix] in each sample code be coded signal sc1[p] in corresponding coded word (encoded word).Correspondingly, across the chip connecting circuit 711Ke Jiang X1e[1 of branch] to the X1e[P of branch] coded signal sc1[1] to coded signal sc1[P] and in coded word gathered (collectively) and arranged, take and form the crossfire sf7[1 that number is K] to crossfire sf7[K], and by data ball pin Da[1] to data ball pin Da[K] transmission stream sf7[1] to crossfire sf7[K].Can be to providing clock signal C K7 across chip connecting circuit 711 across chip connecting circuit 712; Under the sequential control of clock signal C K7, across chip connecting circuit 712, can pass through data ball pin Db[1] to data ball pin Db[K] reception crossfire sf7[1] to crossfire sf7[K], to the crossfire sf7[1 receiving] to crossfire sf7[K] rearrange coded word, and correspondingly obtain coded signal sc1[1] to coded signal sc1[P].Therefore, each decode stage Ga[p] (wherein, p=1～P) just can be to associated coded signal sc1[p] carry out decoding, think follow-up unit U[p, ix+1] obtain signal Sa[p, ix].For example, decoding coded signal sc1[p] in each coded word, to obtain signal Sa[p, ix] in sampling.
For sign, ix is chosen to be the special case of Nu, the X1e[p of branch] possess unit U[p, 1] to unit U[p, Nu], and comprise code level Ea[p], code level Ea[p] can be to unit U[p, Nu] the signal Sa[p that provides, Nu] encode, to form coded signal sc1[p].At the X2e[p of branch] in decode stage Ga[p] and digital and analog interface circuit I A[p] between in without any unit U[p, i]; Decode stage Ga[p] to the coded signal sc1[p obtaining across chip connecting circuit 712] carry out decoding, think digital and analog interface circuit I A[p] obtain signal Sa[p, Nu], thus digital and analog interface circuit I A[p] with digital simulation level DAs[p] can continue to form signal Sa[p, Nu+2].
In signal processing system 700, each converter ADe[q] (wherein, q=1～Q) can be and differ from analog-digital converter, can be by signal Sb[q, 0] be converted to signal Sb[q, Nd+1] (wherein, signal Sb[q, 0] be analog input signal, signal Sb[q, Nd+1] be digital output signal), and comprise that number is the cells D [q of frequency inverted of the serial connection of Nd, 1] to cells D [q, Nd], A/D interface circuit I D[q], analog digital level ADs[q], code level Eb[q] with decode stage Gb[q].For response signal Sb[q, 0], analog digital level ADs[q] with A/D interface circuit I D[q] co-operating, with by intending forming to digital conversion the signal Sb[q of high sample frequency, 1 with differential mode] (wherein, signal Sb[q, 1] be digital signal).Cells D [q, 1] can receive signal Sb[q, 1], and be that follow-up cells D [q, 2] (not shown) provides down-sampled signal Sb[q, 2]; Similarly, each follow-up cells D [q, j] (wherein, j<1) can receive the signal Sb[q that previous cells D [q, j-1] (not shown) provides, j] (not shown), and provide down-sampled signal Sb[q, j+1] (not shown), so the cells D [q at end, Nd] can provide signal Sb[q, Nd+1 to digital interface circuit DI].
Each converter ADe[q] be split into the Y1e[q of branch] with the Y2e[q of branch], the Y1e[q of branch] with the Y2e[q of branch] be formed at respectively in chip 701 and chip 702.The sign jx that utilization is selected from 1 to Nd, the Y2e[q of branch] comprise A/D interface circuit I D[q], analog digital level ADs[q], cells D [q, 1] is to cells D [q, jx-1] and code level Eb[q]; Wherein, code level Eb[q] be coupled to cells D [q, jx-1] and across between chip connecting circuit 712.The Y1e[q of branch] comprise that cells D [q, jx] is to cells D [q, Nd], and decode stage Gb[q]; Wherein, decode stage Gb[q] be coupled to across between chip connecting circuit 711 and cells D [q, jx].
For reaching converter Ad[q] translation function, by the Y2e[q of branch] the signal Sb[q that provides of cells D [q, jx-1], jx] need by across chip transfer to the Y1e[q of branch] cells D [q, jx].For transmitting signal Sb[q, jx], each converter ADe[q] code level Eb[q] can be to signal Sb[q, jx] encode, so that coded signal sc2[q to be provided]; For example,, by signal Sb[q, jx] in each sample code be coded signal sc2[q] in coded word.Correspondingly, across the chip connecting circuit 712Ke Jiang Y2e[1 of branch] to the Y2e[Q of branch] converter ADe[Q] and coded signal sc2[1] to coded signal sc2[Q] and in coded word gathered arrangement, to form K crossfire se7[1 of number] to crossfire se7[K], and by data ball pin Db[1] to data ball pin Db[K] difference transmission stream se7[1] to crossfire se7[K].Across chip connecting circuit 711, can pass through data ball pin Da[1] to data ball pin Da[K] reception crossfire se7[1] to crossfire se7[K], to the crossfire se7[1 receiving] to crossfire se7[K] rearrange coded word, and correspondingly obtain coded signal sc2[1] to coded signal sc2[Q].Therefore, each decode stage Gb[q] (wherein, q=1～Q) just can be to associated coded signal sc2[q] carry out decoding, think that follow-up cells D [q, jx] obtains signal Sb[q, jx].
For sign, jx is chosen to be 1 special case, the Y2e[q of branch] at A/D interface circuit I D[q] and code level Eb[q] between do not have any cells D [q, j], code level Eb[q] to analog digital level ADs[q] with A/D interface circuit I D[q] signal Sb[q, 1] encode, so that coded signal sc2[q to be provided].The Y1e[q of branch] comprise that cells D [q, 1] is to D[q, Nd] and decode stage Gb[q], it can be to the coded signal sc2[q obtaining across chip connecting circuit 711] carry out decoding, think that leading cells D [q, 1] forms signal Sb[q, 1].
Code level Ea[p] with decode stage Ga[p] and code level Eb[q] with decode stage Gb[q] the encoding and decoding mechanism that adopts can comprise: data compression (compression) and decompress (decompression), data scrambling (scrambling) and solution scrambling (de-scrambling), and/or other coding-decoding schemes, for example: by shining upon each sampling to character maximum or least bits conversion, encode, and by reflection, penetrate (inverse mapping) and carry out decoding.Data compression and decompression can be the encoding and decoding based on length of flow (run-length), and/or Huffman (Huffman) encoding and decoding etc., so that signal Sa[p, ix] or signal Sb[q, jx] in each sampling can be encoded as the less coded word of bit.Code level Ea[p] with decode stage Ga[p] the encoding and decoding mechanism and the code level Eb[q that adopt] and decode stage Gb[q] the encoding and decoding mechanism that adopts can be identical or different.
Utilize code level Ea[p], decode stage Ga[p], code level Eb[q] with decode stage Gb[q], the clock rate of clock signal C K7 and crossfire sf7[1] to crossfire sf7[K] with crossfire se7[1] to crossfire se7[K] and handling capacity can decide according at least one factor: the value of the value of number P and Q, number K, coded signal sc1[p] and coded signal sc2[q] in the bit number of each coded word (with checking information), and signal Sa[p, ix] with signal Sb[q, jx] sample frequency.For instance, consider two embodiments of Fig. 1 and Fig. 7, suppose that two number P, number Q, number N u, number N d in embodiment are identical with number K, if code level Ea[p] and code level Eb[q] adopt data compression to come signal Sa[p, ix] and signal Sb[q, jx] in each sampling encode with in coded signal sc1[p] with coded signal sc2[q] in the shorter coded word of formation, clock signal C K7(is as shown in Figure 7) clock rate can set for lower than clock signal C K1(as shown in Figure 1) clock rate.Although lower clock rate can reduce the cost of realizing of signal processing system 700, the extra layout area of setting up code level and decode stage may reduce the benefit of cost.Assess the cost and estimate that can calculate encoding and decoding can really make cost reduction or increase.
Please refer to Fig. 8; Fig. 8 is according to the schematic diagram of the signal processing system 800 of embodiment of the present invention.Coordinate number N u=number N d=3 and a group selection (ix, jx, K)=(1,3,1), the signal processing system 800 shown in Fig. 8 can be in order to illustrate the framework in Fig. 7.Chip 801 and chip 802 are crossed in the distribution of signal processing system 800, and comprise converter DAe[1] to converter DAe[P], converter ADe[1] to converter ADe[Q].Wherein, converter DAe[1] to converter DAe[P] be digital analog converter; Converter ADe[1] to converter ADe[Q] be analog-digital converter.Each converter DAe[p] (wherein, p=1～P) receive signal Sa[p, 0 by digital interface circuit DI] (wherein, signal Sa[p, 0] be digital input signals), and comprise the unit U[p that rises sampling, 1] to unit U[p, 3], therefore signal Sa[p, 0] can sequentially be converted into signal Sa[p, 1 by rising sampling], signal Sa[p, 2] with signal Sa[p, 3]; For instance, signal Sa[p, 0], signal Sa[p, 1], signal Sa[p, 2] with signal Sa[p, 3] sample frequency can be respectively fs, L*fs, L*M*fs and L*M*N*fs.Each converter ADe[q] (wherein, q=1～Q) to signal Sb[q, 0] (wherein, signal Sb[q, 0] be analog input signal) carry out intending to digital conversion with differential mode, and signal Sb[q is correspondingly provided, 1] (wherein, signal Sb[q, 1] be digital signal), and comprise that down-sampled cells D [q, 1] is to cells D [q, 3], therefore signal Sb[q, 1] can sequentially be converted into signal Sb[q, 2], signal Sb[q, 3] with signal Sb[q, 4]; For instance, signal Sb[q, 1], signal Sb[q, 2], signal Sb[q, 3] with signal Sb[q, 4] frequency can be respectively L*M*N*fs, L*M*fs, L*fs and fs.
Signal processing system 800 divided in signal Sa[p, 1] and Sb[q, 3] associated frequency interface.Correspondingly, each converter DAe[p] by across chip connecting circuit 811 with across chip connecting circuit 812, be divided into the X1e[p of branch] with the X2e[p of branch], wherein, across chip connecting circuit 811 with across chip connecting circuit 812, be formed at respectively chip 801 and chip 802.The X1e[p of branch] be formed in chip 801, comprise unit U[p, 1] and code level Ea[p].Unit U[p, 1] can provide signal Sa[p, 1]; Code level Ea[p] in order to signal Sa[p, 1] encode, to form coded signal sc1[p].The X2e[p of branch] be formed in chip 802, comprise decode stage Ga[p] and unit U[p, 2] to unit U[p, 3].Decode stage Ga[p] for decoding coded signal sc1[p] to obtain signal Sa[p, 1]; Number K is selected is set as 1, across the chip connecting circuit 811Ke Jiang X1e[1 of branch] to the X1e[P of branch] coded signal sc1[1] to coded signal sc1[P] be serialized as single crossfire sf8, and by the single data ball pin Da[1 of chip 801] transfer out.Clock signal C K8 can be transferred to by the clock signal ball pin B2 of chip 802 the clock signal ball pin B1 of chip 801, under the sequential control of clock signal C K8, across chip connecting circuit 812, can pass through the single data ball pin Db[1 of chip 802] reception crossfire sf8, and crossfire sf8 is separated to serial, to obtain coded signal sc1[1] to coded signal sc1[P].
Similarly, each converter ADe[q] be segmented into the Y1e[q of branch] with the Y2e[q of branch], by chip 801 and chip 802, realized respectively.The Y2e[q of branch] comprise cells D [q, 2], cells D [q, 1] and code level Eb[q]; Code level Eb[q] can be to signal Sb[q, 3] coding, to form coded signal sc2[q].Across the chip connecting circuit 812Ke Jiang Y2e[1 of branch] to the Y2e[Q of branch] coded signal sc2[1] to coded signal sc2[Q] be serialized as single crossfire se8, and by the single data ball pin Db[1 of chip 802] transfer out.Across chip connecting circuit 811, can pass through the single data ball pin Da[1 of chip 801] receive crossfire se8, to crossfire, se8 separates serial, to obtain coded signal sc2[1] to coded signal sc2[Q].The Y1e[q of branch] comprise decode stage Gb[q] with cells D [q, 3]; Decode stage Gb[q] can be to coded signal sc2[q] carry out decoding, to obtain signal Sb[q, 3].
Be not limited to the example of Fig. 8, the setting that suitably changes Fig. 7 framework is selected, code level Ea[p], code level Eb[q] with decode stage Ga[p], decode stage Gb[q] also can be included in the example of Fig. 2 to Fig. 6.
Although two chips are crossed in the distribution of each signal processing system of Fig. 1 to Fig. 8, signal processing system of the present invention also can be distributed in more multi-chip, for example three chips.For instance, each converter DA[p] can be split into the X1[p of branch], the X2[p of branch] with the X3[p of branch], be formed at respectively three chip (not shown); The X1[p of branch] comprise unit U[p, 1] to unit U[p, ix1], the X2[p of branch] comprise unit U[p, ix1+1] to unit U[p, ix2], the X3[p of branch] comprise unit U[p, ix2+1] to unit U[p, Nu], digital and analog interface circuit I A[p] with digital simulation level DAs[p].By unit U[p, ix] output signal by first, across chip connecting circuit and second, across chip connecting circuit (being formed at respectively the first chip and the second chip), transfer to unit U[p, ix1+1]; By unit U[p, ix2] output signal by the 3rd, across chip connecting circuit and the 4th, across chip connecting circuit (being formed at respectively the second chip and the 3rd chip), transfer to unit U[p, ix2+1].
According to the embodiment of the present invention, a kind of signal processing method is provided, comprise: arrange a plurality of converters (as converter DA[1] to converter DA[P] and/or converter AD[1] to converter AD[Q]), each converter (as converter DA[p] or converter AD[q]) is split into the first branch of being formed in the first chip (as the X1[p of branch] or the Y1[q of branch]) and is formed at the second branch in the second chip (as the X2[p of branch] or the Y2[q of branch]), and by form with the first chip in first across chip connecting circuit be formed at second in the second chip across chip connecting circuit, between the first branch of each converter and the second branch, transmit this M signal (as signal Sa[p, ix] or signal Sb[q, jx]).Wherein, each converter receives input signal, and correspondingly provides output signal by the conversion between digital signal and simulating signal; The sample frequency of one of them converted input signal of the first branch and the second branch, to provide the M signal of different sample frequency.
Please refer to the 9th figure, Fig. 9 is for optimizing the design cycle of embodiment of the present invention.Flow process 900 can in order to determine as how more excellent cost realize distributed signal disposal system; For example, how to design or produce signal processing system as shown in Figure 1 100 or the signal processing system as shown in Figure 7 700 that cost is minimum.The key step of flow process 900 can be described below.
Step 902: arrange a plurality of converters that can change between simulating signal and digital signal, and each converter is associated with the frequency interface of a plurality of different frequencies.Specifically, determine the basis of signal processing system, comprise: the number of converter in signal processing system (as the number Q of the number P of digital analog converter in Fig. 1 or Fig. 7 and analog-digital converter), and the number that each converter comprises frequency translation unit (for example, unit U[p in each digital analog converter as shown in Fig. 1 or Fig. 7, i] number N u and each analog-digital converter in the number N d of cells D [q, j]).In addition, determine which kind of technique the first chip and the second chip that in signal processing system, distribute adopt respectively make.Utilize frequency translation unit, each digital analog converter and analog-digital converter are associated with the frequency interface of a plurality of different frequencies.
Step 904: initialization is used to indicate the selection that wherein each converter (analog-digital converter and digital analog converter) is divided into the first branch and the second branch, and this selects indication will be how between the first paired branch and the second branch, to set up and be connected across chip.For instance, this selection can comprise the setting selection of sign ix as shown in Fig. 1 or Fig. 7, sign jx and number K.This selection also can comprise whether in each digital analog converter and analog-digital converter, adding the setting of code level/decode stage to select; That is, in this selection, also can indicate and adopt which in the structure shown in Fig. 1 and Fig. 7.
Step 906: according to the selection of previous step, cut apart converter step, to obtain following plan.This is designed for selected frequency interface place in each converter each converter is divided into the first branch in the first chip and the second branch in the second chip, and at number, is K across utilizing suitable clock rate and handling capacity that the first all branches and the second branch are communicated under chip wiring.In addition, this plan also can comprise: embedded coding level/decode stage whether, and embedded coding level/decode stage how.
Step 908: use computing machine, carry out cost estimating step, to calculate the required total cost of following item: form all the first branches in the first chip, in the second chip, form all the second branches, and the number K of take in aforementioned selection as realizing, is connected across chip in the signal transmission between all the first branches and the second branch.
Step 910: if still there is another kind of different selection, repeating step 906 correspondingly, otherwise go to step 912.Therefore, step 906 just can repeat several to obtain several costs with step 908, and each cost is to calculate under a different selection.For different selections is provided, can carry out following one or more operation: change the selected dividing frequency interface of each digital analog converter and/or each analog-digital converter (for example, changing sign ix and/or jx), and the value that changes number K.For instance, the selection that the embodiment shown in Fig. 2 to Fig. 6 is corresponding (ix, jx, K)=(2,2,1), (1,3,1), (3,1,1), (1,2,1) and (2,3,1).Therefore, step 906 can repeat five times with step 908, obtains five costs.Different selections also can comprise: select in two kinds of structures shown in Fig. 1 and Fig. 7; Thereby the cost of structural correspondence and the cost of the structural correspondence shown in Fig. 7 shown in assessment comparison diagram 1.
Step 912: after repeating step 906 and step 908, the various costs that relatively calculate, then carry out cost compare by computing machine, realize the selection of cost to select optimum (minimum).For instance, design cycle 900 can be three kinds of selections of Fig. 2 to Fig. 4 and calculates three corresponding costs, if (ix, the jx of Fig. 2, K) selection can correspond to minimum cost, just can adopt the selection of Fig. 2 to realize conversion between three grades of numerals that rise sampling/down-sampled and simulation.
In a word, the present invention, by utilizing and differing from digital-to-analogue conversion and sample with down-sampled with the multistage liter that differential mode is intended under digital conversion, provides enough dirigibilities, the signal processing system in order to optimization across chip distribution.The balance of better (or best) can for example, be reached in this kind of optimization between various influence factors (, across chip handling capacity and clock rate, layout area, pin number (ball pin number) and manufacture the technique of chip).
Although the present invention discloses as above with better embodiment, yet must understand it not in order to limit the present invention.On the contrary, any those skilled in the art, without departing from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention should be as the criterion with the protection domain that claims were defined.
Claims (23)
1. a signal processing system, is characterized in that, distributes and crosses over the first chip and the second chip, and this signal processing system comprises:
First across chip connecting circuit, be formed in this first chip,
Second across chip connecting circuit, and be formed in this second chip, and be coupled to this first across chip connecting circuit, and
A plurality of converters of changing between digital signal and simulating signal; Arbitrary converter in the plurality of converter comprises:
A plurality of unit that form the serial connection of a plurality of frequency interface, different frequency interface is associated with different frequency respectively, and the inversion frequency between two continuous side frequency interfaces of the arbitrary unit in the plurality of unit;
Wherein, this first second is divided into first branch and second branch at the corresponding frequency interface place of this arbitrary converter by this arbitrary converter across chip connecting circuit across chip connecting circuit with this, this of this arbitrary converter the first branch and this second branch are formed at respectively in this first chip and this second chip, and this first across chip connecting circuit and this second across chip connecting circuit signal transmission between this first branch of arbitrary converter and this second branch.
2. signal processing system according to claim 1, is characterized in that, the plurality of converter comprises digital analog converter, and this digital analog converter is converted to analog output signal by digital input signals, and this digital analog converter further comprises:
Digital and analog interface circuit, is coupled to the unit at the end of this digital analog converter, and
Digital simulation level, couples this digital and analog interface circuit;
Wherein, the leading unit in this digital analog converter receives this digital input signals and first signal is correspondingly provided; Arbitrary unit after this leading unit receives the signal that previous unit provides; The signal that this digital and analog interface circuit is used and poor modulation provides the unit at this end is modulated, and to form the signal after modulation, and this digital simulation level is converted to this analog output signal by the signal after this modulation.
3. signal processing system according to claim 2, is characterized in that,
The sample frequency of this first signal is higher than the sample frequency of this data input signal; And
The sample frequency of the signal that the sample frequency of the signal that this arbitrary unit after this leading unit provides provides than this previous unit is high.
4. signal processing system according to claim 1, is characterized in that, the plurality of converter comprises analog-digital converter, and this analog-digital converter is converted to digital output signal by analog input signal, and this analog-digital converter further comprises:
A/D interface circuit, is coupled to the leading unit of this analog-digital converter, by providing secondary signal after modulation to respond this analog input signal with poor modulation;
Wherein, this leading unit in this analog-digital converter receives this secondary signal and the 3rd signal is correspondingly provided; Arbitrary unit between the unit at this leading unit and end receives the signal that its corresponding previous unit provides, and correspondingly to follow-up unit, provides signal; And the unit at this end receives the signal that the previous unit of its correspondence provides and this digital output signal is correspondingly provided.
5. signal processing system according to claim 4, is characterized in that,
The sample frequency of the 3rd signal is lower than the sample frequency of this secondary signal;
The sample frequency of the signal that the sample frequency of the signal that this arbitrary unit after this leading unit provides provides than the previous unit of its correspondence is low; And
The sample frequency of the signal that the sample frequency of this digital output signal that the unit at this end provides provides than the previous unit of its correspondence is low.
6. signal processing system according to claim 1, is characterized in that:
The plurality of converter comprises a plurality of first kind converters, the arbitrary first kind converter in the plurality of first kind converter provide from the first branch of this arbitrary first kind converter transfer to the second branch first across cell signal;
This first arranges a plurality of first across the sampling in cell signal across chip connecting circuit, to form a plurality of the first crossfires, and first across a plurality of the first data ball pin in chip connecting circuit, transmits respectively the plurality of the first crossfire by this; And
By this second across a plurality of the second data ball pin that couple with the plurality of the first data ball pin respectively in chip connecting circuit, this second receives the plurality of the first crossfire across chip connecting circuit, rearrange the sampling in the plurality of the first crossfire, and correspondingly for a plurality of second branches of the plurality of first kind converter obtain the plurality of first across cell signal.
7. signal processing system according to claim 6, is characterized in that:
This first is further attached to checking information across cell signal the plurality of the first crossfire across chip connecting circuit according to the plurality of first, and
When this second obtains the plurality of first during across cell signal across chip connecting circuit, this second further proofreaies and correct received the plurality of the first crossfire according to this checking information across chip connecting circuit.
8. signal processing system according to claim 6, is characterized in that, the number of the plurality of first kind converter is the first number; The number of the plurality of second branch of the plurality of first kind converter is this first number; The the plurality of first number across cell signal is this first number; The number of the plurality of the first data pin ball is the 3rd number; The number of the plurality of the second number pin ball is the 3rd number; The number of the plurality of the first crossfire is the 3rd number.
9. signal processing system according to claim 8, is characterized in that, the 3rd number is less than this first number.
10. signal processing system according to claim 6, is characterized in that:
Arbitrary first kind converter in the plurality of first kind converter further comprises:
The first code level, is located in the first branch of this arbitrary first kind converter, and
The first decode stage, is located in the second branch of this arbitrary first kind converter;
Wherein, this first code level of this arbitrary first kind converter first is encoded across cell signal to this of this arbitrary first kind converter, so that the first coded signal to be provided;
This first arranges a plurality of first coded signals of the plurality of first kind converter across chip connecting circuit, to form the plurality of the first crossfire,
This second rearranges the plurality of the first crossfire across chip connecting circuit, and correspondingly for the plurality of second branch of the plurality of first kind converter obtains the plurality of the first coded signal, and,
This first decode stage of this arbitrary first kind converter carries out decoding to corresponding the first coded signal, and this second branch that thinks this arbitrary first kind converter obtains this first across cell signal.
11. signal processing systems according to claim 10, is characterized in that, the number of the plurality of first kind converter is the first number; The number of the plurality of second branch of the plurality of first kind converter is this first number; The the plurality of first number across cell signal is this first number; The number of the plurality of the first coded signal is this first number; The number of the plurality of the first data pin ball is the 3rd number; The number of the plurality of the second number pin ball is the 3rd number; The number of the plurality of the first crossfire is the 3rd number.
12. signal processing systems according to claim 6, is characterized in that:
The plurality of converter further comprises a plurality of Equations of The Second Kind converters, the arbitrary Equations of The Second Kind converter in the plurality of Equations of The Second Kind converter provide from the second branch of this arbitrary Equations of The Second Kind converter transfer to the first branch second across cell signal,
This second arranges a plurality of second across the sampling in cell signal across chip connecting circuit, to form a plurality of the second crossfires; This second further transmits respectively the plurality of the second crossfire by the plurality of the second data ball pin across chip connecting circuit, and
This first further receives the plurality of the second crossfire by the plurality of the first data ball pin across chip connecting circuit, and rearrange the sampling in the plurality of the second crossfire, and correspondingly for a plurality of first branches of the plurality of Equations of The Second Kind converter obtain respectively the plurality of second across cell signal.
13. signal processing systems according to claim 12, is characterized in that:
This second is further attached to the second checking information across cell signal the plurality of the second crossfire across chip connecting circuit according to the plurality of second, and
When this first obtains the plurality of second during across cell signal across chip connecting circuit, this first further proofreaies and correct received the plurality of the second crossfire according to this second checking information across chip connecting circuit.
14. signal processing systems according to claim 12, is characterized in that, the number of this Equations of The Second Kind converter is the second number; The number of the plurality of first branch of the plurality of Equations of The Second Kind converter is this second number; The the plurality of second number across cell signal is this second number; The number of the plurality of the first data pin ball is the 3rd number; The number of the plurality of the second number pin ball is the 3rd number; The number of this second crossfire is the 3rd number; The number of the number of this second crossfire and this first crossfire equates.
15. signal processing systems according to claim 14, is characterized in that, the 3rd number is less than this second number.
16. signal processing systems according to claim 12, is characterized in that:
Arbitrary Equations of The Second Kind converter in the plurality of Equations of The Second Kind converter further comprises:
The second code level, is located in the second branch of this arbitrary Equations of The Second Kind converter, and
The second decode stage, is located in the first branch of this arbitrary Equations of The Second Kind converter;
Wherein, this second code level of this arbitrary Equations of The Second Kind converter second is encoded across cell signal to this of this arbitrary Equations of The Second Kind converter, so that the second coded signal to be provided;
This second arranges the plurality of second coded signal of the plurality of Equations of The Second Kind converter across chip connecting circuit, to form the plurality of the second crossfire,
This first rearranges the plurality of the second crossfire across chip connecting circuit, and correspondingly for the plurality of first branch of the plurality of Equations of The Second Kind converter obtains the plurality of the second coded signal, and
This second decode stage of this arbitrary Equations of The Second Kind converter carries out decoding to corresponding the second coded signal, and this first branch that thinks this arbitrary Equations of The Second Kind converter obtains this second across cell signal.
17. signal processing systems according to claim 16, is characterized in that, the number of this Equations of The Second Kind converter is the second number; The number of the plurality of first branch of the plurality of Equations of The Second Kind converter is this second number; The the plurality of second number across cell signal is this second number; The number of the plurality of the second coded signal is this second number; The number of the plurality of the first data pin ball is the 3rd number; The number of the plurality of the second number pin ball is the 3rd number; The number of this second crossfire is the 3rd number; The number of the number of this second crossfire and this first crossfire equates.
18. signal processing systems according to claim 12, is characterized in that, the frequency of frequency interface of cutting apart this arbitrary first kind converter is identical or different with the frequency of frequency interface of cutting apart this arbitrary Equations of The Second Kind converter.
19. signal processing systems according to claim 12, is characterized in that, the plurality of first sample frequency across cell signal equates with the plurality of second sample frequency across cell signal or be different.
20. 1 kinds of signal processing methods, is characterized in that, this signal processing method is realized distributing and crossed over the signal processing system of the first chip and the second chip, and this signal processing method comprises:
Arrange a plurality of converters, arbitrary converter in the plurality of converter receives input signal, and correspondingly provide output signal by the conversion between digital signal and simulating signal, wherein, this arbitrary converter is split into the first branch being formed in this first chip and is formed at the second branch in this second chip, and one of them of this first branch and this second branch changed the sample frequency of this input signal, so that the M signal of different sample frequency to be provided; And
By be formed at first in this first chip across chip connecting circuit be formed at second in this second chip across chip connecting circuit, between this first branch of this arbitrary converter and this second branch, transmit this M signal.
21. signal processing methods according to claim 20, is characterized in that, 4 to 16 times of this sample frequency of this input signal that this sample frequency of this M signal of this arbitrary converter is this arbitrary converter.
22. signal processing methods according to claim 20, it is characterized in that, the plurality of converter comprises a plurality of digital analog converters, arbitrary digital analog converter in the plurality of this digital analog converter comprises a plurality of sampling filters that rise, and the plurality of arbitrary sampling filter that rises rising in sampling filter increases sample frequency.
23. signal processing methods according to claim 20, it is characterized in that, the plurality of converter comprises a plurality of analog-digital converters, arbitrary analog-digital converter in the plurality of this analog-digital converter comprises a plurality of desampling fir filters, and the arbitrary desampling fir filter in the plurality of desampling fir filter reduces sample frequency.
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| Application Number | Priority Date | Filing Date | Title |
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| US201361774118P | 2013-03-07 | 2013-03-07 | |
| US61/774,118 | 2013-03-07 | ||
| US14/173,870 | 2014-02-06 | ||
| US14/173,870 US9535858B2 (en) | 2013-03-07 | 2014-02-06 | Signal processing system and associated method |
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| CN104035908A true CN104035908A (en) | 2014-09-10 |
| CN104035908B CN104035908B (en) | 2017-09-29 |
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