CN104035908B - Signal processing system and method - Google Patents

Signal processing system and method Download PDF

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Publication number
CN104035908B
CN104035908B CN201410078322.8A CN201410078322A CN104035908B CN 104035908 B CN104035908 B CN 104035908B CN 201410078322 A CN201410078322 A CN 201410078322A CN 104035908 B CN104035908 B CN 104035908B
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signal
converter
branch
chip
frequency
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CN104035908A (en
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杨健忠
江嘉峰
陈建铭
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MediaTek Inc
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MediaTek Inc
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Abstract

The present invention provides a kind of signal processing system and method.The wherein chip of signal processing system range spans first and the second chip, including：First across chip connection circuit, the second across chip connection circuit, and multiple converters；Any converter in multiple converters includes：Form multiple units of the concatenation of multiple frequency interfaces, and the conversion frequency between two continuous side frequency interfaces of any cell in multiple units；Wherein, any converter is divided into the first branch and the second branch by the first across chip connection circuit with the second across chip connection circuit at the corresponding frequency interface of any converter, first branch of any converter and the second branch are respectively formed in the first chip and the second chip, and the first across chip connection circuit and the second across chip connection circuit transmit signal between the first branch and the second branch of any converter.Signal processing system and method provided by the present invention, with stronger flexibility.

Description

Signal processing system and method
Technical field
The invention relates to a kind of signal processing system and its method, turned in particular to one kind by suitably splitting Parallel operation is to be formed at the different branches in different chips to optimize the signal processing system and its method of cost of implementation.
Background technology
Multimedia（Such as audio and/or video）Broadcasting and/or collection（Such as receive, catch, record）It has been modern Very popular or even indispensable function in electronic installation；These electronic installations include mobile phone, intelligent mobile phone, put down Plate/notebook computer, Wearable accessory, digital camera and camcorders（camcorder）, omniselector（Such as satellite fix dress Put）, monitoring（surveillance）Equipment, hand-held device and pocket computer etc..To handle multimedia broadcasting with collecting, Existing structure is by analog-digital converter（ADC, analog-to-digital converter）With digital analog converter （DAC, digital-to-analog converter）It is integrated into coding and decoding（Codec, coding-decoding）Chip, with Master chip Collaboration；For example, this master chip can be central processing unit（CPU）, application processor（application processor）Or fundamental frequency（baseband）Processor.Coding and decoding chip is to exchange letter by across chip connection mechanism with master chip Number.
For example, to reach the broadcasting and collection of audio, coding and decoding chip be master chip is bridged at it is one or more Loudspeaker and one or more microphones.When playing audio, the digital audio and video signals to be played, the digital sound are provided by master chip Frequency signal can be transferred to coding and decoding chip by across chip connection mechanism, and by coding and decoding chip be converted into simulation it is defeated Go out signal, with drive the speaker.When collecting audio, then the simulated audio signal that microphone is detected is converted to by coding and decoding chip Data signal, and master chip is transferred to by across chip connection mechanism.
In the prior art, transmitted in master chip and coding and decoding chip chamber（relay）Across the chip company of digital audio and video signals The system of picking is with I2S（inter-IC sound）Serial media bus between bus or low-power chip（Hereinafter referred to as Slimbus） Realize.In order to two-way in master chip and coding and decoding chip chamber（bi-directional）Exchange stereophony（2-channel stereo）Digital audio and video signals, I2S at least needs three across chip wiring, therefore master chip need to have three ball pin（ball）（Or Stitch（pin））, and coding and decoding chip need to have the other three ball pin.To support more multichannel, I2S needs more wirings, Therefore master chip must also set more ball pin with coding and decoding chip.Therefore, I2S buses lock into high pin number（The counting of ball pin） With complicated across chip wiring.
On the other hand, Slimbus can be in master chip and many sound of across chip communication support of coding and decoding chip chamber with the 2-wire The DAB two-way exchange in road.However, Slimbus has to realize complexity in both master chip and coding and decoding chip Internet, including physical layer（physical layer）, ccf layer（frame layer）With the messaging protocol of higher （message protocol）With host-host protocol（transport protocol）.Therefore, whether in master chip or coding and decoding Chip, Slimbus locks into the hardware and larger layout area of complexity.
The content of the invention
In view of this, the present invention proposes a kind of signal processing system and method.
According to first embodiment of the invention, there is provided a kind of signal processing system.The signal processing system range spans One chip and the second chip, and including：First across chip connection circuit, is formed in first chip, the second across chip connection Circuit, is formed in second chip, and is coupled to first across the chip connection circuit, and in data signal and analog signal Between multiple converters for being changed；Any converter in the plurality of converter includes：Form the string of multiple frequency interfaces The multiple units connect, different frequency interface is associated with different frequency respectively, and any cell in the plurality of unit is at two Conversion frequency between continuous side frequency interface；Wherein, first across the chip connection circuit second across chip is connected electricity with this Any converter is divided into the first branch and the second branch by road at the corresponding frequency interface of any converter, this First branch of one converter and second branch be respectively formed in first chip with second chip, and this first Across chip connection circuit and second across the chip connection circuit are between first branch and second branch of any converter Transmit signal.
According to second embodiment of the invention, there is provided a kind of signal processing method.The signal processing method realize distribution across The more signal processing system of the first chip and the second chip, the signal processing method includes：Arrange multiple converters, the plurality of turn Any converter in parallel operation receives input signal, and is correspondingly provided by the conversion between data signal and analog signal Output signal, wherein, any converter be divided into the first branch being formed in first chip and be formed at this second The second branch in chip, and one of first branch and second branch change the sample frequency of the input signal, To provide the M signal of different sample frequencys；And by the be formed in first chip first across chip connection circuit with The second across chip connection circuit being formed in second chip, in first branch and second branch of any converter Between transmit the M signal.
Signal processing system and method proposed by the invention, with stronger flexibility.
Brief description of the drawings
Fig. 1 to Fig. 8 is the schematic diagram of the signal processing system according to embodiment of the present invention.
Fig. 9 is the design cycle of optimization embodiment of the present invention.
Embodiment
Fig. 1 is refer to, Fig. 1 is the schematic diagram of the signal processing system 100 according to embodiment of the present invention.Signal transacting system The range spans chip 101 of system 100 and chip 102.Signal processing system 100 includes across chip connection circuit 111 and across chip Connect circuit 112, and converter DA [1] to converter DA [P] and converter AD [1] to converter AD [Q]（Wherein converter Number be (P+Q)）.Converter DA [p]（Wherein, p=1~P）In each be digital analog converter（For example and difference Word analog converter（sigma-delta DAC））, signal Sa [p, 0] can be converted to signal Sa [p, Nu+2], wherein signal Sa [p, 0] is digital input signals, and signal Sa [p, Nu+2] is analog output signal.Converter AD [q]（Wherein, q=1~Q）In Each is analog-digital converter（For example, and poor analog-digital converter（sigma-delta ADC））, can be by signal Sb [q, 0] is converted to signal Sb [q, Nd+1], and wherein signal Sb [q, 0] is analog input signal, and signal Sb [q, Nd+1] is simulation Output signal.Across chip connection circuit 111 is respectively formed in chip 101 and chip 102 with being connected circuit 112 across chip, will Converter DA [p]（Wherein, p=1~P）In each be divided into the branch X1 being respectively formed in chip 101 and chip 102 [p] and branch X2 [p], also, also by converter AD [q]（Wherein, q=1~Q）In each be divided into and be respectively formed in core The branch Y1 [q] and branch Y2 [q] of piece 101 and chip 102.That is, the distribution of signal processing system 100 is at least across two chips （Chip 101 and chip 102）.
Chip 101 includes the external data ball pin for signal exchange（Stitch）Da [1] is to data ball pin（Stitch）Da [K]（Wherein the number of data ball pin is K）, and an external clock signal ball pin（Stitch）B1, to receive clock letter Number CK1.Accordingly, chip 102 includes the external data ball pin Db [1] to data ball pin Db [K] for signal exchange（Wherein The number of data ball pin is K）, and external clock signal ball pin B2, to transmit clock signal CK1.It is each to data ball Pin Da [k] and data ball pin Db [k]（Wherein, k=1~K）Be mutually coupled, clock signal ball pin B1 then with clock signal ball pin B2 It is mutually coupled.By data ball pin Da [1] to data ball pin Da [K] and data ball pin Db [1] to data ball pin Db [K], across Chip connection circuit 111 is mutually coupled with being connected circuit 112 across chip, to carry out two-way number according to clock signal CK1 sequential According to transmission.Correspondingly, across the chip connection circuit 111 that can be in communication with each other just can be each converter with being connected circuit 112 across chip DA [p] (wherein, p=1~P) is transmitted signal to branch X2 [p] by branch X1 [p], and is each converter AD [q]（Wherein, q=1 ~Q）Signal is transmitted to branch Y1 [q] by branch Y2 [q], so as to make in converter DA [p] each can complete signal Sa [p, 0] is digital to analog-converted to signal Sa's [p, Nu+2]（Wherein, signal Sa [p, 0] is digital input signals, signal Sa [p, Nu+2] is analog output signal）, and each for making in converter AD [q] can complete signal Sb [q, 0] to signal Sb [q, Nd+1] simulation to numeral change（Wherein, signal Sb [q, 0] is analog input signal, and signal Sb [q, Nd+1] is numeral output Signal）.
According to the embodiment of the present invention, signal processing system 100 can be audio codec system, in digital sound Changed between frequency signal and simulated audio signal, chip 101 can be high-speed digital integrated circuit, with the small chi of advanced, high cost It is very little（Such as nm level）Manufactured by technique；Chip 102 can be then composite signal integrated circuits, with the large scale of ripe low cost （Such as micron order）Manufactured by technique.The stereo audio that converter DA [1] to converter DA [P] is used for P sound channel is played, wherein, Signal Sa [1,0] to signal Sa [P, 0] is the digital tone source signal to be played of P sound channel, by digital interface circuit DI（It is formed at In chip 101）There is provided, and signal Sa [1, Nu+2] to signal Sa is respectively converted into by converter DA [1] to converter DA [P] [P, Nu+2], makes signal Sa [1, Nu+2] to signal Sa [P, Nu+2] can be to drive P loudspeaker（It is not shown）（Wherein, believe Number Sa [1, Nu+2] to signal Sa [P, Nu+2] is analog output signal）.On the other hand, converter AD [1] to converter AD [Q] The stereo audio for being then used for Q sound channel is collected, wherein, signal Sb [1,0] to signal Sb [Q, 0] is Q microphone（It is not shown） The simulated audio signal detected, can be respectively converted into signal Sb [1, Nd+1] to letter by converter AD [1] to converter AD [Q] Number Sb [Q, Nd+1]（Wherein, signal Sb [1, Nd+1] to signal Sb [Q, Nd+1] is digital output signal）, and it is sent to numeral Interface circuit DI is collected.According to the embodiment of the present invention, number P can be equal to 2 to support two sound channels of left and right, number Q 2 can also be equal to.
As shown in figure 1, converter DA [p]（Wherein, p=1~P）In each include unit U [p, 1] of concatenation to list First U [p, Nu]（Wherein, the number of the unit of concatenation is Nu）, it is coupled to the unit U [p, Nu] at end digital and analog interface electricity Road IA [p], and it is coupled to digital and analog interface circuit I A [p] digital simulation level（DAC stage）DAs[p].In the present invention In one embodiment, number N u can be equal to 3.Unit U [p, i]（Wherein, i=1~Nu）In each can be liter sampling Wave filter, to increase sample frequency（sampling rate）（Sample rate）.Each leading in converter DA [p] Unit U [p, 1] can receive signal Sa [p, 0]（Wherein, signal Sa [p, 0] is digital input signals）, and sampling is correspondingly provided The higher signal Sa of frequency [p, 1]；Each follow-up unit U [p, i]（Wherein, i>1）Previous unit U [p, i- can be received 1]（It is not shown）The signal Sa [p, i-1] of offer, and correspondingly provide sample frequency higher signal Sa [p, i].That is, signal Sa [p, 0] is each passed through to signal Sa [p, Nu]（Nu+1）The frequency interface of individual different frequency, such as（Nu+1）Individual sample frequency is cumulative Frequency interface.Unit U [p, i]（Wherein, i=1~Nu）Liter sampling can liter sampling after signal Sa [p, i] in increase adopt The number of sample, for example, interpolation can be carried out between two neighbouring samples in signal Sa [p, i-1], to make in signal Sa [p, i] Unit interval number of samples is more than the unit interval number of samples in signal Sa [p, i-1].Digital and analog interface circuit I A [p] can It is modulated with difference modulation come the signal Sa [p, Nu] that the unit U [p, Nu] to end is provided, to form the letter after modulation Number Sa [p, Nu+1]（Wherein, signal Sa [p, Nu+1] is data signal）, digital simulation level DAs [p] then can be by the letter after modulation Number Sa [p, Nu+1] is converted to signal Sa [p, Nu+2]（Wherein, signal Sa [p, Nu+2] is analog output signal）.
Each converter DA [p] unit U [p, 1] into unit U [p, Nu], across chip connection circuit 111 with across chip Converter DA [p] is divided into branch X1 [p] and branch X2 by connection circuit 112 in the corresponding frequency interfaces of signal Sa [p, ix] [p], wherein, mark（index）Ix is the definite value selected by 1 into Nu.According to an embodiment of the invention, signal Sa [p, ix] sample frequency is 4 to 16 times of signal Sa [p, 0] to signal Sa [p, ix-1] sample frequency.According to the present invention Another embodiment, if the mark ix selected be less than number N u, be formed at chip 101 branch X1 [p] include unit U [p, 1] to unit U [p, ix], being formed at the branch X2 [p] of chip 102 then includes unit U [p, ix+1] to unit U [p, Nu], numeral Analog interface circuit IA [p], and digital simulation level DAs [p].If making it equal to number N u during selection marker ix, branch X1 [p] can include unit U [p, 1] to unit U [p, Nu], and branch X2 [p] then includes digital and analog interface circuit I A [p] and digital mould Intend level DAs [p].
As shown in figure 1, converter AD [q]（Wherein, q=1~Q）In each include cells D [q, 1] of concatenation to list First D [q, Nd]（Wherein, the number of the unit of concatenation is Nd）, it is coupled to the A/D interface circuit of leading cells D [q, 1] ID [q], the simulation numeral level with being coupled to A/D interface circuit I D [q]（ADC stage）ADs[q].Of the invention one In embodiment, number N d can be set to number N u, such as 3.A/D interface circuit I D [q] and simulation numeral can be integrated Level ADs [q] with by with difference modulation come modulated signal Sb [q, 0], and correspondingly provide modulation after signal Sb [q, 1]（Wherein, believe Number Sb [q, 1] is data signal）.Cells D [q, j]（Wherein, j=1~Nd）In each can turn between two side frequency interfaces Change different frequencies；For example, each unit D [q, j] can be desampling fir filter, to reduce sample frequency（Sampling Rate）.Converter AD [q] leading cells D [q, 1] can receive signal Sb [q, 1] and correspondingly offer sample frequency is relatively low Signal Sb [q, 2], each follow-up cells D [q, j]（Wherein, j>1 and j<Nd）Previous cells D [q, j- can then be received 1]（It is not shown）The signal Sb [q, j] of offer, and to correspondingly follow-up cells D [q, j+1]（It is not shown）Sample frequency is provided Relatively low signal Sb [q, j+1].The cells D [q, Nd] at end can receive previous cells D [q, Nd-1]（It is not shown）Signal Sb [q, Nd], and correspondingly provide sample frequency relatively low signal Sb [q, Nd+1].That is, signal Sb [q, 1] is to signal Sb [q, Nd + 1] it is each passed through（Nd+1）The frequency interface of individual different frequency, such as（Nd+1）The frequency interface of individual sample frequency decrescence.Cells D [q,j]（Wherein, j=1~Nd）Down-sampled signal Sb [q, j+1] that can be after down-sampled in reduce sampling number, for example, In discardable signal Sb [q, j] some sampling, make signal Sb [q, j+1] unit interval number of samples be less than signal Sb [q, J] unit interval number of samples.
Each converter AD [q] cells D [q, 1] into cells D [q, Nd], across chip connection circuit 111 with across chip Converter AD [q] is divided into branch Y1 [q] and branch Y2 by connection circuit 112 in the corresponding frequency interfaces of signal Sb [q, jx] [q], wherein, mark jx is the definite value selected by 1 into Nd.Correspondingly, if mark jx is more than 1, it is formed at chip 102 Branch Y2 [q] include simulation numeral level ADs [q], A/D interface circuit I D [q] and cells D [q, 1] to cells D [q, Jx-1], being formed at the branch Y1 [q] of chip 101 then includes cells D [q, jx] to cells D [q, Nd].If mark jx is chosen to be 1, then being formed at the branch Y2 [q] of chip 102 includes simulation numeral level ADs [q] and A/D interface circuit I D [q], is formed Then include cells D [q, 1] to cells D [q, Nd] in the branch Y1 [q] of chip 101.
Because each converter DA [p] is divided between unit U [p, ix] and unit U [p, ix+1], signal Sa [p, ix] （It can be considered across cell signal）Branch X2 [p] unit U [p, ix+1] need to be transferred to by branch X1 [p] unit U [p, ix].For Reach the transfer of this signal, across chip connection circuit 111 can be arranged（arrange）Branch X1 [1] to branch X1 [P] signal Sa The sampling of [1, ix] into signal Sa [P, ix], to form crossfire sf1 [1] to crossfire sf1 [K]（Wherein, the number of crossfire is K）, and pass through the data ball pin Da [1] on across chip connection circuit 111 to data ball pin Da [K] difference transmission stream sf1 [1] To crossfire sf1 [K].According to clock signal CK1 sequential, across chip connection circuit 112 can pass through across chip connection circuit 112 Data ball pin Db [1] to data ball pin Db [K] receives crossfire sf1 [1] to crossfire sf1 [K], and rearranges crossfire sf1 [1] extremely Sampling in crossfire sf1 [K], and correspondingly obtain converter DA [1] to converter DA [P] branch X2 [1] to branch X2 [P] Signal Sa [1, ix] to signal Sa [P, ix].
Selectively, across chip connection circuit 111 further can according to branch X1 [1] to branch X1 [P] signal Sa [1, Ix] to signal Sa [P, ix] by checking information（Such as self-correcting code（error correction code））It is attached to Crossfire sf1 [1] to crossfire sf1 [K].When across chip connection circuit 112 obtain branch X2 [1] to branch X2 [P] signal Sa [1, Ix] to signal Sa [P, ix] when, across chip connection circuit 112 can be further by checking checking information, and detect and connect The crossfire sf1 [1] to crossfire sf1 [K] of receipts error；And if necessary and be possible to, then corrected according to checking information Crossfire sf1 [1] to crossfire sf1 [K].
Similarly, because each converter AD [q] is divided between cells D [q, jx-1] and D [q, jx], signal Sb [q, jx] （It can be considered across cell signal）Branch Y1 [q] cells D [q, jx] need to be transferred to by branch Y2 [q] cells D [q, jx-1].For Reach the transfer of this signal, across chip connection circuit 112 can arrange branch Y2 [1] to branch Y2 [Q] signal Sb [1, jx] extremely Sampling in signal Sb [Q, jx], to form crossfire se1 [1] to crossfire se1 [K]（Wherein, the number of crossfire is K）, and pass through The data ball pin Db [1] of chip 102 to data ball pin Db [K] difference transmission stream se1 [1] to crossfire se1 [K].Pass through chip 101 data ball pin Da [1] to data ball pin Da [K], across chip connection circuit 111 can further receive crossfire se1 [1] to string Se1 [K] is flowed, and rearranges the sampling in crossfire se1 [1] to crossfire se1 [K], and correspondingly obtains converter AD [1] and is extremely turned Parallel operation AD [Q] branch Y1 [1] to branch Y1 [Q] signal Sb [1, jx] to signal Sb [Q, jx].
Selectively, across chip connection circuit 112 further can according to branch Y2 [1] to branch Y2 [Q] signal Sb [1, Jx] checking information is attached to crossfire se1 [1] to crossfire se1 [K] to signal Sb [Q, jx].When across chip connection electricity When road 111 obtains branch Y1 [1] to branch Y1 [Q] signal Sb [1, jx] to signal Sb [Q, jx], across chip connection circuit 111 Can be further by checking checking information, and detect the crossfire se1 [1] to crossfire se1 [K] received error；And If necessary and it is possible to, then crossfire se1 [1] to crossfire se1 [K] is corrected according to checking information.
In one embodiment, number K is less than number N u or number N d, therefore realizes（P+Q）Pin needed for individual sound channel Digit（That is number K）It can reduce.For example, number K can be set to 1；That is, in branch X1 [1] to branch X1 [P], divide Between portion Y1 [1] to branch Y1 [Q] and branch X2 [1] to X2 [P], branch Y2 [1] to branch Y2 [Q] needed for across chip signal Transmission can use single a pair of data ball pin Da [1] and data ball pin Db [1] and a pair of clock signal ball pin B1 and clock signal ball Pin B2 is achieved.In the case of number K is equal to 1, across chip connection circuit 111 can be by parallel signal Sa [1, ix] extremely Sampling in signal Sa [P, ix]（The additional checking information with selectivity）Serialization（serialize）For single crossfire Sf1 [1], and single crossfire sf1 [1] is transmitted by the single data ball pin Da [1] for being allocated to signal processing system 100.Lift For example, across chip connection circuit 111 can sequentially transmit each bit of a certain sampling in signal Sa [1, ix]（According to choosing The error correcting function of selecting property, the then a certain sampling that will be transmitted in signal Sa [1, ix] is transmitted together with self-correcting code）, then for Sequentially transmit each bit of the sampling of same sampling time point in signal Sa [2, ix]（And its self-correcting code）, by that analogy. Accordingly, across chip connection circuit 112 can be received single crossfire sf1 [1] by single data ball pin Db [1], to crossfire sf1 [1] sampling in is de-serialized（de-serialize）, so as to the branch X2 for converter DA [1] to converter DA [P] [1] parallel signal Sa [1, ix] to signal Sa [P, ix] is recovered to branch X2 [P].For example, across chip connection circuit 112 Available buffer（For example use flip-flop）The bit sequentially received in crossfire sf1 [1], and count whether enough group of the bit received Close out a sampling（And its self-correcting code）, the bit that correspondingly group receives, so as to for rebuild parallel signal Sa [1, Ix] to signal Sa [P, ix] same sampling time point sampling（And its self-correcting code, and each sampling progress error is detectd Survey and correction）；In this way, signal Sa [1, ix] to signal Sa [P, ix] can be transferred to branch X2 [1] to branch X2 [P].
Vice versa, and in the case of number K is equal to 1, across chip connection circuit 112 can be by parallel signal Sb [1, jx] Sampling into signal Sb [Q, jx]（The additional checking information with selectivity）Single crossfire se1 [1] is serialized as, and Pass through single data ball pin Db [1] transmission stream se1 [1].As response, across chip connection circuit 111 can be by single data Ball pin Da [1] receives single crossfire se1 [1], and the sampling in crossfire se1 [1] is de-serialized, to be converter AD [1] the branch Y1 [1] to branch Y1 [Q] to converter AD [Q] recovers parallel signal Sb [1, jx] to signal Sb [Q, jx].
With needing to support complicated communication layers and agreement（For example, Slimbus）Complicated circuit compare, due to connecting across chip Simple function need to be performed with being connected 112, circuit across chip by connecing circuit 111, and for example data arrangement is with rearranging（And choosing The error correction of selecting property）, therefore across chip connection circuit 111 with across chip be connected circuit 112 can with fairly simple circuit come Realize.Although signal Sa [1,0] to signal Sa [P, 0] can be pulse code modulation（PCM, pulse-code modulation）Data signal, signal Sa [1, ix] to signal Sa [P, ix] need not be pulse code modulation numeral letter Number.
In an embodiment of the invention, clock signal CK1 is supplied to across chip company by across chip connection circuit 112 Connect circuit 111；Clock signal CK1 is aligned in branch X2 [1] to branch X2 [P] and branch Y2 [1] to branch Y2 in chip 102 The sequential of [Q], thus across chip connection circuit 112 can synchronization crossfire sf1 [] alignd with crossfire se1 [] branch X2 [] with Branch Y2 [] sequential.To meet branch X1 [], branch X2 [], branch Y1 [] and branch Y2 [] time sequential routine, clock Signal CK1 clock rate, and crossfire sf1 [1] to crossfire sf1 [K] and crossfire se1 [1] to crossfire se1 [K] handling capacity, It can be determined according at least one following factor：Number P and number Q value, number K value, signal Sa [p, ix] and signal Sb Respectively sampled in [q, jx]（With checking information）Bit number, and signal Sa [p, ix] and signal Sb [q, jx] sampling frequency Rate.For example, if if if number P and/or number Q numerical value is bigger, number K value is smaller and/or signal Sa [, Ix] it is higher with signal Sb [, jx] sample frequency, then clock signal CK1 clock rate should also set higher.In number P In the case of=number Q=2, number K is set as that 1 should be technically appropriate feasible.Consider clock rate, if number P or Number Q is more than 2, and number K can be configured to 2,3 or bigger.When i.e., only with a pair of clock signal ball pin, number K can be Changeable（scalable）.
Liter sampling and down-sampled structure according to Fig. 1, signal Sa [p, i] frequency are higher than signal Sa's [p, i-1] Frequency（Wherein, i=1~Nu）；On the other hand, signal Sb [q, j] frequency is higher than signal Sb [q, j+1] frequency（Wherein, j=1 ~Nd）.By the frequency interface for changing segmentation（For example, from 1 into Nu selection marker ix, and/or from 1 into Nd select Indicate jx）And/or pin number（Number K）, the present invention just can provide the elasticity of design, to optimize the total of signal processing system 100 Cost of implementation.
In the case of number K value remains unchanged, if mark ix value is closer to number N u and/or indicates that jx value is got over Close to 1, the then circuit that realized by chip 101（For example, more unit U [p ,] and D [q ,]）It is more, and will be by chip 102 circuits realized are then fewer；In addition, because the frequency interface of segmentation corresponds to the higher signal of sample frequency, data ball pin Da [1] to Da [K] and Db [1] to Db [K] handling capacity, together with clock signal CK1 clock rate, is also required for increase.Will More circuits is realized in chip 101, cost is intended to increase with layout area, and across the chip connection of high speed can be also added to This；However, because chip 102 only need to realize less circuit with smaller layout, cost can be reduced again.Manufacture chip 101 and 102 The manufacturing technology of use can also influence the balance of cost, if chip 101 is manufactured by advanced small size technique, to realize more The extra layout area of circuit can not necessarily be significantly increased；On the other hand, if chip 102 is with manufactured by ripe large scale technique , its effect for reducing cost also can be impacted.In addition, number K value can also influence cost；Number K is increased, across chip company The handling capacity connect can be reduced with clock rate, reduce cost, but larger number K can also increase pin number and across chip cloth The complexity of line, this can reduce the influence of cost reduction again.
Although the implementation cost with intuition estimating signal processing system 100 is extremely difficult, connect for dividing frequency The different choice of mouth and number K, still can accurately calculate the cost under different choice with computer.Compare under various selections Cost, just can actually realize signal processing system 100 using the minimum selection of cost.
Fig. 2 is refer to, Fig. 2 is the schematic diagram of the signal processing system 200 according to embodiment of the present invention.Follow Fig. 1 institutes The range spans chip 201 of signal processing system 200 in the structure shown, Fig. 2 and chip 202, and use three-level rise sample with For numeral to analog-converted, and three-level is down-sampled for simulating to numeral conversion, therefore number N u=number Ns d=3. Signal processing system 200 includes converter DA [1] to converter DA [P] and converter AD [1] to converter AD [Q].Wherein, Converter DA [1] to converter DA [P] is digital analog converter and number is P；Converter AD [1] to converter AD [Q] is Analog-digital converter and number are Q.Each converter DA [p]（Wherein, p=1~P）Including for a liter unit U [p, 1] for sampling To unit U [p, 3], digital and analog interface circuit I A [p] and digital simulation level DAs [p].Each converter AD [q]（Wherein, q=1~ Q）Including simulation numeral level ADs [q], A/D interface circuit I D [q], and for down-sampled cells D [q, 1] to unit D[q,3]。
There is digital interface circuit DI in chip 201, it is possible to provide frequency is fs signal Sa [1,0] to signal Sa [P, 0], its Middle signal Sa [1,0] to signal Sa [P, 0] be digital input signals.Signal Sa [p, 0]（Wherein, p=1~P）By unit U [p, 1] Sampling is risen, to provide signal Sa [p, 1] of the frequency as L*fs；That is, unit U [p, 1] liter sampling operation can be by signal Sa [p, 0] Frequency fs be multiplied by frequency factor L.Similarly, unit U [p, 2] and unit U [p, 3] can be provided respectively by a liter sampling multiply frequency because Sub- M can distinguish the signal Sa [p, 2] that output frequency is L*M*fs and the signal that frequency is L*M*N*fs with multiplying frequency factor N Sa[p,3]。
In each converter AD [q], simulation numeral level ADs [q] with A/D interface circuit I D [q] can cooperating, Receive signal Sb [q, 0]（Wherein, signal Sb [q, 0] is analog input signal）, and it is L*M*N* correspondingly to provide a frequency Fs signal Sb [q, 1]（Wherein, signal Sb [q, 1] is data signal）.Signal Sb [q, 1] can be down-sampled by cells D [q, 1], To provide signal Sb [q, 2] of the frequency as L*M*fs；That is, the down-sampled operation of cells D [q, 1] is by signal Sb's [q, 0] Frequency L*M*N*fs divided by frequency elimination factor N.Similarly, cells D [q, 2] and D [q, 3] by it is down-sampled can provide respectively frequency elimination because Sub- M and frequency elimination factor L, therefore the signal Sb [q, 3] that output frequency is L*fs and the signal Sb [q, 4] that frequency is fs can be distinguished.
2 are equal to by selection marker ix with mark jx to connect through come splitting signal processing system 200, and across chip Selection number K is equal to 1 to set up.Correspondingly, each converter DA [p] is segmented into branch X1 [p] and branch X2 [p], branch X1 [p] and branch X2 [p] are respectively by chip 201 is realized with chip 202；Unit U [p, 1] and unit U [p, 2] is included in branch X1 In [p], unit U [p, 3] then belongs to branch X2 [p].The signal that branch X1 [1] to branch X1 [P] is provided, frequency is L*M*fs Sa [1,2] to signal Sa [P, 2], by across chip connection circuit 211 and single a pair of data that circuit 212 is connected across chip Single crossfire sf2 on ball pin Da [1] and data ball pin Db [1], is transmitted to branch X2 [1] to branch X2 [P].
Similarly, each converter AD [q] is segmented into branch Y1 [q] and branch Y2 [q], branch Y1 [q] and branch Y2 [q] Realized respectively by chip 201 with chip 202；Cells D [q, 2] is included in branch Y1 [q] with cells D [q, 3], cells D [q, 1] Then belong to branch Y2 [q].The signal Sb [1,2] to signal Sb that branch Y2 [1] to branch Y2 [Q] is provided, frequency is L*M*fs [Q, 2], by single a pair of data ball pin Db [1] and the data that are connected circuit 211 with across chip in across chip connection circuit 212 Single crossfire se2 on ball pin Da [1], is transmitted to branch Y1 [1] to branch Y1 [Q].Clock signal CK2 by chip 202 when Clock signal ball pin B2 is transmitted to the clock signal ball pin B1 of chip 201, to be that crossfire sf2 and crossfire se2 provide sequential.Clock is believed Number CK2 clock rate is determined with crossfire sf2 and crossfire se2 handling capacity according to frequency L*M*fs, to meet bidirectional linked list Transmit the sequential required by signal Sa [1,2] to signal Sa [P, 2] and signal Sb [1,2] to signal Sb [Q, 2].
Fig. 3 is refer to, Fig. 3 is the schematic diagram of the signal processing system 300 according to embodiment of the present invention.It is similar with Fig. 2, Signal processing system 300 shown in Fig. 3 across chip 301 and chip 302, and including converter DA [1] to converter DA [P] with And converter AD [1] to converter AD [Q].Wherein, converter DA [1] to converter DA [P] is digital analog converter, conversion Device AD [1] to converter AD [Q] is analog-digital converter.Each converter DA [p]（Wherein, p=1~P）By digital interface circuit DI receives the signal Sa [p, 0] that sample frequency is fs, and including rising the unit U [p, 1] to unit U [p, 3] of sampling, therefore frequency The signal Sa [p, 1] that frequency is L*fs can be converted into for fs signal Sa [p, 0], frequency is L*M*fs signal Sa [p, 2], And the signal Sa [p, 3] that frequency is L*M*N*fs.Each converter AD [q]（Wherein, q=1~Q）To signal Sb [q, 0] carry out and Differential mode is intended to numeral conversion, and correspondingly provides the signal Sb [q, 1] that sample frequency is L*M*N*fs（Wherein, signal Sb [q, 1] For data signal）, and including down-sampled cells D [q, 1] to cells D [q, 3], therefore frequency is L*M*N*fs signal Sb [q, 1] can be converted into the signal Sb [q, 2] that frequency is L*M*fs, and frequency is L*fs signal Sb [q, 3], and frequency is fs Signal Sb [q, 4].
In the case of number K is all 1, one of Fig. 2 and difference of two embodiments shown in Fig. 3 are：Shown in Fig. 3 The frequency that is segmented in associated by signal Sa [p, 1] and signal Sb [q, 3] of signal processing system 300 be L*fs frequency interface. Correspondingly, each converter DA [p] is segmented into branch X1 [p] and branch X2 [p], and branch X1 [p] and branch X2 [p] is respectively by core Piece 301 is realized with chip 302；Branch X1 [p] includes unit U [p, 1], and branch X2 [p] then includes unit U [p, 2] and unit U [p,3].By single a pair of data ball pin Da [1] and the data that are connected circuit 312 with across chip in across chip connection circuit 311 The signal Sa [1,1] that single crossfire sf3 on ball pin Db [1], branch X1 [1] to branch X1 [P] are provided respectively is to signal Sa[P,1]（Frequency is L*fs）Branch X2 [1] to branch X2 [P] can be transferred to.
Similarly, each converter AD [q] is segmented into branch Y1 [q] and branch Y2 [q], branch Y1 [q] and branch Y2 [q] Realized respectively by chip 301 with branch 302；Branch Y1 [q] includes cells D [q, 3], and branch Y2 [q] then includes cells D [q, 2] With cells D [q, 1].Pass through the single crossfire se3 on single a pair of data ball pin Db [1] and data ball pin Da [1], branch The signal Sb [1,3] to signal Sb [Q, 3] that Y2 [1] to branch Y2 [Q] is provided respectively（Frequency is L*fs）It can be transferred to point Portion Y1 [1] to branch Y1 [Q].Clock signal CK3 is transmitted to the clock letter of chip 301 by the clock signal ball pin B2 of chip 302 Number ball pin B1, to be that crossfire sf3 and crossfire se3 provides sequential.
Compare Fig. 2 and Fig. 3 two embodiments, because signal processing system 200（As shown in Figure 2）Split in higher Frequency L*M*fs frequency interface, signal processing system 300（As shown in Figure 3）The frequency then split in relatively low frequency L*fs connects Mouthful, clock signal CK2（As shown in Figure 2）Clock rate need to be higher than clock signal CK3（As shown in Figure 3）Clock rate.String Flow sf2 and crossfire se2（As shown in Figure 2）Handling capacity also need higher than crossfire sf3 and crossfire se3（As shown in Figure 3）Handling capacity. However, chip 302（As shown in Figure 3）Than chip 202（As shown in Figure 2）More circuits is needed to realize.
Fig. 4 is refer to, Fig. 4 is the schematic diagram of the signal processing system 400 according to embodiment of the present invention.With Fig. 2 and Fig. 3 It is similar, range spans chip 401 and the chip 402 of the signal processing system 400 shown in Fig. 4, and extremely turn including converter DA [1] Parallel operation DA [P] and converter AD [1] to converter AD [Q].Wherein, converter DA [1] to converter DA [P] is digital simulation Converter, converter AD [1] to converter AD [Q] is analog-digital converter.Each converter DA [p]（Wherein, p=1~P）By Digital interface circuit DI receives the signal Sa [p, 0] that sample frequency is fs, and including rising the unit U [p, 1] to U [p, 3] of sampling, Therefore the signal Sa [p, 0] that frequency is fs can be converted into the signal Sa [p, 1] that frequency is L*fs, and frequency is L*M*fs signal Sa [p, 2], and the signal Sa [p, 3] that frequency is L*M*N*fs.Each converter AD [q]（Wherein, q=1~Q）To signal Sb [q, 0] carry out and differential mode is intended to numeral conversion, and the signal Sb [q, 1] that sample frequency is L*M*N*fs is correspondingly provided, and including drop The cells D [q, 1] of sampling is to cells D [q, 3], therefore frequency can be converted into frequency for L*M*N*fs signal Sb [q, 1] and be L*M*fs signal Sb [q, 2], frequency is L*fs signal Sb [q, 3], and the signal Sb [q, 4] that frequency is fs.
In the case of number K is all 1, one of difference of two embodiments shown in Fig. 2 to Fig. 4 is：Fig. 4 signals The frequency that processing system 400 is segmented in associated by signal Sa [p, 3] and signal Sb [q, 1] is L*M*N*fs frequency interfaces.Accordingly Ground, each converter DA [p] is segmented into branch X1 [p] and branch X2 [p], and branch X1 [p] and branch X2 [p] is respectively by chip 301 realize with chip 302；Branch X1 [p] includes unit U [p, 1], unit U [p, 2] and unit U [p, 3], and branch X2 [p] is then wrapped Include converter DA [p] remaining circuit, such as digital simulation interface circuit IA [p] and digital simulation level DAs [p].By across core Piece connects circuit 411 and is connected single a pair of data ball pin Da [1] of circuit 412 and the list on data ball pin Db [1] with across chip The signal Sa [1,3] to signal Sa [P, 3] that one crossfire sf4, branch X1 [1] to branch X1 [P] are provided respectively（Frequency is L* M*N*fs）Branch X2 [1] to branch X2 [P] can be transferred to.
Similarly, each converter AD [q] is segmented into branch Y1 [q] and branch Y2 [q], branch Y1 [q] and branch Y2 [q] Realized respectively by chip 401 and 402；Branch Y1 [q] includes cells D [q, 1] to cells D [q, 3], branch Y2 [q] then converters AD [q] remaining circuit, such as simulation numeral level ADs [q] and A/D interface circuit I D [q].By in single a pair of data Single crossfire se4 on ball pin Db [1] and data ball pin Da [1], the letter that branch Y2 [1] to branch Y2 [Q] is provided respectively Number Sb [1,1] to signal Sb [Q, 1]（Frequency is L*M*N*fs）Branch Y1 [1] to branch Y1 [Q] can be transferred to.Clock signal CK4 is transmitted to the clock signal ball pin B1 of chip 401 by the clock signal ball pin B2 of chip 402, thinks crossfire sf4 and crossfire Se4 provides sequential.
Compare Fig. 2 to Fig. 4 multiple embodiments, because signal processing system 400（As shown in Figure 4）Split in higher Frequency L*M*N*fs frequency interface, signal processing system 300（As shown in Figure 3）With signal processing system 200（As shown in Figure 2） The frequency interface in relatively low frequency L*fs and frequency L*M*fs, clock signal CK4 are then divided respectively（As shown in Figure 4）When Clock rate rate need to be higher than clock signal CK3（As shown in Figure 3）With clock signal CK2（As shown in Figure 2）Clock rate.Crossfire sf4 With crossfire se4（As shown in Figure 4）Handling capacity also need higher than crossfire sf3 and crossfire se3（As shown in Figure 3）Handling capacity and crossfire Sf2 and crossfire se2（As shown in Figure 2）Handling capacity.Although chip 402（As shown in Figure 4）The circuit that need to realize is minimum, using across Chip connects circuit 411 and realizes that across chip connection may but increase cost at a high speed with being connected circuit 412 across chip.
In Fig. 2 to Fig. 4 each embodiment, converter DA [] is divided in identical frequency with converter AD [] Frequency interface.In Fig. 2, each converter DA [p] is divided in the frequency interface that frequency is L*M*fs with each converter AD [q].Fig. 3 In, each converter DA [p] is divided in the frequency interface that frequency is L*fs with each converter AD [q].In Fig. 4, each converter DA [p] is divided in the frequency interface that frequency is L*M*N*fs with each converter AD [q].However, converter DA [p] and converter AD [q] can also be divided the frequency interface in different frequency.Fig. 5 and Fig. 6 are refer to, Fig. 5 is the letter according to embodiment of the present invention The schematic diagram of number processing system 500；Fig. 6 is the schematic diagram of the signal processing system 600 according to embodiment of the present invention.
It is similar with Fig. 2 to Fig. 4, range spans chip 501 and the chip 502 of the signal processing system 500 shown in Fig. 5, and Including converter DA [1] to converter DA [P] and converter AD [1] to converter AD [Q].Wherein, converter DA [1] extremely turns Parallel operation DA [P] is digital analog converter, and converter AD [1] to converter AD [Q] is analog-digital converter.Each converter is each Converter DA [p]（Wherein, p=1~P）The signal Sa [p, 0] for being fs by digital interface circuit DI reception sample frequencys, and including Rise the unit U [p, 1] to unit U [p, 3] of sampling, thus frequency be fs signal Sa [p, 0] can be converted into frequency be L*fs Signal Sa [p, 1], frequency be L*M*fs signal Sa [p, 2], and frequency be L*M*N*fs signal Sa [p, 3].Each turn Parallel operation AD [q]（Wherein, q=1~Q）Signal Sb [q, 0] is carried out and differential mode is intended to numeral conversion, and sampling frequency is correspondingly provided Rate is L*M*N*fs signal Sb [q, 1], and including down-sampled cells D [q, 1] to cells D [q, 3], therefore frequency is L*M* N*fs signal Sb [q, 1] can be converted into the signal Sb [q, 2] that frequency is L*M*fs, and frequency is L*fs signal Sb [q, 3], And the signal Sb [q, 4] that frequency is fs.
In the case of number K is all 1, one of difference of each embodiment shown in Fig. 2 to Fig. 5 is：Shown in Fig. 5 Digital analog converter and the analog-digital converter of signal processing system 500 split frequency interface in different frequency.Respectively Converter DA [p] splits the frequency interface that the frequency associated in signal Sa [p, 1] is L*fs；Each converter AD [q] splits in letter The frequency of number Sb [p, 2] association for the L*M*fs of upper frequency frequency interface.Correspondingly, each converter DA [p] is segmented into Branch X1 [p] and branch X2 [p], branch X1 [p] and branch X2 [p] is respectively by chip 501 is realized with chip 502；Branch X1 [p] includes unit U [p, 1], and branch X2 [p] then includes unit U [p, 2] and unit U [p, 3].By in across chip connection circuit 511 are connected single a pair of data ball pin Da [1] of circuit 512 and the single crossfire on data ball pin Db [1] with across chip The signal Sa [1,1] to signal Sa [P, 1] that sf5, branch X1 [1] are provided respectively to branch X1 [P]（Frequency is L*fs）Can quilt Transmit to branch X2 [1] to branch X2 [P].
Similarly, each converter AD [q] is segmented into branch Y1 [q] and branch Y2 [q], branch Y1 [q] and branch Y2 [q] Respectively by chip 501 is realized with chip 502；Branch Y1 [q] includes cells D [q, 3] and cells D [q, 2], and branch Y2 [q] is then Including cells D [q, 1].By the single crossfire se5 on single a pair of data ball pin Db [1] and data ball pin Da [1], point The signal Sb [1,2] to signal Sb [Q, 2] that portion Y2 [1] to branch Y2 [Q] is provided respectively（Frequency is L*M*fs）It can be transmitted To branch Y1 [1] to branch Y1 [Q].Clock signal CK5 by the clock signal ball pin B2 of chip 502 transmit to chip 501 when Clock signal ball pin B1, to be that crossfire sf5 and crossfire se5 provide sequential.Compared with crossfire sf5, due to crossfire se5 need it is serial compared with High frequency（Frequency L*M*fs）Signal Sb [1,2] to signal Sb [Q, 2], therefore clock signal CK5 frequency rate can root Determined according to higher frequency L*M*fs, to meet crossfire se5 timing requirements, wherein frequency L*M*fs is dividing frequency.Separately On the one hand, crossfire sf5 only needs serial relatively low frequency（Frequency L*fs）Signal Sa [1,1] to signal Sa [P, 1], therefore crossfire Sf5 sequential can be determined according to clock signal CK5 frequency elimination result.
Similar with Fig. 2 to Fig. 5, Fig. 6 signal processing system 600 integrates realization by chip 601 and chip 602, and including Converter DA [1] to converter DA [P] and converter AD [1] to converter AD [Q].Wherein, converter DA [1] is to converter DA [P] is digital analog converter, and converter AD [1] to converter AD [Q] is analog-digital converter.Each converter DA [p] （Wherein, p=1~P）The signal Sa [p, 0] that sample frequency is fs is received by digital interface circuit DI, and including rising the unit of sampling U [p, 1] to unit U [p, 3], thus frequency be fs signal Sa [p, 0] can be converted into signal Sa that frequency is L*fs [p, 1], frequency is L*M*fs signal Sa [p, 2], and the signal Sa [p, 3] that frequency is L*M*N*fs.Each converter AD [q]（Its In, q=1~Q）Signal Sb [q, 0] is carried out and differential mode is intended to numeral conversion, and it is L*M*N*fs correspondingly to provide sample frequency Signal Sb [q, 1], and including down-sampled cells D [q, 1] to cells D [q, 3], therefore frequency is L*M*N*fs signal Sb [q, 1] can be converted into the signal Sb [q, 2] that frequency is L*M*fs, and frequency is L*fs signal Sb [q, 3], and frequency is fs Signal Sb [q, 4].
In the case of number K is set to 1, one of difference of each embodiment shown in Fig. 2 to Fig. 6 is：Shown in Fig. 6 Digital analog converter and the analog-digital converter of signal processing system 600 split respectively in higher with lower frequency frequency Rate interface.It is L*M*fs frequency interfaces that each converter DA [p], which splits the frequency associated in signal Sa [p, 2],；Each converter AD [q] Split the L*fs frequency interfaces that the frequency associated in signal Sb [p, 3] is lower frequency.Correspondingly, each converter DA [p] is divided Section is branch X1 [p] and branch X2 [p], and branch X1 [p] and branch X2 [p] is respectively by chip 601 is realized with chip 602；Point Portion X1 [p] includes unit U [p, 1] and unit U [p, 2], and branch X2 [p] then includes unit and U [p, 3].By connecting across chip Connect circuit 611 and be connected single on single a pair of data ball pin Da [1] of circuit 612 and data ball pin Db [1] with across chip The signal Sa [1,2] to signal Sa [P, 2] that crossfire sf6, branch X1 [1] are provided respectively to branch X1 [P]（Frequency is L*fs）Can It is transferred to branch X2 [1] to branch X2 [P].
Similarly, each converter AD [q] is segmented into branch Y1 [q] and branch Y2 [q], branch Y1 [q] and branch Y2 [q] Respectively by chip 601 is realized with chip 602；Branch Y1 [q] include cells D [q, 3], branch Y2 [q] then include cells D [q, 1] with cells D [q, 2].By the single crossfire se6 on single a pair of data ball pin Db [1] and data ball pin Da [1], point The signal Sb [1,3] to signal Sb [Q, 3] that portion Y2 [1] to branch Y2 [Q] is provided respectively（Frequency is L*fs）It can be transferred to Branch Y1 [1] to branch Y1 [Q].Clock signal CK6 is transmitted to the clock of chip 601 by the clock signal ball pin B2 of chip 602 Signal ball pin B1, to be that crossfire sf6 and crossfire se6 provide sequential.Because crossfire sf6 needs serially higher frequency（Frequency L*M* fs）Signal Sa [1,2] to signal Sa [P, 2], therefore clock signal CK6 clock frequency can be according to higher frequency L*M*fs To determine, to meet crossfire sf6 timing requirements, wherein frequency L*M*fs is dividing frequency.On the other hand, crossfire se6 is only needed Serial relatively low frequency（Frequency L*fs）Signal Sb [1,3] to signal Sb [Q, 3], therefore crossfire se6 sequential can according to when Clock signal CK6 frequency elimination result is determined.
From Fig. 2 to Fig. 4 and Fig. 5 to Fig. 6, converter DA [p] is segmented into the frequency of the frequency interface of two branches, with And converter AD [q] is segmented into the frequency of the frequency interface of two branches, the two frequencies can be with equal or different.That is, because each Converter DA [p] is divided in signal Sa [p, ix] frequency interface, and each converter AD [q] is divided in signal Sb's [q, jx] Frequency interface, therefore signal Sa [p, ix] and signal Sb [q, jx] frequency can be identical or different.In Fig. 2 to Fig. 4's In embodiment, signal Sa [p, ix] and signal Sb [q, jx] frequency is identical；And in Fig. 5 and Fig. 6 embodiment, signal Sa [p, ix] and signal Sb [q, jx] frequency is then different.As Fig. 5 and Fig. 6 are discussed, if signal Sa [p, ix] and signal Sb [q, jx] is selected as the signal of different frequency, be may depend on across the clock rate of the clock signal of chip streams in two frequencies Higher frequency.
Fig. 7 is refer to, Fig. 7 is the schematic diagram of the signal processing system 700 according to embodiment of the present invention.With shown in Fig. 1 Embodiment it is similar, the range spans chip 701 of signal processing system 700 and chip 702, and including converter DAe [1] to turn Parallel operation DAe [P], converter ADe [1] to converter ADe [Q], and be respectively formed in chip 701 and chip 702 across core Piece connection circuit 711 is connected circuit 712 with across chip.Wherein, converter DAe [1] to converter DAe [P] turns for digital simulation Parallel operation and number are P；Converter ADe [1] to converter ADe [Q] is analog-digital converter and number is Q.Chip 701 has The data ball pin Da [1] to data ball pin Da [K] that number is K and clock signal ball pin B1, data ball pin Da [1] to data ball pin Da [K] and clock signal ball pin B1 is respectively coupled to the data ball pin Db [1] of chip 702 to data ball pin Db [K] and clock signal Ball pin B2, the number of the data ball pin of its chips 702 is identical with the number of the data ball pin of chip 701.
In signal processing system 700, each converter DAe [p]（Wherein, p=1~P）Can be and poor digital-to-analogue conversion Device, should can be converted to signal Sa [p, Nu+2] with poor digital analog converter by signal Sa [p, 0]（Wherein, signal Sa [p, 0] is Digital input signals, signal Sa [p, Nu+2] is analog output signal）, and including list of the number for the frequency conversion of Nu concatenation First U [p, 1] is to unit U [p, Nu], digital and analog interface circuit I A [p], digital simulation level DAs [p], code level Ea [p] with translating Code level Ga [p].Unit U [p, 1] can be received signal Sa [p, 0] by the digital interface circuit DI in chip 701, and be follow-up list First U [p, 2]（It is not shown）There is provided and rise the signal Sa [p, 1] after sampling；Similarly, each follow-up unit U [p, i]（Wherein, i>1）Previous unit U [p, i-1] can be received（It is not shown）The signal Sa [p, i-1] of offer（It is not shown）, and provide frequency compared with High liter sampled signal Sa [p, i]（It is not shown）.Digital and analog interface circuit I A [p] can be modulated come the unit to end with difference The signal Sa [p, Nu] that U [p, Nu] is provided is modulated, to form the signal Sa [p, Nu+1] after modulation（Wherein, signal Sa [p, Nu+1] is data signal）, digital simulation level DAs [p] then the signal Sa [p, Nu+1] after modulation can be converted to signal Sa [p,Nu+2]（Wherein, signal Sa [p, Nu+2] is analog output signal）.
Each converter DAe [p] is divided into branch X1e [p] and branch X2e [p], branch X1e [p] and branch X2e [p] points It is not formed in chip 701 and chip 702.Include unit U [p, 1] using from the 1 mark ix selected into Nu, branch X1e [p] To unit U [p, ix] and code level Ea [p], wherein, code level Ea [p] is coupled to unit U [p, ix] and is connected circuit with across chip Between 711.Branch X2e [p] then includes unit U [p, ix+1] to unit U [p, Nu], digital and analog interface circuit I A [p], numeral Inert stage DAs [p] and decoding level Ga [p]；Wherein, decoding level Ga [p] is coupled to across chip connection circuit 712 and unit U [p, ix + 1] between.
To reach converter DA [p] translation function, the signal Sa provided by branch X1e [p] unit U [p, ix] [p, ix] need to be transmitted across chip to branch X2e [p] unit U [p, ix+1].To transfer signal Sa [p, ix], each converter DAe [p] code level Ea [p] can be encoded to signal Sa [p, ix], to provide encoded signal sc1 [p].For example, compile Each sample code in signal Sa [p, ix] can be the corresponding coded word in encoded signal sc1 [p] by code level Ea [p] （encoded word）.Correspondingly, across chip connection circuit 711 can be by branch X1e [1] to branch X1e [P] encoded signal Coded word in sc1 [1] to encoded signal sc1 [P] is gathered（collectively）Arrangement, to form string of the number as K Sf7 [1] is flowed to crossfire sf7 [K], and passes through data ball pin Da [1] to data ball pin Da [K] transmission stream sf7 [1] to crossfire sf7[K].Across chip connection circuit 712 can provide clock signal CK7 to across chip connection circuit 711；Clock signal CK7's Under SECO, across chip connection circuit 712 can receive crossfire sf7 [1] by data ball pin Db [1] to data ball pin Db [K] To crossfire sf7 [K], coded word is rearranged to the crossfire sf7 [1] to crossfire sf7 [K] received, and correspondingly obtains coding letter Number sc1 [1] to encoded signal sc1 [P].Therefore, each decoding level Ga [p]（Wherein, p=1~P）Just can be to the encoded signal of association Sc1 [p] enters row decoding, thinks that follow-up unit U [p, ix+1] obtains signal Sa [p, ix].For example, decoding encoded signal sc1 Each coded word in [p], to obtain the sampling in signal Sa [p, ix].
Nu special case is chosen to be for mark ix, branch X1e [p] possesses unit U [p, 1] to unit U [p, Nu], and wraps Code level Ea [p] is included, code level Ea [p] can be encoded to unit U [p, Nu] the signal Sa [p, Nu] provided, to form coding Signal sc1 [p].It is then not any between decoding level Ga [p] and digital and analog interface circuit I A [p] in branch X2e [p] Unit U [p, i]；Decoding level Ga [p] enters row decoding to the encoded signal sc1 [p] that across chip connection circuit 712 is obtained, and thinks number Word analog interface circuit IA [p] obtains signal Sa [p, Nu], therefore digital and analog interface circuit I A [p] and digital simulation level DAs [p] can continuously form signal Sa [p, Nu+2].
In signal processing system 700, each converter ADe [q]（Wherein, q=1~Q）Can be and poor Analog-digital Converter Device, can be converted to signal Sb [q, Nd+1] by signal Sb [q, 0]（Wherein, signal Sb [q, 0] is analog input signal, signal Sb [q, Nd+1] is digital output signal）, and including number for Nd concatenation frequency conversion cells D [q, 1] to cells D [q, Nd], A/D interface circuit I D [q], simulation numeral level ADs [q], code level Eb [q] with decoding level Gb [q].For response letter Number Sb [q, 0], simulation numeral level ADs [q] and A/D interface circuit I D [q] cooperating, with by intending with differential mode to number Word changes the signal Sb [q, 1] to form high sample frequency（Wherein, signal Sb [q, 1] is data signal）.Cells D [q, 1] can connect Collection of letters Sb [q, 1], and be follow-up cells D [q, 2]（It is not shown）Down-sampled signal Sb [q, 2] is provided；Similarly, after each Continuous cells D [q, j]（Wherein, j<1）Previous cells D [q, j-1] can be received（It is not shown）The signal Sb [q, j] of offer（Do not scheme Show）, and down-sampled signal Sb [q, j+1] is provided（It is not shown）, therefore the cells D [q, Nd] at end can be to digital interface circuit DI provides signal Sb [q, Nd+1].
Each converter ADe [q] is divided into branch Y1e [q] and branch Y2e [q], branch Y1e [q] and branch Y2e [q] points It is not formed in chip 701 and chip 702.Using from the 1 mark jx selected into Nd, branch Y2e [q] connects including simulation numeral Mouth circuit I D [q], simulation numeral level ADs [q], cells D [q, 1] to cells D [q, jx-1] and code level Eb [q]；Wherein, encode Level Eb [q] is coupled to cells D [q, jx-1] and is connected with across chip between circuit 712.Branch Y1e [q] then includes cells D [q, jx] To cells D [q, Nd], and decoding level Gb [q]；Wherein, decoding level Gb [q] is coupled to across chip connection circuit 711 and cells D Between [q, jx].
To reach converter Ad [q] translation function, the signal Sb provided by branch Y2e [q] cells D [q, jx-1] [q, jx] need to be transmitted across chip to branch Y1e [q] cells D [q, jx].For transmission signal Sb [q, jx], each converter ADe [q] code level Eb [q] can be encoded to signal Sb [q, jx], to provide encoded signal sc2 [q]；For example, by signal Each sample code in Sb [q, jx] is the coded word in encoded signal sc2 [q].Correspondingly, across chip connection circuit 712 can By the coding in branch Y2e [1] to branch Y2e [Q] converter ADe [Q] encoded signal sc2 [1] to encoded signal sc2 [Q] Word is gathered arrangement, to form K crossfire se7 [1] of number to crossfire se7 [K], and passes through data ball pin Db [1] to data Ball pin Db [K] difference transmission stream se7 [1] to crossfire se7 [K].Across chip connection circuit 711 can pass through data ball pin Da [1] Crossfire se7 [1] to crossfire se7 [K] is received to data ball pin Da [K], to the crossfire se7 [1] to crossfire se7 [K] that receives again Arranging and encoding word, and correspondingly obtain encoded signal sc2 [1] to encoded signal sc2 [Q].Therefore, each decoding level Gb [q]（Its In, q=1~Q）Just row decoding can be entered to the encoded signal sc2 [q] of association, thinks that follow-up cells D [q, jx] obtains signal Sb [q,jx]。
1 special case is chosen to be for mark jx, branch Y2e [q] is in A/D interface circuit I D [q] and code level Eb Any cells D [q, j] is not had between [q], code level Eb [q] is to simulation numeral level ADs [q] and A/D interface circuit I D The signal Sb [q, 1] of [q] is encoded, to provide encoded signal sc2 [q].Branch Y1e [q] include cells D [q, 1] to D [q, Nd] and decoding level Gb [q], it can enter row decoding to the encoded signal sc2 [q] that across chip connection circuit 711 is obtained, think leading Cells D [q, 1] formation signal Sb [q, 1].
The coding that code level Ea [p] is used with decoding level Ga [p] and code level Eb [q] with decoding level Gb [q] is with translating Ink recorder system can include：Data compression（compression）With decompression（decompression）, data scrambling （scrambling）Scrambled with solution（de-scrambling）, and/or other coding-decoding schemes, for example：Pass through mapping The character that each sampling is changed to most or least bits is penetrated to encode by reflection（inverse mapping）To translate Code.Data compression and decompression can be based on length of flow（run-length）Coding and decoding, and/or Huffman （Huffman）Coding and decoding etc., so that each sampling in signal Sa [p, ix] or signal Sb [q, jx] can be encoded as The less coded word of bit.The coding that code level Ea [p] is used with decoding level Ga [p] and decoding mechanism and code level Eb [q] Coding and decoding mechanism is used to be identical or different with decoding level Gb [q].
Using code level Ea [p], decoding level Ga [p], code level Eb [q] with decoding level Gb [q], clock signal CK7 when Clock rate rate and crossfire sf7 [1] to crossfire sf7 [K] and crossfire se7 [1] to crossfire se7 [K] handling capacity can be according at least one Individual factor is determined：Number P and Q value, number K value, encoded signal sc1 [p] and each coded word in encoded signal sc2 [q] （With checking information）Bit number, and signal Sa [p, ix] and signal Sb [q, jx] sample frequency.For example, examine Consider Fig. 1 and Fig. 7 two embodiments, it is assumed that number P, number Q, number N u, number N d and number K in two embodiments It is all identical, if code level Ea [p] and code level Eb [q] using data compression come in signal Sa [p, ix] and signal Sb [q, jx] Each sampling encoded to form shorter coded word in encoded signal sc1 [p] and encoded signal sc2 [q], then clock is believed Number CK7（As shown in Figure 7）Clock rate can be set to be less than clock signal CK1（As shown in Figure 1）Clock rate.Although Relatively low clock rate can reduce the cost of implementation of signal processing system 700, but set up the extra cloth of code level and decoding level Situation product may but reduce the benefit of cost reduction.Calculating cost estimate, which can calculate coding and decoding, really to subtract cost Less or increase.
It refer to Fig. 8；Fig. 8 is the schematic diagram of the signal processing system 800 according to embodiment of the present invention.Coordinate number N u =number N d=3 and a group selection（ix,jx,K）=（1,3,1）, the signal processing system 800 shown in Fig. 8 can be used to citing Illustrate the framework in Fig. 7.The range spans chip 801 of signal processing system 800 and chip 802, and including converter DAe [1] To converter DAe [P], converter ADe [1] to converter ADe [Q].Wherein, converter DAe [1] to converter DAe [P] is number Word analog converter；Converter ADe [1] to converter ADe [Q] is analog-digital converter.Each converter DAe [p]（Wherein, p =1~P）Signal Sa [p, 0] is received by digital interface circuit DI（Wherein, signal Sa [p, 0] is digital input signals）, and including The unit U [p, 1] to unit U [p, 3] of sampling is risen, therefore signal Sa [p, 0] can sequentially be converted into signal Sa by a liter sampling [p, 1], signal Sa [p, 2] and signal Sa [p, 3]；For example, signal Sa [p, 0], signal Sa [p, 1], signal Sa [p, 2] with Signal Sa [p, 3] sample frequency can be respectively fs, L*fs, L*M*fs and L*M*N*fs.Each converter ADe [q]（Wherein, q=1 ~Q）To signal Sb [q, 0]（Wherein, signal Sb [q, 0] is analog input signal）Carry out and differential mode is intended to numeral conversion, and phase Should ground offer signal Sb [q, 1]（Wherein, signal Sb [q, 1] is data signal）, and including down-sampled cells D [q, 1] to list First D [q, 3], therefore signal Sb [q, 1] can sequentially be converted into signal Sb [q, 2], signal Sb [q, 3] and signal Sb [q, 4]；Lift For example, signal Sb [q, 1], signal Sb [q, 2], signal Sb [q, 3] and signal Sb [q, 4] frequency can be L*M*N* respectively Fs, L*M*fs, L*fs and fs.
Signal processing system 800 is divided in the frequency interface associated with signal Sa [p, 1] and Sb [q, 3].Correspondingly, respectively Converter DAe [p] is divided into branch X1e [p] and branch X2e by across chip connection circuit 811 with being connected circuit 812 across chip [p], wherein, across chip connection circuit 811 is respectively formed in chip 801 and chip 802 with being connected circuit 812 across chip.Branch X1e [p] is formed in chip 801, including unit U [p, 1] and code level Ea [p].Unit U [p, 1] can provide signal Sa [p, 1]；Code level Ea [p] to signal Sa [p, 1] then to be encoded, to form encoded signal sc1 [p].Branch X2e [p] formation In chip 802, including decoding level Ga [p] and unit U [p, 2] to unit U [p, 3].Decoding level Ga [p] is used to decode coding letter Number sc1 [p] is to obtain signal Sa [p, 1]；Number K is chosen to be set as 1, and across chip connection circuit 811 can be by branch X1e [1] Encoded signal sc1 [1] to encoded signal sc1 [P] to branch X1e [P] is serialized as single crossfire sf8, and passes through chip 801 Single data ball pin Da [1] transfer out.Clock signal CK8 can be transmitted to chip by the clock signal ball pin B2 of chip 802 801 clock signal ball pin B1, under clock signal CK8 SECO, across chip connection circuit 812 can pass through chip 802 Single data ball pin Db [1] receive crossfire sf8, and crossfire sf8 is carried out to solve serial, to obtain encoded signal sc1 [1] to volume Code signal sc1 [P].
Similarly, each converter ADe [q] is segmented into branch Y1e [q] and branch Y2e [q], respectively by chip 801 and core Piece 802 is realized.Branch Y2e [q] includes cells D [q, 2], cells D [q, 1] and code level Eb [q]；Code level Eb [q] can be to letter Number Sb [q, 3] coding, to form encoded signal sc2 [q].Across chip connection circuit 812 can be by branch Y2e [1] to branch Y2e The encoded signal sc2 [1] to encoded signal sc2 [Q] of [Q] is serialized as single crossfire se8, and by the single data of chip 802 Ball pin Db [1] is transferred out.Across chip connection circuit 811 can receive crossfire by the single data ball pin Da [1] of chip 801 Se8, carries out solving serial, to obtain encoded signal sc2 [1] to encoded signal sc2 [Q] to crossfire se8.Branch Y1e [q] includes translating Code level Gb [q] and cells D [q, 3]；Decoding level Gb [q] row decoding can be entered to encoded signal sc2 [q], with obtain signal Sb [q, 3]。
Be not limited to Fig. 8 example, suitably change Fig. 7 frameworks setting selection, code level Ea [p], code level Eb [q] with Decoding level Ga [p], decoding level Gb [q] can be also included in Fig. 2 to Fig. 6 example.
Although two chips of the range spans of Fig. 1 to Fig. 8 each signal processing system, signal processing system of the present invention also may be used It is distributed in more chips, such as three chips.For example, each converter DA [p] can be divided into branch X1 [p], branch X2 [p] and branch X3 [p], is respectively formed in three chips（It is not shown）；Branch X1 [p] include unit U [p, 1] to unit U [p, Ix1], branch X2 [p] includes unit U [p, ix1+1] to unit U [p, ix2], and branch X3 [p] includes unit U [p, ix2+1] extremely Unit U [p, Nu], digital and analog interface circuit I A [p] and digital simulation level DAs [p].By unit U [p, ix] export signal by First across chip connection circuit is connected circuit with second across chip（It is respectively formed in the first chip and the second chip）Transmit to list First U [p, ix1+1]；Electricity is then connected across chip with the 4th by the 3rd across chip connection circuit by unit U [p, the ix2] signals exported Road（It is respectively formed in the second chip and the 3rd chip）Transmit to unit U [p, ix2+1].
According to the embodiment of the present invention there is provided a kind of signal processing method, including：Arrange multiple converters（As changed Device DA [1] to converter DA [P] and/or converter AD [1] to converter AD [Q]）, each converter（Such as converter DA [p] turns Parallel operation AD [q]）It is divided into the first branch being formed in the first chip（Such as branch X1 [p] or branch Y1 [q]）With being formed at The second branch in second chip（Such as branch X2 [p] or branch Y2 [q]）, and by formed with the first chip in first across Chip connect circuit be formed in the second chip second across chip be connected circuit, in the first branch and second of each converter The M signal is transmitted between branch（Such as signal Sa [p, ix] or signal Sb [q, jx]）.Wherein, each converter receives input letter Number, and output signal is correspondingly provided by the conversion between data signal and analog signal；First branch and the second branch One of converted input signal sample frequency, to provide the M signal of different sample frequencys.
The 9th figure is refer to, Fig. 9 is the design cycle of optimization embodiment of the present invention.Flow 900 can be used to determine as how More excellent cost realizes distributed signal processing system；For example, how to design or produce the minimum signal as shown in Figure 1 of cost Processing system 100 or signal processing system 700 as shown in Figure 7.The key step of flow 900 can be described as follows.
Step 902：Arrange multiple converters that can be changed between analog signal and data signal, and each converter It is associated with the frequency interface of multiple different frequencies.Specifically, the basis of signal processing system is determined, including：Signal transacting system The number of converter in system（Such as the number P and the number Q of analog-digital converter of digital analog converter in Fig. 1 or Fig. 7）, with And each converter includes the number of frequency translation unit（For example, single in each digital analog converter as shown in Fig. 1 or Fig. 7 The number N u of first U [p, i] and the number N d of cells D [q, j] in each analog-digital converter）.In addition, determining signal processing system Which kind of technique first chip of middle distribution is respectively adopted to make with the second chip.Using frequency translation unit, each digital simulation Converter is associated with the frequency interface of multiple different frequencies with analog-digital converter.
Step 904：Initialize for indicating where each converter（Analog-digital converter and digital-to-analogue conversion Device）The selection of the first branch and the second branch is divided into, and how selection instruction is will be in paired the first branch and second Across chip connection is set up between branch.For example, the selection may include mark ix, mark jx and the number as shown in Fig. 1 or Fig. 7 K setting selection.Whether the selection may also comprise to add in each digital analog converter and analog-digital converter and encodes The setting selection of level/decoding level；Which that is, it can also indicate that in the selection using in the structure shown in Fig. 1 and Fig. 7.
Step 906：According to the selection of previous step, segmentation converter step is carried out, to obtain following plan.The plan For the first branch and the second core being divided into each converter at the selected frequency interface in each converter in the first chip The second branch in piece, and be K across under chip wiring will be all using appropriate clock rate and handling capacity in number First branch is communicated with the second branch.In addition, the plan may also comprise：Whether embedded coding level/decoding level, and how Embedded coding level/decoding level.
Step 908：With computer, cost estimate step is carried out, to calculate the totle drilling cost needed for following item：First All first branches are formed in chip, all second branches are formed in the second chip, and using the number K in foregoing selection as institute There is the signal transmission between the first branch and the second branch to realize across chip connection.
Step 910：If still there is another different selection, correspondingly repeat step 906, otherwise go to step 912.Cause This, step 906 is just may be repeated several times with step 908 to obtain several costs, and each cost is calculated under a different selection 's.To provide different selections, following one or more operations can be carried out：Change each digital analog converter and/or each mould Intend the dividing frequency interface that digital quantizer is selected（For example, changing mark ix and/or jx）, and change number K value.Lift For example, the corresponding selection of embodiment shown in Fig. 2 to Fig. 6（ix,jx,K）=（2,2,1）、（1,3,1）、（3,1,1）、（1, 2,1）With（2,3,1）.Therefore, step 906 is repeatable five times with step 908, obtains five costs.Different selections can also be wrapped Include：Select one in two kinds of structures shown in Fig. 1 and Fig. 7；So as to assess and compare the corresponding cost of the structure shown in Fig. 1 with The corresponding cost of structure shown in Fig. 7.
Step 912：After repeat step 906 and step 908, compare the various costs for calculating and obtaining, then by calculating Machine carries out cost comparison, optimal to select（It is minimum）The selection of cost of implementation.For example, design cycle 900 can be for Fig. 2 extremely Fig. 4 three kinds of selections calculate three corresponding costs, if Fig. 2（ix,jx,K）Selection can be corresponded to minimum cost, so that it may adopted Realize that three-level rises sampling/down-sampled numeral being changed between simulation with Fig. 2 selection.
In a word, the present invention by using with poor digital-to-analogue conversion with and poor Analog-digital Converter under it is multistage rise sampling and It is down-sampled there is provided enough flexibilities, to optimize the signal processing system across chip distribution.Such a optimization can be in various influences Factor（For example, across chip handling capacity and clock rate, layout area, pin number（Ball pin number）With the technique for manufacturing chip）Between Reach preferably（Or it is optimal）Balance.
Although the present invention is disclosed above in a preferred embodiment thereof, but have to be understood that it is not limited to the present invention. On the contrary, any those skilled in the art, without departing from the spirit and scope of the present invention, when a little change and retouching can be done, because The protection domain that this protection scope of the present invention should be defined by claims is defined.

Claims (23)

1. a kind of signal processing system, it is characterised in that the chip of range spans first and the second chip, the signal processing system bag Include：
First across chip connection circuit, is formed in first chip,
Second across chip connection circuit, is formed in second chip, and is coupled to first across the chip connection circuit, and
The multiple converters changed between data signal and analog signal；Any converter bag in the plurality of converter Include：
Multiple units of the concatenation of multiple frequency interfaces are formed, different frequency interface is associated with different frequency respectively, and this is more Any cell in the individual unit conversion frequency between two continuous side frequency interfaces；
Wherein, the corresponding frequency of first across the chip connection circuit and second across the chip connection circuit in any converter Any converter is divided into the first branch and the second branch by interface, first branch of any converter with this second Branch is respectively formed in first chip and second chip, and first across the chip connection circuit and this second across chip Connection circuit transmits signal between first branch and second branch of any converter.
2. signal processing system according to claim 1, it is characterised in that the plurality of converter includes digital-to-analogue conversion Digital input signals are converted to analog output signal by device, the digital analog converter, and the digital analog converter enters one Step includes：
Digital and analog interface circuit, is coupled to the unit at the end of the digital analog converter, and
Digital simulation level, couples the digital and analog interface circuit；
Wherein, the leading unit in the digital analog converter receives the digital input signals and correspondingly provides first and believes Number；Any cell after the leading unit receives the signal that previous unit is provided；The digital and analog interface circuit use and The signal that the unit at the end is provided is modulated by difference modulation, to form the signal after modulation, and digital simulation level Signal after this is modulated is converted to the analog output signal.
3. signal processing system according to claim 2, it is characterised in that
The sample frequency of first signal is higher than the sample frequency of the data input signal；And
The signal that the sample frequency of the signal that any cell after the leading unit the is provided unit more previous than this is provided Sample frequency it is high.
4. signal processing system according to claim 1, it is characterised in that the plurality of converter includes Analog-digital Converter Analog input signal is converted to digital output signal by device, the analog-digital converter, and the analog-digital converter enters one Step includes：
A/D interface circuit, is coupled to the leading unit of the analog-digital converter, by providing modulation with difference modulation Secondary signal afterwards is to respond the analog input signal；
Wherein, the leading unit in the analog-digital converter receives the secondary signal and correspondingly provides the 3rd signal； Any cell between the unit of the leading unit with end receives the signal that its corresponding previous unit is provided, and phase Ground is answered to provide signal to follow-up unit；And the unit at the end receives signal and the phase that its corresponding previous unit is provided Ground is answered to provide the digital output signal.
5. signal processing system according to claim 4, it is characterised in that
The sample frequency of 3rd signal is lower than the sample frequency of the secondary signal；
The sample frequency previous unit more corresponding than its for the signal that any cell after the leading unit is provided is provided Signal sample frequency it is low；And
The signal that the sample frequency previous unit more corresponding than its for the digital output signal that the unit at the end is provided is provided Sample frequency it is low.
6. signal processing system according to claim 1, it is characterised in that：
Any first kind converter that the plurality of converter is included in multiple first kind converters, the plurality of first kind converter is carried Transmitted for the first branch from any first kind converter to the second branch first across cell signal；
First across the chip connection circuit arrangement multiple first is across the sampling in cell signal, to form multiple first crossfires, and The plurality of first crossfire is transmitted respectively by multiple first data ball pin on first across the chip connection circuit；And
By the multiple second data ball pin coupled respectively with the plurality of first data ball pin on second across the chip connection circuit, Second across the chip connection circuit receives the plurality of first crossfire, rearranges the sampling in the plurality of first crossfire, and accordingly Ground obtains the plurality of first across cell signal for multiple second branches of the plurality of first kind converter.
7. signal processing system according to claim 6, it is characterised in that：
Checking information is further attached to by first across the chip connection circuit according to the plurality of first across cell signal The plurality of first crossfire, and
When second across the chip connection circuit obtain the plurality of first it is across cell signal when, second across the chip connection circuit enters one Walk and received the plurality of first crossfire is corrected according to the checking information.
8. signal processing system according to claim 6, it is characterised in that the number of the plurality of first kind converter is the One number；The number of the plurality of second branch of the plurality of first kind converter is first number；The plurality of first across unit The number of signal is first number；The number of the plurality of first data ball pin is the 3rd number；The plurality of second data ball pin Number be the 3rd number；The number of the plurality of first crossfire is the 3rd number.
9. signal processing system according to claim 8, it is characterised in that the 3rd number is less than first number.
10. signal processing system according to claim 6, it is characterised in that：
Any first kind converter in the plurality of first kind converter further comprises：
First code level, in the first branch of any first kind converter, and
First decoding level, in the second branch of any first kind converter；
Wherein, first across the unit letter of first code level of any first kind converter to any first kind converter Number encoded, to provide the first encoded signal；
Multiple first encoded signals of first across the chip the plurality of first kind converter of connection circuit arrangement, it is the plurality of to be formed First crossfire,
Second across the chip connection circuit rearranges the plurality of first crossfire, and is correspondingly the plurality of first kind converter The plurality of second branch obtains the plurality of first encoded signal, and,
The first decoding level of any first kind converter enters row decoding to corresponding first encoded signal, think this any the Second branch of one class converter obtains this first across cell signal.
11. signal processing system according to claim 10, it is characterised in that the number of the plurality of first kind converter is First number；The number of the plurality of second branch of the plurality of first kind converter is first number；The plurality of first across list The number of first signal is first number；The number of the plurality of first encoded signal is first number；The plurality of first data The number of ball pin is the 3rd number；The number of the plurality of second data ball pin is the 3rd number；The number of the plurality of first crossfire Mesh is the 3rd number.
12. signal processing system according to claim 6, it is characterised in that：
The plurality of converter further comprises that any Equations of The Second Kind in multiple Equations of The Second Kind converters, the plurality of Equations of The Second Kind converter turns Parallel operation is provided to be transmitted to the first branch second across cell signal from the second branch of any Equations of The Second Kind converter,
Second across the chip connection circuit arrangement multiple second is across the sampling in cell signal, to form multiple second crossfires；Should Second across chip connection circuit further transmits the plurality of second crossfire respectively by the plurality of second data ball pin, and
First across the chip connection circuit further receives the plurality of second crossfire by the plurality of first data ball pin, and arranges again The sampling in the plurality of second crossfire is arranged, and correspondingly obtains this respectively for multiple first branches of the plurality of Equations of The Second Kind converter Multiple second across cell signal.
13. signal processing system according to claim 12, it is characterised in that：
Second across the chip connection circuit is further attached by the second checking information across cell signal according to the plurality of second The plurality of second crossfire is added to, and
When first across the chip connection circuit obtain the plurality of second it is across cell signal when, first across the chip connection circuit enters one Walk and received the plurality of second crossfire is corrected according to second checking information.
14. signal processing system according to claim 12, it is characterised in that the number of the Equations of The Second Kind converter is second Number；The number of the plurality of first branch of the plurality of Equations of The Second Kind converter is second number；The plurality of second across unit letter Number number be second number；The number of the plurality of first data ball pin is the 3rd number；The plurality of second data ball pin Number is the 3rd number；The number of second crossfire is the 3rd number；The number of second crossfire and first crossfire Number is equal.
15. signal processing system according to claim 14, it is characterised in that the 3rd number is less than second number.
16. signal processing system according to claim 12, it is characterised in that：
Any Equations of The Second Kind converter in the plurality of Equations of The Second Kind converter further comprises：
Second code level, in the second branch of any Equations of The Second Kind converter, and
Second decoding level, in the first branch of any Equations of The Second Kind converter；
Wherein, second across the unit letter of second code level of any Equations of The Second Kind converter to any Equations of The Second Kind converter Number encoded, to provide the second encoded signal；
The plurality of second encoded signal of second across the chip the plurality of Equations of The Second Kind converter of connection circuit arrangement is more to form this Individual second crossfire,
First across the chip connection circuit rearranges the plurality of second crossfire, and is correspondingly the plurality of Equations of The Second Kind converter The plurality of first branch obtains the plurality of second encoded signal, and
The second decoding level of any Equations of The Second Kind converter enters row decoding to corresponding second encoded signal, think this any the First branch of two class converters obtains this second across cell signal.
17. signal processing system according to claim 16, it is characterised in that the number of the Equations of The Second Kind converter is second Number；The number of the plurality of first branch of the plurality of Equations of The Second Kind converter is second number；The plurality of second across unit letter Number number be second number；The number of the plurality of second encoded signal is second number；The plurality of first data ball pin Number be the 3rd number；The number of the plurality of second data ball pin is the 3rd number；The number of second crossfire for this Three numbers；The number of second crossfire is equal with the number of first crossfire.
18. signal processing system according to claim 12, it is characterised in that split the frequency of any first kind converter The frequency of frequency interface of the frequency of rate interface with splitting any Equations of The Second Kind converter is identical or different.
19. signal processing system according to claim 12, it is characterised in that the plurality of first across cell signal sampling Frequency with the plurality of second across cell signal sample frequency it is equal or different.
20. a kind of signal processing method, it is characterised in that the signal processing method realizes the chip of range spans first and the second core The signal processing system of piece, the signal processing method includes：
Arrange any converter in multiple converters, the plurality of converter to receive input signal, and pass through data signal and mould Intend the conversion between signal and output signal is correspondingly provided, wherein, any converter, which is divided into, is formed at first core The first branch in piece and the second branch being formed in second chip, and first branch and second branch wherein it One changes the sample frequency of the input signal, to provide the M signal of different sample frequencys；And
By the be formed in first chip first across chip connection circuit and be formed in second chip second across core Piece connects circuit, and the M signal is transmitted between first branch and second branch of any converter.
21. signal processing method according to claim 20, it is characterised in that the M signal of any converter The sample frequency is 4 to 16 times of the sample frequency of the input signal of any converter.
22. signal processing method according to claim 20, it is characterised in that the plurality of converter includes multiple numerals Any digital analog converter in analog converter, the plurality of digital analog converter includes multiple liters of sampling filters, Any liter of sampling filter increase sample frequency in the plurality of liter of sampling filter.
23. signal processing method according to claim 20, it is characterised in that the plurality of converter includes multiple simulations Any analog-digital converter in digital quantizer, the plurality of analog-digital converter includes multiple desampling fir filters, Any desampling fir filter in the plurality of desampling fir filter reduces sample frequency.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1536933A (en) * 2003-04-08 2004-10-13 联发科技股份有限公司 Direct flow digital technique and data flow treatment system
CN101807426A (en) * 2009-02-13 2010-08-18 瑞昱半导体股份有限公司 Audio device and audio processing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323379C (en) * 2003-04-02 2007-06-27 友达光电股份有限公司 Data driving circuit and its method of driving data
US7569836B2 (en) * 2006-05-05 2009-08-04 Virgin Islands Microsystems, Inc. Transmission of data between microchips using a particle beam
US8331887B2 (en) * 2009-12-30 2012-12-11 Silicon Laboratories Inc. Antenna diversity system with multiple tuner circuits having multiple operating modes and methods

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1536933A (en) * 2003-04-08 2004-10-13 联发科技股份有限公司 Direct flow digital technique and data flow treatment system
CN101807426A (en) * 2009-02-13 2010-08-18 瑞昱半导体股份有限公司 Audio device and audio processing method

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